coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2016-08-02	arch/riscv: Add include/arch/barrier.h	Jonathan Neuschäfer
2016-07-14	spike-riscv: Look for the CBFS in RAM	Jonathan Neuschäfer
2016-06-17	Define RAMTOP for x86 only	Kyösti Mälkki
2016-04-28	Add board URLs for the RISC-V boards	Jonathan Neuschäfer
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-09-16	riscv-memlayout: fix existing memlayout issues, add sbi interface	Thaminda Edirisooriya
2015-06-08	Remove empty lines at end of file	Elyes HAOUAS
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2015-04-18	kconfig: automatically include mainboards	Stefan Reinauer
2015-04-17	uart: pass register width in the coreboot table	Vadim Bendebury
2015-04-14	CBFS: Automate ROM image layout and remove hardcoded offsets	Julius Werner
2015-04-06	New mechanism to define SRAM/memory map with automatic bounds checking	Julius Werner
2015-03-20	bootblocks: use run_romstage()	Aaron Durbin
2015-03-20	romstages: use common run_ramstage()	Aaron Durbin
2014-12-04	RISCV: get RISCV to build again	Ronald G. Minnich
2014-12-01	Add UCB RISCV support for architecture, soc, and emulation mainboard..	Ronald G. Minnich