summaryrefslogtreecommitdiff
path: root/src/mainboard/emulation/qemu-riscv
AgeCommit message (Expand)Author
2016-10-24RISCV: Clean up the common architectural codeRonald G. Minnich
2016-10-15riscv: Use the generic src/lib/bootblock.cJonathan Neuschäfer
2016-10-15riscv: Clean up {qemu,spike}_utilJonathan Neuschäfer
2016-10-15riscv and power8: Convert printk/while(1) to dieJonathan Neuschäfer
2016-08-19qemu-riscv: Remove obsolete CSR - send_ipiMartin Roth
2016-08-18Kconfig: lay groundwork for not assuming SPI flash boot deviceAaron Durbin
2016-08-02arch/riscv: Add include/arch/barrier.hJonathan Neuschäfer
2016-07-14spike-riscv: Look for the CBFS in RAMJonathan Neuschäfer
2016-06-17Define RAMTOP for x86 onlyKyösti Mälkki
2016-04-28Add board URLs for the RISC-V boardsJonathan Neuschäfer
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
2015-09-16riscv-memlayout: fix existing memlayout issues, add sbi interfaceThaminda Edirisooriya
2015-06-08Remove empty lines at end of fileElyes HAOUAS
2015-05-21Remove address from GPLv2 headersPatrick Georgi
2015-04-18kconfig: automatically include mainboardsStefan Reinauer
2015-04-17uart: pass register width in the coreboot tableVadim Bendebury
2015-04-14CBFS: Automate ROM image layout and remove hardcoded offsetsJulius Werner
2015-04-06New mechanism to define SRAM/memory map with automatic bounds checkingJulius Werner
2015-03-20bootblocks: use run_romstage()Aaron Durbin
2015-03-20romstages: use common run_ramstage()Aaron Durbin
2014-12-04RISCV: get RISCV to build againRonald G. Minnich
2014-12-01Add UCB RISCV support for architecture, soc, and emulation mainboard..Ronald G. Minnich