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path: root/src/mainboard/emulation/spike-riscv
AgeCommit message (Expand)Author
2018-11-28mb/*/*/Kconfig: Remove useless commentElyes HAOUAS
2018-10-29Documentation/mainboard: Add emulation/spike-riscv.mdJonathan Neuschäfer
2018-10-22mainboard/: Select MISSING_BOARD_RESET appropriatelyNico Huber
2018-10-06mb/emulation/*-riscv: Remove "UCB" from RISC-V board namesJonathan Neuschäfer
2018-06-09mainboard: Get rid of device_t in ramstageElyes HAOUAS
2018-06-02src/mainboard: Add and update license headersMartin Roth
2018-04-27RISC-V boards: Remove PAGETABLES section from memlayout.ldJonathan Neuschäfer
2018-04-25util/riscvtools: Rename to util/riscv/Jonathan Neuschäfer
2018-02-20mb/emu/spike-riscv: Move usage instructions into Kconfig helpJonathan Neuschäfer
2017-11-07RISC-V boards: Stop using the config stringJonathan Neuschäfer
2017-09-27mb/emu/*-riscv: Remove outdated memory mapJonathan Neuschäfer
2017-06-12mb/emulation/spike-riscv: Update UART addressJonathan Neuschäfer
2017-02-23mb/emulation/*-riscv: Don't select ARCH_BOOTBLOCK_RISCVJonathan Neuschäfer
2017-01-16riscv/spike: Remove obsolete DRAM_SIZE_MB settingJonathan Neuschäfer
2016-11-12riscv: start to use the configstring functionsRonald G. Minnich
2016-11-07riscv: Unify SBI call implementations under arch/riscv/Jonathan Neuschäfer
2016-10-24RISCV: Clean up the common architectural codeRonald G. Minnich
2016-10-15riscv: Use the generic src/lib/bootblock.cJonathan Neuschäfer
2016-10-15riscv: Clean up {qemu,spike}_utilJonathan Neuschäfer
2016-10-15riscv and power8: Convert printk/while(1) to dieJonathan Neuschäfer
2016-08-23arch/riscv: Implement the SBI againJonathan Neuschäfer
2016-08-18Kconfig: lay groundwork for not assuming SPI flash boot deviceAaron Durbin
2016-08-02arch/riscv: Add include/arch/barrier.hJonathan Neuschäfer
2016-07-14spike-riscv: Look for the CBFS in RAMJonathan Neuschäfer
2016-07-14spike-riscv: Register RAM resource at 0x80000000Jonathan Neuschäfer
2016-07-12spike-riscv: Remove HTIF related codeJonathan Neuschäfer
2016-06-21riscv-spike: Move coreboot to 0x80000000 (2GiB)Jonathan Neuschäfer
2016-06-17Define RAMTOP for x86 onlyKyösti Mälkki
2016-06-12riscv-spike: Replace custom UART with a memory-mapped 8250Jonathan Neuschäfer
2016-04-28Add board URLs for the RISC-V boardsJonathan Neuschäfer
2016-04-28Fix "Spike RISCV" board nameJonathan Neuschäfer
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
2015-09-16riscv-memlayout: fix existing memlayout issues, add sbi interfaceThaminda Edirisooriya
2015-09-10riscv-trap-handling: Add implementation for trap calls in riscvThaminda Edirisooriya
2015-08-09riscv-spike: support for Spike emulation of riscvThaminda Edirisooriya