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Change-Id: Ie21c390ab04adb5b05d5f9760d227d2a175ccb56
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Use common code to detect ACPI S3.
Tested on Thinkpad X60.
Change-Id: Ia759a9ed141efc8130860300f2a8961f0c084d70
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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PCI config accessors are no longer indirectly included
from <arch/io.h> use <device/pci_ops.h> instead.
Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Was tested with the following:
- 2 DIMM slots
- USB
- Ethernet NIC
- automatic fan control
- Libgfxinit with VGA, DVI (HDMI slot unpopulated)
- PS2 Keyboard
- SATA
- PEG
- S3 resume
What does not work:
- Using the second DIMM slot on a channel
G41 can only handle 2 ranks per channel and on this mainboard 1 rank
per DIMM slot. Supporting this would require too much raminit rework
and is not worth it (at least for me)
Change-Id: I67784038ef929f561b82365f00db70a69c024321
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: Iacbee658a4049e1c13a120dbc21425ffb6a1cabb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The initial timestamps are now pushed on the stack when entering the
romstage C code.
Tested on Asus P5QC.
Change-Id: I88e972caafff5c53d8e68e85415f920c7341b92d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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This removes the need to synchronize the devicetree and the romstage
writing to FD.
Change-Id: I83576599538a02d295fe00b35826f98d8c97d1cf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30244
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Things cleaned up in this patch:
* Add macros for the GENx_DEC registers;
* replace many magic numbers by macros;
* remove many writes to DxxIP since they were 'setting' reset default
values;
* fix some comments about decode ranges.
Change-Id: I9d6a0ff3d391947f611a2f3c65684f4ee57bc263
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Especially on ICH7 failing to do so results in i2c block read being
unusable. On ICH10 this problem doesn't manifest itself that much.
This moves disabling the watchdog reboot to the northbridge code like
i945 (even though it technically is southbridge stuff).
TESTED on Intel DG41WV: hacking on raminit is much nicer since no
need to do a hard power down for +4s are needed to clear the timeouts.
Change-Id: Icfd3789312704f61000a417f23a121d02d2e7fbe
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Based on the Intel G41 chipset, ICH7 southbridge, and IT8720F Super I/O.
Tested, working:
* Booting Linux 4.11.3 and Windows 8.1 from USB and HDD
* Resume from S3 (Linux and Windows)
* Native raminit (DDR2-800)
* Native graphics init (SeaBIOS, Linux)
* Graphics init with VGA BIOS (SeaBIOS, Windows)
* PCI-E x16 PEG slot, PCI-E x1 slot from southbridge
* Realtek ALC888 HD Audio (including front panel and jack detection)
* Realtek R8168 Gigabit LAN
* Both SATA ports
* USB 1.1 and 2.0 devices (keyboard, mass storage)
* PC speaker beep
* COM header
* Super I/O Environment controller (temps, voltage, fans)
* PS/2 keyboard and mouse
* Flashing with `flashrom -p internal`
* 1MiB and 2MiB SPI flash chips
* CMOS gfx_uma_size
Appears, OS driver loads, but otherwise untested:
* IrDA header
* CIR header
* TPM header
Untested:
* S/PDIF digital audio
Tested, known broken:
* CMOS power_on_after_fail
* USB keyboard in secondary payloads
Change-Id: Ifc4c8935b1a11e55f4bf6cfa484a8a8d09b1adda
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-on: https://review.coreboot.org/20027
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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