summaryrefslogtreecommitdiff
path: root/src/mainboard/foxconn/g41s-k
AgeCommit message (Expand)Author
2020-06-19Kconfig: Escape variable to accommodate new Kconfig versionsPatrick Georgi
2020-06-15x4x boards: Factor out MAX_CPUSAngel Pons
2020-05-18mainboard/*/*/Kconfig*: Remove leading blank lines from SPDX headerElyes HAOUAS
2020-05-18src: Remove leading blank lines from SPDX headerElyes HAOUAS
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
2020-05-10src/mainboard: Replace GPLv2 long form headers with SPDX headerElyes HAOUAS
2020-05-09src/: Replace GPL boilerplate with SPDX headersPatrick Georgi
2020-05-06treewide: replace GPLv2 long form headers with SPDX headerPatrick Georgi
2020-05-06treewide: Move "is part of the coreboot project" line in its own commentPatrick Georgi
2020-05-02acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh
2020-04-04mainboard/foxconn: Use SPDX for GPL-2.0-only filesAngel Pons
2020-03-20mb/**/gma-mainboard.ads: Use SPDX for GPL-2.0-or-laterAngel Pons
2020-03-18mainboard/[a-f]*: Remove copyright noticesPatrick Georgi
2020-01-13mb/foxconn/g41s-k/acpi_tables.c: Remove unneeded includesElyes HAOUAS
2020-01-02mb/*/*/acpi_tables: Remove unused includesElyes HAOUAS
2019-12-31mb/*/*/acpi_tables: Don't zero out gnvs againPeter Lemenkov
2019-12-31mb/**/dsdt.asl: Remove outdated sleepstates.asl commentAngel Pons
2019-12-16arch/x86: Make X86 stages select ARCH_X86Arthur Heymans
2019-11-15nb/intel/x4x: Move to C_ENVIRONMENT_BOOTBLOCKArthur Heymans
2019-11-15nb/intel/x4x: Move boilerplate romstage to a common locationArthur Heymans
2019-11-14mb/*/*(ich7/x4x): Use common early southbridge initArthur Heymans
2019-11-12sb/intel/i82801gx: Add common LPC decode codeArthur Heymans
2019-11-11mb/{x4x}: Remove unused 'include <northbridge/intel/x4x/iomap.h>'Elyes HAOUAS
2019-11-04mb/*/*{i82801gx}: Use sb/intel/common/acpi/platform.aslArthur Heymans
2019-11-03mb/intel/{i82801gx,x4x}: Don't select ASPM optionsArthur Heymans
2019-11-01soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpiSubrata Banik
2019-10-11sb/intel/i82801gx: Move CIR init to a common placeArthur Heymans
2019-08-26soc/intel: Use common romstage codeKyösti Mälkki
2019-08-18cpu/intel: Enter romstage without BISTKyösti Mälkki
2019-06-06sb/intel/i82801gx: Detect if the southbridge supports AHCIArthur Heymans
2019-06-05mb/*/devicetree.cb: Remove unavailable PCIe portsArthur Heymans
2019-04-23src: Add missing include 'console.h'Elyes HAOUAS
2019-04-13sb/intel/i82801gx: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIBPatrick Rudolph
2019-03-18mb/foxconn/g41m: Fix overridetreeKyösti Mälkki
2019-03-13src/mainboard/*/*/cstates.c: Drop unused includesElyes HAOUAS
2019-03-13{mb,nb/pineview}/*.asl: Remove unneeded include i82801gx.hElyes HAOUAS
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
2019-03-01device/pci: Fix PCI accessor headersKyösti Mälkki
2019-01-23nb/intel/x4x: Use parallel MP initArthur Heymans
2019-01-10mb/foxconn/g41s-k: Add g41m variantArthur Heymans
2019-01-10mb: Move timestamp_add_now to northbridge x4xElyes HAOUAS
2019-01-09cpu/intel: Use the common code to initialize the romstage timestampsArthur Heymans
2019-01-08sb/intel/i82801gx: Autodisable functions based on devicetreeArthur Heymans
2018-12-19mb/foxconn/g41s-k: Don't reprogram inherited subsystemidArthur Heymans
2018-11-23mb: Set coreboot as DSDT's manufacturer model IDElyes HAOUAS
2018-11-21ACPI: Fix DSDT's revision fieldElyes HAOUAS
2018-11-12mb/*/*: Harmonise FD and devicetree on boards featuring ICH7Arthur Heymans
2018-08-15mb/*/*/cmos.default: Decrease debug_level to 'Debug'Elyes HAOUAS
2018-06-29sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tablesArthur Heymans
2018-06-14nb/intel/x4x: Deprecate native graphic initArthur Heymans
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-31 15:56:33 +0000