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path: root/src/mainboard/google/fizz
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2018-11-16mb/google/kalista: Disable EC-EFSDaisuke Nojiri
Only input from the BJ port is wired to VSYS on Kalista. VBUS from USB-C is for output only. In other words, Kalista is a source only device from a USB/PD perspective. This patch disables EC-EFS, which would be needed for the EC to jump to RW to get PD power before the AP boots. Kalista will be always supplied enough power to boot the AP through the BJ port. CQ-DEPEND=CL:1330171 BUG=b:118386511 BRANCH=none TEST=Boot Fizz. Verify normal boot, soft sync, recovery mode work. Change-Id: Icd18662ae1e76f35eb9bcd521b1951aacc713252 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/29564 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-07mb/google/fizz: Comment variant names in KconfigDavid Wu
Refer to CL:1043916 BUG=none BRANCH=none TEST=none Change-Id: I3fbbbcac334646f68b8b9fd38fbb529d9e833581 Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-05mb/google/fizz: Remove variant_cros_gpios from variantDavid Wu
This change removes the function defintions from variant so that the weak definition in baseboard can be used. Refer to CL:813944. BUG=none BRANCH=master TEST=Build and boot on DUT Change-Id: I561414fcc94e3c812bb88730df9b94e332c61781 Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-05mb/google/fizz/variants/karma: Update GPIO GPP_D9David Wu
Update GPP_D9 to fix audio jack can't detect issue. BUG=b:118393646 BRANCH=master TEST=Verify audio jack can auto detect. Change-Id: I87d24ed294c1ddc59bbd6ba9194c76d1f66413f3 Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-01mb/google/fizz/variants/karma: Rename kalista to karmaDavid Wu
Change the variant name from kalista to karma. According to the CL:1298319, the baseboard name is kalista and the board name is karma. BUG=none BRANCH=master TEST=emerge-kalista coreboot chromeos-bootimage Change-Id: Idea295cc14249721a6dc0fc4e2ef6470d43e16eb Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29314 Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-25mb/google/fizz/variants/kalista: Add variant for kalistaDavid Wu
Add a new variant of fizz for the kalista board. Key differences from baseboard include: - GPIO changes - devicetree.cb changes BUG=b:117066935 BRANCH=master TEST=Build (as initial setup) Change-Id: I808c5e0883049575cbedd181c249a78a833fa96a Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29205 Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-25mb/google/fizz: Enable use of override devicetreeFurquan Shaikh
This change enables override device tree for Fizz to allow variants to provide their own overrides and also moves I2C5 realtek node to fizz/overridetree.cb since it doesn't apply to some variants being added for Fizz. Change-Id: Ia1a069fc539b51a22882ef94b55baf5bf7cd302f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/29242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2018-10-19mb/google/fizz: Provide nhlt variant APIDavid Wu
Move current NHLT configuration implementation to baseboard so that variants can leverage it or provide their own configuration. BUG=b:117066935 BRANCH=Fizz TEST=emerge-fizz coreboot Change-Id: I30d93babb6fc09e8642b3740f1f7638fa33f0ade Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28965 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-19mb/google/fizz: Provide cros_gpio variant APIDavid Wu
Add support for ChromeOS GPIO ACPI table information by providing weak implementation from the baseboard. BUG=b:117066935 BRANCH=Fizz TEST=emerge-fizz coreboot Change-Id: I2fa52c005cacdbcc322d107a3ac92d22df3f3697 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-19mb/google/fizz: Add variant API for gpioDavid Wu
Provide API for gpio table functionality. Default weak implementations are provided from the baseboard. BUG=b:117066935 BRANCH=Fizz TEST=emerge-fizz coreboot Change-Id: Iaafa8d6932bc0a37826175b15816f1b9a4f4c314 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-19mb/google/fizz: Provide baseboard and variant conceptsDavid Wu
In order to be able to share code across different fizz variants, provide the concept of baseboard and variants. New directory layout: variants/baseboard - code variants/baseboard/include/baseboard - headers variants/fizz - code variants/fizz/include/variant - headers New boards would then add themselves under their board name within "variants" directory. This is purely an organizational change. BUG=b:117066935 BRANCH=Fizz TEST=emerge-fizz coreboot CQ-DEPEND=CL:1273514 Change-Id: I28cc41681e7af88ddeba2e847dc0a4686606feb2 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-10mb/google/fizz: Prepare sharing directory for variantsDavid Wu
Clean up Kconfig file in order to support variants for fizz. Add BOARD_GOOGLE_BASEBOARD_FIZZ that can be set by various fizz variants to use the common baseboard configs. BUG=b:117066935 BRANCH=Fizz TEST=emerge-fizz coreboot Change-Id: I9c89f1dc526a9d623e1ae4d4b52a923489b389d3 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-12mainboards: Add SMMSTORE region in chromeos configsPatrick Georgi
Only for those that are x86 and also have a RW_LEGACY region. The assumption is that all devices touched have 64k block sizes when choosing size and alignment of the region. Change-Id: I12addb137604f003d1296f34f555dae219330b18 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/28532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-25mb/google/x86-boards: Get rid of power button device in corebootFurquan Shaikh
As per the ACPI specification, there are two types of power button devices: 1. Fixed hardware power button 2. Generic hardware power button Fixed hardware power button is added by the OSPM if POWER_BUTTON flag is not set in FADT by the BIOS. This device has its programming model in PM1x_EVT_BLK. All ACPI compliant OSes are expected to add this power button device by default if the power button FADT flag is not set. On the other hand, generic hardware power button can be used by platforms if fixed register space cannot be used for the power button device. In order to support this, power button device object with HID PNP0C0C is expected to be added to ACPI tables. Additionally, POWER_BUTTON flag should be set to indicate the presence of control method for power button. Chrome EC mainboards implemented the generic hardware power button in a broken manner i.e. power button object with HID PNP0C0C is added to ACPI however none of the boards set POWER_BUTTON flag in FADT. This results in Linux kernel adding both fixed hardware power button as well as generic hardware power button to the list of devices present on the system. Though this is mostly harmless, it is logically incorrect and can confuse any userspace utilities scanning the ACPI devices. This change gets rid of the generic hardware power button from all google mainboards and relies completely on the fixed hardware power button. BUG=b:110913245 TEST=Verified that fixed hardware power button still works correctly on nautilus. Change-Id: I733e69affc82ed77aa79c5eca6654aaa531476ca Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-11skylake: Remove "IshEnable"li feng
Remove "IshEnable" from soc_intel_skylake_config since it's not used anymore. Enable/disable ISH by checking if ISH device is turned on or not. Refer to https://review.coreboot.org/#/c/coreboot/+/26485/. BUG=b:79244403 BRANCH=none TEST=Built. Change-Id: I4d2889af118659852431c87cb516fd19b577efc5 Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://review.coreboot.org/26521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-27mb/google/*: Add a few VBT filesMatt DeVillier
These files are directly extracted from the vendor firmware Change-Id: I1f05c913872c5d2d8c8279d89eac52fd4bf4e35e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27222 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-11google/fizz: fix LAN driver chip_info attachmentMatt DeVillier
As a result of commit: [711fb81] soc/intel/skylake: Swap PCI devfn resides in same PCI device fizz's chip_info for the LAN driver is being overwritten/nulled, as the LAN device is on function 2 (PCIe port 3), but the driver info was set for the post-swapped PCIe port (1). Move the driver chip_info to function 2/port 3, so that it follows the PCI device function when swapped after FSP-s, and is correctly passed to the LAN driver. Test: boot google/fizz (teemo variant), check cbmem console and verify ethernet MAC address and LED config correctly set. Change-Id: I08810c0c89d99af5799f42c7c4e51814f09aafec Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-11Fizz: Remove BJ adapter configurationDaisuke Nojiri
This patch removes BJ adapter configuration, which has been moved to the EC. BUG=b:109762580 CQ-DEPEND=CL:1089328 BRANCH=none TEST=Verify BJ adapter is set expectedly on Teemo. Change-Id: I3041b984e7f02624b94ba2713b084d001fa155f9 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1089370 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/26965 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-06soc/intel/common/block: Add common chip config blockSubrata Banik
Adding common chip config structure which will be used to return data to common code. When common code requires soc data, code used to fetch entire soc config structure. With this change, common code will only get the data/structure which is required by common code and not entire config. For now, adding i2c, gspi and lockdown configuration which will be used by common code. BUG=none BRANCH=b:78109109 TEST=compile code for APL/SKL/CNL. Boot using SKL/APL/CNL and check values are returned properly using common structure. Change-Id: I7f1671e064782397d3ace066a08bf1333192b21a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/26189 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Hannah Williams <hannah.williams@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-05soc/intel/skylake: Add option to skip coreboot MP initSubrata Banik
This patch provides option for mainboard to skip coreboot MP initialization if required based on use_fsp_mp_init. Option for mainboard to skip coreboot MP initialization * 0 = Make use of coreboot MP Init * 1 = Make use of FSP MP Init Default coreboot does MP initialization. Change-Id: I8de24e662963f4600209ad1b110dc950ecfb3a27 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26818 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-04security/tpm: Unify the coreboot TPM software stackPhilipp Deppenwiese
* Remove 2nd software stack in pc80 drivers directory. * Create TSPI interface for common usage. * Refactor TSS / TIS code base. * Add vendor tss (Cr50) directory. * Change kconfig options for TPM to TPM1. * Add user / board configuration with: * MAINBOARD_HAS_*_TPM # * BUS driver * MAINBOARD_HAS_TPM1 or MAINBOARD_HAS_TPM2 * Add kconfig TPM user selection (e.g. pluggable TPMs) * Fix existing headers and function calls. * Fix vboot for interface usage and antirollback mode. Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/24903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-01mb/google/fizz: Add USB port infoEmil Lundmark
This adds all USB ports to the device tree. Additionally, it adds _PS0 and _PS3 ACPI methods for the visible USB A ports, which makes it possible to control the port power (VBUS) of each port individually. Change-Id: I80ba090f323fbf9fc2b333b1c647b7dfb3393ff6 Signed-off-by: Emil Lundmark <lndmrk@chromium.org> Reviewed-on: https://review.coreboot.org/26472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-05-15mb/google/fizz: Add device index for dual LAN skuDavid Wu
Fix dual LAN sku can't inherit correct MAC from VPD setting. BUG=b:77836343 BRANCH=Fizz TEST=Program the mac address to VPD in shell vpd -s ethernet_mac0=<mac address1> vpd -s ethernet_mac1=<mac address2> && reboot the system. Ensure the MAC address was fetched correctly by ifconfig command. Change-Id: Ic357a3f1435d6d08107520e40872f1003ef2edf3 Signed-off-by: David Wu <david_wu@quantatw.com> Reviewed-on: https://review.coreboot.org/25587 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-08mb/google: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I8e549e4222ae2ed6b9c46f81c5b5253e8b227ee8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-28soc/intel/skylake: Limit xDCI feature when VBOOT is enabledDuncan Laurie
Use the common xDCI function to check if the controller is allowed in the current mode before enabling it. Otherwise, disable the PCI device if it has been enabled in devicetree. To make the SOC behavior consistent the XdciEnable config option is removed in favor of direct control by devicetree.cb and the mainboards that had defined it were adjusted accordingly. This was tested on an Eve board with xDCI enabled in devicetree.cb to ensure the xDCI device is enabled in developer mode and disabled in normal mode. Change-Id: Ic3c84beac87452f17490de32082030880834501d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/25365 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-21mb/google/fizz: Enable I2C bus 2Zhongze Hu
I2C bus 2 goes to the custom add-in card slot and it was disalbed cuase it was idle. Google CFM add-in card is going to use this I2C bus so it needs to be re-enabled. BUG=b:73006317 TEST=Tested with add-in card on fizz hardware and verified I2C bus 2 is working properly. Change-Id: I2c9b5a9323fd51872e340c35005c4a3432716808 Signed-off-by: Zhongze Hu <frankhu@chromium.org> Reviewed-on: https://review.coreboot.org/25258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2018-03-19mb/google/fizz: Enable VMXShelley Chen
We are enabling at the kernel level, but that is triggering an issue where FSP expects it to be disabled so it forces a cold reboot on every warm reboot, clearing the ramoops logs. Enabling in BIOS so it matches what the kernel expects. This is the same change that were done for eve: https://review.coreboot.org/#/c/22449/ BUG=None BRANCH=None TEST=echo PANIC > /sys/kernel/debug/provoke-crash/DIRECT check for /dev/pstore/console-ramoops Change-Id: Icd0bd01f5aee4c89f503eebba0808a1f3059e739 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/25251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-06mainboard/google/fizz: Check HDMI HPD and DisplayPort HPDDaisuke Nojiri
Some type-c monitors do not immediately assert HPD. If we continue to boot without HPD asserted, Depthcharge fails to show pictures on a monitor even if HPD is asserted later. Also, if an HDMI monitor is connected, no wait is needed. If only an HDMI monitor is connected, currently the API always loops until the stopwatch expires. This patch will make the AP skip DisplayPort wait loop if it detects an HDMI monitor. And if an HDMI monitor is not detected, the AP will wait for DisplayPort mode (like before) but also its HPD signal. This patch also extends the wait loop time-out to 3 seconds. BUG=b:72387533 BRANCH=none TEST=Verify firmware screen is displayed even when a type-c monitor does not immediately assert HPD. Verify if HDMI monitor is connected, AP does not wait (and firmware screen is displayed on HDMI monitor). Change-Id: I0e1afdffbebf4caf35bbb792e7f4637fae89fa49 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/23816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-06mb/google/fizz: Skip FSP init for UART 0Duncan Laurie
The GPIO pins for UART 0 on Fizz are routed to the add-in card slot and should not be used as a UART device. coreboot is setting the pins to GPIO Mode but FSP is re-configuring them for Native Mode and the behavior is unexpected when the kernel tries to initialize the UART device. The UART 0 device is PCI function 0 so it needs to be enabled for other functions to be visible to the OS so it can't just be disabled. Instead, set the device to PchSerialIoSkipInit so that FSP will not change the pin state. BUG=b:73006317 TEST=Tested with add-in card on fizz hardware to ensure the pin state does not change when FSP runs or the kernel boots. Change-Id: Id97c1e482ef0d5642fcf9018d802e1d0e073263d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/24973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-23mb/google/fizz: Enable PCIe port 11, 12Zhongze Hu
Our CFM daughter card would like to use individual PCIe lanes for two different devices on the card. dlaurie@ has reconfigured PCIe port 9-12 from 1x4 to 1x2 + 2x1 on b2b connector on fizz to meet the requirement: https://chrome-internal-review.googlesource.com/571936 We also need to enable the ports on device tree. BUG=b:72523836 TEST=none BRANCH=fizz Change-Id: Icded9850d833752680e0174b6c476e657817b319 Reviewed-on: https://chromium-review.googlesource.com/923867 Commit-Ready: Zhongze Hu <frankhu@google.com> Tested-by: Zhongze Hu <frankhu@google.com> Reviewed-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/924860 Commit-Queue: Shelley Chen <shchen@chromium.org> Tested-by: Shelley Chen <shchen@chromium.org> Signed-off-by: Zhongze Hu <frankhu@chromium.org> Reviewed-on: https://review.coreboot.org/23845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2018-02-17mb/google/fizz: Wait until display is readyDaisuke Nojiri
Fizz fails to show pictures on a type-c monitor because VBIOS runs before DisplayPort link is ready. With this patch, when firmware needs to display something, Fizz calls google_chromeec_wait_for_display to make sure display is ready. The penalty is up to 2 sec per boot in dev and rec boot. Normal boot won't affected unless there is EC update. BUG=b:72387533 BRANCH=none TEST=Verify screens are displayed on Fizz as follows: 1. Put DUT in normal mode 2. Flash EC image to trigger EC sync (critical update) 3. Trigger manual recovery (insert) 4. Hit ctrl+d to switch to dev mode (to-dev) 5. Confirm to reboot (dev warning) 6. Warm reboot (dev warning) 7. Cold reboot (dev warning) 8. Flash EC image to trigger EC sync (critical update) 9. Trigger manual recovery (insert) Change-Id: I90befe94f93e13904987acda50b2598d034b0031 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/23746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-11mb/google/fizz: Set SATA GPIOs in bootblockShelley Chen
Previously, we were seeing device boot into the recovery screen with error code 0x5a. This was root caused to the SATA GPIOs (specifically DEVSLP) not being initialized early enough, causing the SATA 1 link detection to time out and the device to reboot into recovery with 0x5a instead of booting into the OS as usual. BUG=b:69715162 BRANCH=None TEST=after flashing BIOS, set gbb flags to 0, then type reboot from the OS. Change-Id: I53913d5b7adaeb43edd0ef2d24a7cad92052d68a Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/23647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kane Chen <kane.chen@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-07mb/google/fizz: Set Pmax to 120 for all SKUsShelley Chen
The Pmax is calcuated from MAX(Psku1, Psku2), where Psku1, Psku2 are estimated Pmax power of U42 and U22 skus. For U42 sku, the Pmax is PL4 (71W) + ROPmax (49W) = 120W; for U22 SKU, the Pmax is PL4 (43W) + ROPmax (49W) = 92W. So Pmax is set to MAX(120W, 92W) = 120W. BUG=b:71594855 BRANCH=None TEST=Make sure correct pmax value is being passed into fsp Change-Id: Ic27fef87c869094b20438e6ee0e1eb0b35122b8d Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/23633 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Chris Ching <chingcodes@chromium.org>
2018-02-06mb/google/fizz: Determine PsysPl3 and Pl4 valuesShelley Chen
Pass in fizz-specific adapter-based PsysPl3 and Pl4 values to avoid brownouts. According to Intel doc #560604, page 74, the max time window is 64ms (code=6) and the min duty cycle we can set is 4%. BUG=b:71594855 BRANCH=None TEST=Boot to OS and check MSRs using iotools for expected values Change-Id: I06a4c5bc25f6ec036b79f6941f80e26058d64930 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/23528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-05mb/google/fizz: Get OEM ID and SKU ID from ECDaisuke Nojiri
This patch makes coreboot fetch OEM ID and SKU ID from EC. If it fails, it falls back to GPIO pins. BUG=b:70294260 BRANCH=none TEST=Verify AP log shows expected OEM ID and SKU ID on Fizz. Change-Id: I06d3a205275b46660b3974bc3673d4be8e13f6d1 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/23548 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-29google/fizz: Adjust PL2 and PsysPl2 values for power lossShelley Chen
Set PsysPl2 values to 90% of max adapter power for all types of adapters (typeC and barrel jack) to account for a 10% power loss from the adapter to the soc. BUG=b:71594855 BRANCH=None TEST=reboot device and make sure Pl2 and PsysPl2 MSRs are properly set with iotools rdmsr command on both U42 and U22 skus with both typeC and barrel jack power adapters. Change-Id: I8425c6d4d669449eccb9324ff58ff6d1662c5c43 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/23457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-24mb/google/fizz: Add AC/DC loadline settingsGaggery Tsai
This patch adds AC and DC loadline settings since vr_config_enable is set. Without correct AD/DC loadline settings, VRs reported incorrect VID values which caused CPU freqency clipping. The clipping reason could be retrieved from MSR 0x64F. From VRTT report, the AC/DC loadline resistances are within spec, we can use default value defined in Table 6-1, doc #543977. BUG=b:70646304 BRANCH=None TEST=emerge-fizz coreboot chromeos-bootimage & Read AC/DC loadline settings from DCI to ensure the values were programmed correctly. Change-Id: Id0ce29fa5726ca3711aa4c822fb123e2de7bc48f Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/23349 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-23mainboard/google/fizz: Tune audio i2c parametersShelley Chen
Tune I2C params for I2C bus 5 to ensure that the frequency does not exceed 400KHz. BUG=b:65058277 BRANCH=None TEST=Measured bus frequency for audio <= 400MHz Change-Id: I18bca023a6a0fe21e6f46f8688264d3c04d77f25 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/23359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-22mb/google/fizz: Remove IccMax settings from DTGaggery Tsai
This patch removes IccMax settings from device tree since they are handled in SoC code from patch e1a75d. BUG=b:71369428 BRANCH=None TEST="USE=fw_debug emerge-fizz chromeos-mrc coreboot chromeos-bootimage" & ensure the IccMax settings passed to FSP are from SoC code. Change-Id: I6b01c50a2589d1722c5bf4aa2f44a9574df818f4 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/23278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2018-01-17google/fizz: Fix barrel jack values for U42 and U22Shelley Chen
Our current U22 skus (celeron and i3) actually don't support PL2, but making sure that if we do decide in the future to use it to make sure PL2 and PsysPl2 values are set appropriately. BUG=b:71594855 BRANCH=None TEST=Make sure that PsysPL2 value set to 90W with barrel jack for U42 and 65W with barrel jack for U22. Change-Id: I084d0320128a6e05948023520a30c497c41be23b Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/23294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-12mb/google/fizz: update DPTF settingsKevin Chiu
TCPU: _CRT: 100 _PSV: 93 _TRT: 100/5(s) TSR0: _CRT: 83 _PSV: 70 _TRT: 100/10(s) TSR1: _CRT: 73 _PSV: 67 _TRT: 100/30(s) TCC: 6 for 94'C PL1: max: 15W min: 3W BUG=b:70294260 BRANCH=master TEST=build Change-Id: Ie17f4395d2199009fd68a600d818f2be54bc8935 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/23155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-12mb/google/fizz: Disable PCH LanKane Chen
Fizz has external Lan on PCIE port. The Lan device on PCH is not used. BUG=b:70889517 Change-Id: I99894bedec14a44724ac7c22d0c894132a795b78 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/23180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-11google/fizz: Dynamically set PsysPl2 MSR if using type-C chargerShelley Chen
If using type-C charger, then PsysPl2 may be lower than barrel jack value of 90W, so need to override value to the max power of type-C charger. BUG=b:71594855 BRANCH=None TEST=Make sure that PsysPL2 value set to 60W with zinger, but 90W when using proper barrel jack adapter on and i7. Change-Id: If955b9af0e23f47719f001f1d73ec37113937cea Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/23182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-09mb/google/fizz: Turn off SATA SALPKevin Chiu
turn off SATA SALP to prevent 0x5A/0x5B error on Sandisk SSD in below conditions: 1. reboot stress 2. FAFT BIOS qualification BUG=b:70146894,b:69984821,b:70590720 BRANCH=master TEST=pass firmware_ConsecutiveBoot 2500 loops FAFT BIOS test pass Change-Id: I5d57dd8ef256d5f0a1027ab77f63da62c6c9ce74 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/23153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2018-01-02google/fizz: Enable SataPwrOptEnable FSP UPDKane Chen
This change is to enable SataPwrOptEnable. With this change, we no longer see SError message in kernel during suspend_stress_test. BUG=b:70491485 Change-Id: Ieb991f6889c5ff3181a670bc7702314049fa983c Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/23019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-22mb/google/fizz: revise LED0 behavior for link speed 100MbGaggery Tsai
This patch revises LED0 Green light behavior from patch 2ecf3f8c. For 100Mb link speed, LED0 should be OFF. BUG=b:65437780, b:68284778, b:69950854, b:65808944 BRANCH=None TEST=Run DUT with 100Mb and 1000Mb ethernet connection and observe LED0 is behaving as expected. Change-Id: Ia805c955711b8ce77eba087a28427a005c456fa1 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/22964 Reviewed-by: David Wu <david_wu@quantatw.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-22soc/intel/skylake: Add PcieRpClkSrcNumber UPD configuartion supportDivya Chellap
New UPD PcieRpClkSrcNumber introduced in FSP V2.9.2 to configure clock source number of PCIe root ports. This UPD array is set to clock source number(0-6) for all the enabled PCIe root ports, invalid(0x1F) is set for disabled PCIe root ports. BUG=b:70252901 BRANCH=None TEST= Perform the following 1. Build and boot soraka 2. Verify PCIe devices list using lspci command 3. Perform Basic Assurance Test(BAT) on soraka Change-Id: I95ca0d893338100b7e4d7d0b76c076ed7e2b040e Signed-off-by: Divya Chellap <divya.chellappa@intel.com> Reviewed-on: https://review.coreboot.org/22947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-21google/fizz: Enable ec sw sync gbb by defaultShelley Chen
firmware test team is requesting that default gbb flags set to 0x39 rather than 0x239 so that it's consistent with the default gbb flags of other platforms. BUG=b:70392534 BRANCH=None TEST=emerge-fizz coreboot chromeos-bootimage gbb_utility --get --flags image-fizz.bin and make sure that it returns 0x39 instead of 0x239 Change-Id: Ib73e4619b13f6b7c2d01598c926fbbd7d7eb9bef Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/22962 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-21mainboard/google/fizz: Enable S0ixShelley Chen
Enable S0ix for fizz. BUG=b:67598361 BRANCH=None TEST=None. Need to be tested with EC and kernel as well. Change-Id: I981d2cc7e969a44567b0f21f63f68c78e73f5cb5 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/22955 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-20mb/google/fizz: Enable mbox command for ISL VR c-state issueRizwan Qureshi
There is a potential IMVP8 issue for KBL that affects Intersil VRs Fizz is using one of the affected parts. The fix is to use an updated microcode and also send a mailbox box command from FSP. BUG=b:65499724 BRANCH=None TEST=Build and boot Fizz Change-Id: Iebfda02df88ea0d2aaf79e8449b95c0eb2165c6b Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/22763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-15 02:53:21 +0000