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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I3c90ef02041799954aa656924df8c07325b83431
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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They're listed in AUTHORS and often incorrect anyway, for example:
- What's a "Copyright $year-present"?
- Which incarnation of Google (Inc, LLC, ...) is the current
copyright holder?
- People sometimes have their editor auto-add themselves to files even
though they only deleted stuff
- Or they let the editor automatically update the copyright year,
because why not?
- Who is the copyright holder "The coreboot project Authors"?
- Or "Generated Code"?
Sidestep all these issues by simply not putting these notices in
individual files, let's list all copyright holders in AUTHORS instead
and use the git history to deal with the rest.
Change-Id: I09cc279b1f75952bb397de2c3f2b299255163685
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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This patch is part of the patch series to drop support for FSP 1.1 in
soc/intel/skylake.
The following modifications have been done to migrate the board(s) from
FSP 1.1 to FSP 2.0:
- remove deprecated devicetree VR_RING domain (only 4 domains in FSP 2.0)
- switch to using the FSP default VBT
TODO:
- testing
Change-Id: Id747ef484dfdcb2d346f817976f52073912468d0
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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DqByteMapCh0 and DqByteMapCh1 are declared adjacently in the
FSP_M_CONFIG struct, so it is tempting to begin memcpy at the address of
the first array and overwrite both of them at once. However, FSP_M_CONFIG
is not declared with the packed attribute, so this is not guaranteed to
work and is undefined behaviour to boot. It is cleaner and less tricky
to copy them independently. The same is true for DqsMapCpu2DramCh0 and
DqsMapCpu2DramCh1, so we change those as well.
Change-Id: If394f14c4a39d6787ae31868241229646c26be7a
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1365730, 14013{38,39,40,42,43}
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The SoC specific `struct pei_data` was filled with values that were
later only consumed by the mainboard code again. Avoid jumping through
this hoop and fill FSP UPDs directly.
Change-Id: I040f4a55b4f4bad3f6072920e5e2eceded4cb9bb
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Add google/cave (Asus Chromebook Flip C302SA) as a variant of
glados Skylake reference board:
- add cave-specific DPTF, EC config, GPIO config, Kconfig,
NHLT config, PEI data, VBT, SPD data, and devicetree
Adapted from Chromium branch firmware-glados-7820.B, commit
b0c3efe54d877246d07f2467b2dff51cc30348fa [soc/intel/skylake: Enable VMX]
Test: build/boot google/cave, verify correct functionality
Change-Id: I5c5181ce68f7a24ccd49f53ecd9d48c081fd085a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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