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Missing bus init for RTL8111H ethernet chip hanging on bus.
V.2: Include admendments from Kangheui.
BRANCH=none
BUG=b:146437819
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: I22aba312f183ea05eeb81d326ca0c05ce340a2e8
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Create initial overlays and build for mushu
Signed-off-by: Bob Moragues <moragues@chromium.org>
Change-Id: I81b5bf960ead0463159ac35f4f96e3ccc8c0364e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This impacts boards:
hatch (&variants) and drallion.
Some variants like Puff can have up to 12 cores. coreboot should take
the min() where MAX_CPU is the upper bound.
Further to that, boards themseleves shouldn't be setting the MAX_CPUS,
the chipset should be and so do that.
BRANCH=none
BUG=b:146255011
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: I284d027886f662ebb8414ea92540916ed19bc797
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
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(Auto-Generated by create_coreboot_variant.sh version 1.0.0).
BUG=b:145101696
TEST=util/abuild/abuild -p none -t google/hatch -x -a
make sure the build includes GOOGLE_STRYKE
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Iea6f8a1c6c24a1e3545c364551cb623debdc4a1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Change-Id: Ic92e08ae5b741889a8200d10ea8148e4b4384dc8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37270
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: David Guckian
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Now that the EC software sync in romstage ("early EC sync") patches
have landed, it's time to enable this for Hatch.
BUG=none
BRANCH=hatch
TEST=verify EC sync runs in romstage
Change-Id: Ie567ab081b95b2302b051812fbf46e183c76bab6
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37025
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Create new variant for jinlon
BUG=b:144150654
TEST=emerge-hatch coreboot chromeos-bootimage and boot on jinlon proto
board
Change-Id: I8deb29041475e38cbbf2f54519940f62b9f21822
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36681
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Created helios_diskswap as a variant of helios (hatch variant).
BUG=b:143378037
BRANCH=None
TEST=none
Change-Id: I6536b3908ec569e1ac42ea7c5be85701012ab177
Signed-off-by: Alexis Savery <asavery@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Includes:
- gpio mappings,
- overridetree.cb,
- kconfig adjustments for reading spd over smbus.
V.2: Rework devicetree with comments and drop some useless gpio maps.
BUG=b:141658115
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: I6449c4fcc1df702ed4f0d35afd7b0981e4c72323
Signed-off-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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All Hatch variants so far embed static SPD data encoded within the
firmware image. However we wish the flexibility for romstage
implementations that allow for reading the SPD data dynamically over
SMBus. This romstage variant allows for reading the SPD data over
SMBus.
V.2: Dispence with memcpy().
V.3: Revert back to previous patch with memcpy().
V.4: Rewrite again to avoid memcpy().
BRANCH=none
BUG=b:143134702
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: I3516a46b91840a9f6d1f4cffb2553d939d79cda2
Signed-off-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36449
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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All Hatch variants so far embed static SPD data encoded within the
firmware image. However we wish the flexibility for romstage
implementations that allow for reading the SPD data dynamically over
SMBus.
BRANCH=none
BUG=b:143134702
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: Ie1637d08cdd85bc8d7c3b6f2d6f386d0e0c6589b
Signed-off-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Previously all boards using eSPI for the Chrome EC just called it
LPC as the code for the chrome EC is the same between the two
busses.
I'm adding a new Kconfig symbol to specify eSPI, so switch the
boards that actually use eSPI to that symbol and add the LPC
symbol to all the others.
The EC_GOOGLE_CHROMEEC_LPC symbol will no longer default
to enabled for x86 platforms, so one symbol or the other needs to be
specified for each platform.
BUG=b:140055300
TEST=Build tested only.
Change-Id: Icf242ca2b7d8b1470feda4e44b47a2cdc20680f2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The CONFIG_GBB_HWID can be generated automatically now so we can remove
the test-only HWIDs set in board config files.
BUG=b:140067412
TEST=Built few boards (kukui, cheza, octopus) and checked HWID:
futility gbb -g coreboot.rom
Change-Id: I4070f09d29c5601dff1587fed8c60714eb2558b7
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35635
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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All variants of hatch are using Comet Lake and so the selection can be
done in Kconfig without requiring each variant to do the same.
Change-Id: Ief34296334ede5ba0f5f13381e92427ccc440707
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Andrew McRae <amcrae@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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Create dratini variant
BUG=b:140610519
TEST=emerge-hatch coreboot, and boot into chromeos on proto board
Change-Id: Ied1240d1be831568e4ab4695b893c3f48821f68b
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35285
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This is based on the hatch variant
BUG=b:138879565
TEST=FW_NAME="akemi" emerge-hatch coreboot depthcharge intel-cmlfsp
chromeos-bootimage look for image-akemi.*.bin generated under the
/build/hatch/firmware/
Change-Id: I1a868839e2c598f8052d37c99713bc58b21e887c
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This change adds a user selectable option to enable all WiFi SAR
configs that apply to hatch.
BUG=b:138177048
Change-Id: I4b72f90896841e7c556d4a1b8cdad8ca89d01021
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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Hatch_whl variant is deprecated.
BUG=b:137180390
Change-Id: I88fa201398ad5fb70da48d022f1ae86fecafa660
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34432
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add Helios as a variant of Hatch.
BUG=b:133182138
BRANCH=None
TEST=util/abuild/abuild -p none -t google/hatch -x -a
attempts to build a Helios target.
Change-Id: I64ba06932eb0ee32405f7b14a94971a64c8fce71
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32918
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Create the Kindred variant of Hatch by taking a copy of the Hatch files
as placeholders. Kindred-specific changes will happen in future CLs.
BUG=b:133181366
BRANCH=NONE
TEST=util/abuild/abuild -p none -t google/hatch -x -a
make sure the build includes GOOGLE_KINDRED
Change-Id: I09ad3da0505d599fc3797d7fa24b4dc170dcd18b
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This change fixes the typo in CB:32161 (mb/google/hatch: Add Kohaku
board) that defaults GBB_HWID incorrectly for kohaku using
BOARD_GOOGLE_HATCH_WHL.
Change-Id: I387879619ac4f79fad422e5f1f047dfe3c7b5b22
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32690
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add common SoC config.
Disable PCIe WiFi.
Add digitizer.
Turn off native SD card interface.
No WWAN.
Add DA7219 driver to Kconfig.
BUG=b:130310626
BRANCH=none
TEST=compiles (no Hatch ref or Kohaku device to test)
Change-Id: I17d5ba6ce4ec412384e4a1678474b8d26499ba40
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add a fmd file for 16MiB fmap, so that we can support
both 16MiB / 32MiB SPI flash ROM chips.
BUG=b:129464811
TEST=build hatch firmware image with 16MiB fmap and
verify fmap is updated by 'fuility dump_fmap'
Change-Id: Ifc0103c7fd0d99439f40a31d23422401a6dce826
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This change moves the I2C/SPI devices and configs which do not apply
to all variants to override tree. Currently, there are just two
variants. However, as we prepare to add more variants, these devices
need to be moved out of the base devicetree.
BUG=b:129728235
TEST=Verified that I2C/SPI devices are present in static.c for hatch
and hatch_whl.
Change-Id: I9426f6bf5f8514de5f1889e22e57105749fd92de
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32138
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Adding Kohaku as a variant of hatch.
BUG=b:129706980
BRANCH=NONE
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
make sure HATCH_KOHAKU is built as well.
Change-Id: I5b451f421f6d353005e6b73eac180dcec2e8b0c0
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add GPIO_A8 for pen detect function.
BUG=b:122765828
TEST=flash BIOS and using switch to verify GPIO_A8 value change.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ie7c888ea61dd61e60c1d184565bd95e6b03777be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31815
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add serialio settings to hatch. Only applies to CML.
BUG=b:128347800
BRANCH=None
TEST=abuild
Change-Id: I6a9ec778d74cd48a2e1c79f8e669a9a6a6a9477d
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32003
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add SAR0, which is an SX9310. The schematics and layout have a second
SAR1 sensor provisioned on I2C4, with an interrupt of GPP_A6, but this
is not populated.
Signed-off-by: Evan Green <evgreen@chromium.org>
BUG=b:128540461
BRANCH=none
TEST=Boot kernel with sx9310 driver, see it come up happily
Change-Id: I63943cc7da5ff56f6ef6dcbd99bb8f8f031e8bf7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Enrico Granata <egranata@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Move these configs to Kconfig.name as well.
BUG=b:127310803
BRANCH=None
TEST=emerge-hatch coreboot chromeos-bootimage
Change-Id: I793363740fa0730a1e9e1aa7a9fa82d2789334b4
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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The board version is part of EC's EEPROM, select Kconfig items to enable
requesting the EC for board version.
BUG=b:128385395
TEST=Verified the mainboard version is from EC's EEPROM.
Change-Id: I4bc1cac43c6cf73522f3a4bee89cc000a430d996
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31858
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Adding Hatch_whl as a variant of hatch. This is a snapshot of the WHL
version of hatch so that we can rebuild the bios images for Hatch with
WHL SoC.
BUG=b:127310803
BRANCH=NONE
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
make sure HATCH_WHL is built as well.
Change-Id: I24510fa226878582a61f1846f0b56a2c65204a92
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Following changes are done to enable audio support on hatch
1. Enable I2C4 device at 400Khz at 1.8V
2. Configure GPIO for HP INT and SPKR_PA_EN
3. Add ACPI entry for RT5682 and MAX98357A
4. Enable I2S0 and I2S1 lines
5. Enable generic max98357a driver in Kconfig
BUG=b:123738217
BRANCH=none
TEST=Check SSDT table for RT5682 & MAX98357a entry.
Verify audio using Sound Open firmware (SOF)
Change-Id: I93f3917c19cc3f0f8fd7b5e1b4d9b24a59f45f84
Signed-off-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Hatch implements active high SD_PWR_EN and requires a workaround
in _PS0 and _PS3 control methods to make sure SD_PWR_EN stays low
in D3. Select MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE to enable the same.
BUG=b:123350329
Change-Id: I96ab9660eb50100207fe9a237f5924b65eae0928
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/31446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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EC software sync had been disabled because BIOS was not bundling a
useful EC image. This is no longer required. This CL removes that
change so EC software sync is enabled by default.
BUG=b:124208414
BRANCH=None
TEST=Tested with a system that have a different RW image and verified
that this image was overwritten to the one bundled in the BIOS and
that the EC was running its RW image.
Signed-off-by: Scott Collyer <scollyer@chromium.org>
Change-Id: Ic1ffdb62e9fa2cacb3296cb3807082f23e171ab5
Reviewed-on: https://review.coreboot.org/c/31537
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch performs below tasks
1. Create SOC_INTEL_COMMON_CANNONLAKE_BASE kconfig.
2. Allow required SoC to select this kconfig to extend CANNONLAKE
SoC support and add incremental changes.
3. Select correct SoC support for hatch, sarien, cflrvps
and whlrvp.
* Hatch is WHL SoC based board
* Sarien is WHL SoC based board
* CFLRVP U/8/11 are CFL SoC based board
* WHLRVP is based on WHL SoC
4. Add correct FSP blobs path for WHL SoC based designs.
Change-Id: I66b63361841f5a16615ddce4225c4f6182eabdb3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This implementation adds support to create ACPI package for USB port
capability (_UPC) and physical location of device (_PLD) for USB2 port 10.
BUG:b:123375275
TEST:Verify _UPC and _PLD ACPI packages gets published for USB2 Port 10
in SSDT and BT is functional in discrete and integrated mode.
Change-Id: Ifeab24505a700e8e4677be20074c7d0400769cec
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/31197
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch removes duplicate selects of same SOC_INTEL_CANNONLAKE_MEMCFG_INIT
from various CFL/WHL SoC based boards to include cnl_memcfg_init.c file
and include the cnl_memcfg_init.c file by default in CNL SoC Makefile.inc.
Change-Id: Ib21ea305871dc859e7db0720c18a9479100346c3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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hatch shouldn't make use of internal ec.bin through IFD tool.
Change-Id: Ib1a324291b1c8ac90a7d790b63427b2e85c74fd1
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
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Disabling software sync since EC patches haven't landed yet.
BUG=b:120914069
BRANCH=None
TEST=build bios image and make sure gbb flag 0x200 is set
Change-Id: I1661bcd6ebbee6d9aa8068efcc18b259fb4c8203
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/30943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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After f5ca922 (Untangle CBFS microcode updates) got merged, all
mainboard using intel apollolake, cannonlake, coffeelake, glk,
kabylake, skylake, icelake and whiskeylake get affected.
Using INTEL_LPSS_UART_FOR_CONSOLE instead of UART_DEBUG
and set default console for each platform.
BUG=N/A
TEST=Build and test on Sarien platform, by default we can still get
console from cbmem, and enable CONSOLE_SERIAL can get logs from UART
port 2.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I550a00144cff21420537bb161c64e7a132c5d2de
Reviewed-on: https://review.coreboot.org/c/30853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Most boards currently do not use EC firmware from SPI flash in the
IFD, this hides this option by default and shows it only for boards
that need it.
A new config variable MAINBOARD_USES_IFD_EC_REGION is introduced to
enable this option for boards that need it.
The following list of boards requiring this was provided by
Lijian Zhao:
1. intel/cannonlake_rvp
2. intel/coffeelake_rvp
3. intel/icelake_rvp
4. google/sarien
5. google/hatch
Change-Id: I52ab977319d99a23a5e982cc01479fe801e172a7
Signed-off-by: Jan Tatje <jan@jnt.io>
Reviewed-on: https://review.coreboot.org/c/30697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
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This patch incorporates following changes to enable console on UART0
1. update default console number to 0
2. Enable PCI port for UART0
GPIO configuration will be done by coreboot based on correct console
number.
Change-Id: I735d33674b276b28e2cbb753d3a6d83edbabe89d
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/30424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
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Enable EC LPC interface and configure below LPC IO decode ranges:
1. 0x200-020F: EC host command range.
2. 0x800-0x8FF: EC host command args and params.
3. 0x900-0x9ff: EC memory map range.
BUG=b:120914069
TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot
Change-Id: Ie5d92df80d6b3a5913d0cbe78c1b8eefb5269d4a
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/30416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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This implementation adds below code:
1. Add SOC ACPI code in dsdt.asl
-> platform.asl
-> globalnvs.asl
-> cpu.asl
-> northbridge.asl
-> southbridge.asl
-> sleepstate.asl
2. Add chromeos.asl in dsdt.asl
3. Add EC ACPI code in dsdt.asl
-> superio.asl
-> ec.asl
4. Remove config for WAK/PTS ACPI method as chromeec
doesn't implement those.
BUG=b:120914069
TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot
Change-Id: Icf1b1d7e34a7e863139c3583903f3b1e2cdc8da6
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/30282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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This implementation adds below support:
1. Add support to read memory strap.
2. Add support to configure below memory parameters
-> rcomp resistor configuration
-> dqs mapping
-> ect and ca vref config
3. Include SPD configuration
BUG=b:120914069
BRANCH=None
TEST=USE="-intel_mrc -bmplk" emerge-hatch coreboot
Change-Id: I9bda08bd0b9f91ebb96b39291e15473492a6bf19
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/30248
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Incorporating some feedback to initial hatch mainboard checking
(CL:30169) that came in after the CL merged.
Updated the chromeos.fmd with the following,
* SI_ALL = 3MB
* SI_BIOS = 16MB
BUG=b:20914069
BRANCH=None
TEST=./util/abuild/abuild -p none -t google/hatch -x -a -v
Change-Id: I4e311c68873f10f71314e44d3a714639a06dbee8
Signed-off-by: Shelley Chen <shchen@google.com>
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/30296
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add code support to enable H1 TPM interfaced to SOC on GSPI0.
The TPM interrupt is mapped to GPP_C21.
BUG=b:120914069
TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot
Change-Id: Ib63a0b473f632d91745102ebd01993e8d65b9552
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/30210
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Creating skeleton files and directories in mainboard for the new Hatch
board. This is to facilitate development for different parties
involved.
BUG=None
BRANCH=None
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: I5fc60c178f83034abe5d846d0f4169072b66f448
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/30169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
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