Age | Commit message (Collapse) | Author | |
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2019-03-14 | mb/google/hatch: Update DRAM IDs | Shelley Chen | |
Update Hatch DRAM IDs to use the new DRAM ID assignment for general spds: 0 = 4G 2400 1 = 4G 2666 2 = 8G 2400 3 = 8G 2666 4 = 16G 2400 5 = 16G 2666 BUG=b:122959294 BRANCH=None TEST=emerge coreboot and make sure boots up Change-Id: Ic47737ce37597318bb794b63a47ced2467d8bbb0 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> | |||
2019-02-08 | mb/google/hatch: Replace part-specific SPD files with generic ones | Shelley Chen | |
Traditionally, we have always allocated 1 DRAM ID per part number. However, on nami, we have run out of DRAM IDs because we have supported so many different parts. We are now adopting the use of generic SPD files that are feature-based rather than specific to each part, allowing us to support multiple parts with a single SPD. The common SPDs were created by taking current SPDs in Nami (which is using the same DDR4 parts as Hatch) and zeroing out all the manufacturer information and part names. Additionally, we zeroed out bytes 128 (raw card extension, module nominal height), 129 (module maximum thickness), and 130 (reference raw card used) after verifying that they are not used in FSP. We verified with these fields zeroed out, all nami devices could boot up without errors. We also verified on the two Hatch skus that we have (4G 2400, 8G 2666) that the generic SPDs boot properly. BUG=b:122959294 BRANCH=None TEST=Make sure that we can boot up on both 4G Samsung and 8G Hynix DDR4 devices that we currently have. Change-Id: I14d9e6b13975b6a65b506e6cd475160711b8f6d4 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/31261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> | |||
2018-12-23 | mb/google/hatch: Add memory init setup for hatch | Aamir Bohra | |
This implementation adds below support: 1. Add support to read memory strap. 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config 3. Include SPD configuration BUG=b:120914069 BRANCH=None TEST=USE="-intel_mrc -bmplk" emerge-hatch coreboot Change-Id: I9bda08bd0b9f91ebb96b39291e15473492a6bf19 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/30248 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> | |||
2018-12-13 | mb/google/hatch: Creating skeleton directories and files | Shelley Chen | |
Creating skeleton files and directories in mainboard for the new Hatch board. This is to facilitate development for different parties involved. BUG=None BRANCH=None TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I5fc60c178f83034abe5d846d0f4169072b66f448 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/30169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> |