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In https://review.coreboot.org/c/coreboot/+/37459
(commit fcd8c9e99e7f70e2b9494f2fa28a08ba13126daa) which moves power/reset
pin control of FPMCU to var/board/ramstage, but does not implement it for
dratini/jinlon. So, add it in dratini/jinlon.
BUG=b:146366921
TEST=emerge-hatch coreboot
Change-Id: I1b6dbe4ba0a1242aa64346410beed4152b4f457f
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37833
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The baseboard GPIO table definitions are too straineous to the extend
that variants need to redefine assumptions back to NC. Invert this so
that baseboard by default assumes the safer NC and move the specific
board configurations to their respective places.
This patch handles the GPP_H3 gpio config for easier review. This
toggles the MAX amp which not all boards have. Move the pin
configuration to boards with the respective devicetree configuration
following on from the theme of commit b417786525.
BUG=b:142094759
BRANCH=none
TEST=builds
Change-Id: Iefd2223af79a13c8a42d07bc10b2772dbff6d3e5
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The baseboard GPIO table definitions are too straineous to the extend
that variants need to redefine assumptions back to NC. Invert this so
that baseboard by default assumes the safer NC and move the specific
board configurations to their respective places.
This patch handles the GPP_C15 group for easier review.
BUG=b:142094759
BRANCH=none
TEST=builds
Change-Id: I578245e24895d361d80ad016a4f18204e2b6e1ca
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The baseboard GPIO table definitions are too straineous to the extend
that variants need to redefine assumptions back to NC. Invert this so
that baseboard by default assumes the safer NC and move the specific
board configurations to their respective places.
This patch handles the GPP_A* group for easier review.
BUG=b:142094759
BRANCH=none
TEST=builds
Change-Id: I29b4323ac80b1288b2562846217c4f377714fc2c
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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FPMCU_PCH_BOOT1 pin is connected to GPP_C12. So, config GPP_C12.
BUG=b:142188003
TEST=emerge-hatch coreboot
Change-Id: I73a5c3529330ef3e72f4c7d5fcbbd2f6693494d8
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35845
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Create dratini variant
BUG=b:140610519
TEST=emerge-hatch coreboot, and boot into chromeos on proto board
Change-Id: Ied1240d1be831568e4ab4695b893c3f48821f68b
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35285
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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