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path: root/src/mainboard/google/hatch
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2020-09-01mb/google/puff: Convert ASL file to new DPTF dt implEdward O'Callaghan
This patch converts the current DPTF policies from static ASL files into the new SSDT-based DPTF implementation. All settings are intended to be copied exactly. BUG=b:158986928 BRANCH=puff TEST=duffy boots and dumped SSDT table for quick check. Change-Id: I45987f44ec381917173f8d2a878edb50da454b4b Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-08-31mb/google/puff: Set TCC offset to 5 for kaisa and duffyDavid Wu
Set tcc offset to 5 degree celsius for kaisa and duffy BUG=b:166696500 BRANCH=puff TEST=Build, and verify test result by thermal team. Change-Id: I2bb977b98c0764f0b9cac3543074da56057717cf Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44901 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-27mb/google/puff: Update psyspl2 to 97% of adapter ratingDavid Wu
Set psyspl2 to 97% of adapter rating, based on our experiment results. BUG=b:160676773 TEST=Built and check firmware log. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I4b621a8cc1749ee52a9f16a7ad2ae7a7aa0f7a5a Reviewed-on: https://review.coreboot.org/c/coreboot/+/44805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2020-08-23soc/intel/cnl: Configure FSP option PcieRpSlotImplementedNico Huber
Allow configuring FSP option PcieRpSlotImplemented. Also, update all related devicetrees and configure PcieRpSlotImplemented to keep the current behaviour. Change-Id: I6c57ab0ae50a37cd9a90786134e9056851a86a3c Signed-off-by: Nico Huber <nico.huber@secunet.com> Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-08-22mb/google/puff: Select cse_board_reset() strong symbolEdward O'Callaghan
Since Puff uses CSE Lite SKU that supports in-field CSME updates an additional reset is triggered when jmp from RO to RW during boot. However this reset is not detected by the cr50 running older firmware because the strapping configuration for EFS2 uses PLT_RST_L to assert to cr50 that a AP reset occured. The older cr50 firmware version of 0.0.22 only monitors AP resets via SYS_RESET_L and hence never detects the reset. To mitigate the issue above a modified reset sequence is required to be performed to signal the reset occured and hence a board-specific cse_board_reset() strong symbol is provided to modify the flow accordingly. V.2: Select CHROMEOS_CSE_BOARD_RESET_OVERRIDE common implementation instead of a local variant in mainboard.c BUG=b:162290856 BRANCH=puff TEST=none Change-Id: I27ab9711aedf92b5af7a58f3b5472ce79f78c8fa Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44454 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-18src: Remove unused 'include <delay.h>'Elyes HAOUAS
Change-Id: I6afea5c102299e570378a1656d3dcd329a373399 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44093 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-07soc/intel/cnl: Set Heci1Disable depending on devicetree configFelix Singer
Currently HECI1 gets enabled by the option HeciEnabled, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement/disablement of the HECI1 device. All corresponding mainboards were checked if the devicetree matches the HeciEnabled setting, and adjusted where necessary. Change-Id: I03dd3577fbe3f68b0abc2d196d016a4d26d88ce5 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-08-06mainboard/google/puff: Remove second temp sensorAndrew McRae
Newer boards have removed the second temperature sensor and relocated the remaining sensor. BUG=b:162909373 TEST=Confirm on hardware. Change-Id: Ie41a57598b0c87a6632f4c55c0f60a94a89cae43 Signed-off-by: Andrew McRae <amcrae@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-04mb/**/{devicetree,overridetree}.cb: Indent with tabsAngel Pons
Use tabs instead of eight (sometimes less) spaces. Change-Id: Ic3d61f5210d21d9613fc50b47b90af71f544169a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-07-27mb/google/hatch: Add smart battery I2C passthrough for DratiniTim Wawrzynczak
Some smart battery patches have been backported to the ChromeOS 4.19 kernel, and userspace can now access smart battery data from sysfs instead of using the hacky ectool instead. Also change all space indents into tab indents while we're here. BUG=chromium:1047277 TEST=confirmed a /sys/class/power_supply/sbs-i2c device shows up Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I43687e63e4c1a7756c117129ced20749afc1b9e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-26src: Remove extra lines in license headerElyes HAOUAS
Change-Id: I7378aa7d6156ece3ab3959707a69f45886f86d21 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43593 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20mb/google/puff: update USB3 gen2 parametersTim Chen
Based on USB3 gen2 SI report to fine tune the parameters for USB3 gen2. BRANCH=none BUG=b:150515720 TEST=build and check the USB3 gen2 register on DUT is correct. Change-Id: I6ec109871d682a1ae2fa4c22fdd6b87ad8a39e9e Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jamie Chen <jamie.chen@intel.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-07-14mb/hatch: Fix Puff baseboard missing mainboard symbolsEdward O'Callaghan
Fix a missing CONFIG_ prefix in Makefile. BUG=b:161154280 BRANCH=puff TEST=builds Change-Id: I177fcd830a8a03a8db1910bfbfd784a60dc08e11 Spotted-by: Ryan Lin. Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43438 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-14mb/google/hatch: Set SA slow slew rate to 1/2 for jinlon/dratiniWisley Chen
Screen flickered on VT2 on some devices after idle a period of time. Remove SSR (1/8) setting for SA to default SSR (1/2), screen flicking issue disappeared, and didn't affect acoustic noise much. Because CB:38212 (commit eae254e) caused this issue. BUG=b:160754994 TEST=build dratini, observe that screen flick issue disapppered Change-Id: I9e81c2f15dd6babfa360eee213fc4ab6310c7455 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43284 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03mb/google/hatch: Allow USB2/3 wakeups to (un)plug events in WyvernEdward O'Callaghan
V.2: Spare USB routed internally to another peripheral and so no plug event hook needed. BUG=b:1603699358,b:157479891 BRANCH=none TEST=none Change-Id: Ideacac417a46b96f3e82b53bbb341ecce79ee420 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42994 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03mb/google/hatch: Allow USB2/3 wakeups to (un)plug events in NoibatEdward O'Callaghan
BUG=b:160296662 BRANCH=none TEST=none Change-Id: I5298e1779461995a98722099b397692351767089 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42975 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03mb/google/hatch: Allow USB2/3 wakeups to (un)plug events in FaffyEdward O'Callaghan
BUG=b:160295948 BRANCH=none TEST=none Change-Id: I3600340d3448457942c827a463b458b280fea19a Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
2020-07-03mb/google/hatch: Allow USB2/3 wakeups to (un)plug events in KaisaEdward O'Callaghan
BUG=b:160296661 BRANCH=none TEST=none Change-Id: Id5a03f2cbdca2723ab1882c619d2d34387996b27 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42973 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03mb/google/hatch: Allow USB2/3 wakeups to (un)plug events in DuffyEdward O'Callaghan
BUG=b:160296325 BRANCH=none TEST=none Change-Id: Iffa6997029d0babfd6dd504a6cc212bd74de3a8f Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42972 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-02mb/google/faffy: update DPTF parametersTim Chen
Modify DPTF parameters for faffy from thermal team. BUG=b:160292247 BRANCH=None TEST=emerge-puff coreboot chromeos-bootimage verify the parameters are correct Change-Id: Ie8290f5460838f785a587c85b2ab7dd171dd0a54 Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sam McNally <sammc@google.com>
2020-07-01mb/google/nightfury: Override VBT selection for nightfury 2nd skuSeunghwan Kim
Override VBT for nightfury SKU_ID = 2 to support different panel. BUG=b:159051021 BRANCH=firmware-hatch-12672.B TEST=Built and verified using different VBT by SKU_ID Change-Id: I9450814aadc43cc7991457c3793f109b889186b9 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-30mb/google/hatch: Allow USB2/3 wakeups to (un)plug events in dtEdward O'Callaghan
BUG=b:159187889 BRANCH=none TEST=none Change-Id: I13626a236f1b7385208c4181150f094cbda490ed Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
2020-06-28mb/google/faffy: Enable USB2 port6Tim Chen
Due to faffy has PL-2303 connect to USB2 port6(count from port0), needs to enable it. BUG=b:159760559 BRANCH=None TEST=emerge-puff coreboot chromeos-bootimage boot on puff board Change-Id: Icc805757b043e7fac4d05188cbf2f9c9c56c2a2e Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-06-28gpio_keys: Allow boards to configure different wakeup routesFurquan Shaikh
This change allows mainboard to configure different wakeup routes that can be used by a GPIO key: 1. SCI: This is selected when SCI route is used to wake the system. It results in _PRW property being exposed in ACPI tables. 2. GPIO IRQ: This is selected when GPIO controller wake is used to wake the system. It is typically used when the input signal is not dual routed and the GPIO controller block is not capable of applying filters for IRQ and wake separately. In this case, _PRW is not exposed in ACPI tables for the key device. 3. Disabled: No wakeup supported. Based on these wakeup routes, gpio_keys_add_child_node() is updated to expose _PRW and _DSD properties for wakeup appropriately. Additionally, the change updates mainboards that were already using gpio_keys to set wakeup_route attribute correctly and renames "wake" to "wake_gpe" to make the usage clear. BUG=b:159942427 Change-Id: Ib32b866b5f0ca559ed680b46218454bdfd8c6457 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-26Revert "Mushu: Enable PCIe 1d.4 to enable dgpu"Shelley Chen
This reverts commit 1408798637125f1707ded7215e22461c623a79a8. Reason for revert: Causing backlight issues in device. Will reland after more debugging to figure out the root cause. BUG=b:159370566 BRANCH=None TEST=boot up device and make sure when kernel is booted, backlight comes up. Change-Id: I643854c6c805d262539bbb482808e8c322059a49 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-06-26mb/google/hatch: Set Reset Power Cycle Duration for hatch platformsSridhar Siricilla
Currently, Reset Power Cycle Duration is set with default value (4s). This adds around ~5 seconds of delay during power cycle or global reset. So, this patch sets PchPmPwrCycDur (Reset Power Cycle Duration) to 1s to minimize the delay. Delay with Power Cycle or Global Reset: Existing behaviour: S0->S5 -> [ ~5 seconds delay ] -> S5->S0 With the patch: S0->S5 -> [ ~2 seconds delay ] -> S5->S0 Also, correct the comment mentioned for PchPmSlpAMinAssert. The value(3) defined for PchPmSlpAMinAssert triggers signal assertion width to 98ms not 2s. Test=Verified on Hatch and Puff boards BUG=b:158634281 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I368c6716a92e06903a872f9e87ae0698eab95bdd Reviewed-on: https://review.coreboot.org/c/coreboot/+/42441 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-23hatch: Create wyvern variantPaul Fagerburg
Create the wyvern variant of the puff reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.1.1). BUG=b:158269582 BRANCH=None TEST=util/abuild/abuild -p none -t google/hatch -x -a make sure the build includes GOOGLE_WYVERN Signed-off-by: Paul Fagerburg <pfagerburg@google.com> Change-Id: Id7a090058d2926707495387f7e90b3b8ed83dac7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42551 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-23hatch: Create faffy variantEdward O'Callaghan
Create the faffy variant of the puff reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.1.1). V.2: Manually modified to keep Kconfig sorted. BUG=b:157448038 BRANCH=None TEST=util/abuild/abuild -p none -t google/hatch -x -a make sure the build includes GOOGLE_FAFFY Signed-off-by: Edward O'Callaghan <quasisec@google.com> Change-Id: I5f14c2d6144ce3c2e48488ca81f31b3c04dc5fb9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42717 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-23palkia: separate the gpio pins control for the second touchZhuohao Lee
There are two touch screen controllers on the Palkia device. One is on the lid; another is on the base. To support the different control path (for example: turning off the base's touch event when we don't want to use it however still keeping the lid's touch event), we use the different gpio pins to control the second touch. As a result, we need to modify the devicetree to adopt this change. With this change, we can control the primary and secondary touch screen controller respectively. BUG=b:149714955 TEST=lid/base touch screen works correctly Change-Id: I1f896e334e51c78300af724cbef8d57641ae5612 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-23mb/google/hatch: Make puff and variants share common mainboard.cEdward O'Callaghan
Here we consolidate some of the mainboard.c duplication between Puff and it's variants. Customizations can be done later via introducing a devicetree parameterisation. BUG=b:154071868 BRANCH=none TEST=none Change-Id: I75c2de7ae8efd544d800bc77e34e667c3afa4b01 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42672 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22mb/google/hatch: Stop AP power-off on Puff & variants cr50 updatesEdward O'Callaghan
Fix Puff and its variants to not shutdown the AP before the cr50 reboot. This is the same approach that Sarien do to remain on during a cr50 cycle. BUG=b:154071064 BRANCH=none TEST=none Change-Id: I5f92b4f769654b67c10c91e4cc7b2bce785e302f Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42497 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22mb/google/hatch: Make puff and variants share common dptf.aslEdward O'Callaghan
Here we consolidate some of the dptf.asl duplication between Puff and it's variants. Customizations can be done later either as a direct copy or preferably via introducing a #define. BUG=b:154071868 BRANCH=none TEST=none Change-Id: I35fa1e152adb5f04fb6ef1bd2448376cf9f37980 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
2020-06-22mb/google/hatch: Make puff and variants share common ec.hEdward O'Callaghan
Here we consolidate some of the ec.h duplication between Puff and it's variants. BUG=b:154071868 BRANCH=none TEST=none Change-Id: I13dfe09da5c7a19677b156063bb51a58bc059b93 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
2020-06-19Kconfig: Escape variable to accommodate new Kconfig versionsPatrick Georgi
Kconfig 4.17 started using the $(..) syntax for environment variable expansion while we want to keep expansion to the build system. Older Kconfig versions (like ours) simply drop the escapes, not changing the behavior. While we could let Kconfig expand some of the variables, that only splits the handling in two places, making debugging harder and potentially messing with reproducible builds (e.g. when paths end up in configs), so escape them all. Change-Id: Ibc4087fdd76089352bd8dd0edb1351ec79ea4faa Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-06-18mb/google: remove cannonlake dptf.asl include file from dsdt filesSumeet R Pawnikar
Remove cannonlake dptf.asl include file from all the dsdt files as per soc/intel/common/acpi code changes for dptf. BUG=None BRANCH=None TEST=Build and boot on the system Change-Id: I961a3ecb27e7bb7bb0b98c8630900bada0531639 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-18mb/google/hatch: fix variants' selection of CHROMEOS_DSM_CALIBMatt DeVillier
CHROMEOS_DSM_CALIB requires/selects CHROMEOS, so only select if CHROMEOS already selected, otherwise building for non-ChromeOS targets fails. Test: build HELIOS for non-ChromeOS target (Tianocore payload) Change-Id: Ic0fd3b0a0efbc5a1f6896eb379569a55cb0f67f8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-17mb/google/hatch: mushu: Add F75303 temp sensor to dptfPuthikorn Voravootivat
Update the following in dptf.asl - Add support for TSR3 - Change TSR0/TSR1/TSR2/TSR3 From: Charger, 5V, GPU , None To: Charger, GPU, F75303_GPU, F75303_GPU_POWER - Adjust fan/cpu trip point accordingly - Fix formating in dptf.asl - Throttle charger when TSR0 (charger) is hot instead of throttle CPU BUG=b:158676970 BRANCH=None TEST=grep . /sys/class/thermal/thermal_zone5/{type,temp} /sys/class/thermal/thermal_zone5/type:TSR3 /sys/class/thermal/thermal_zone5/temp:50800 Change-Id: Iedbb6bc7c1e59a027119c70791b9bc8a4d83ff87 Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42270 Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Bob Moragues <moragues@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17mb/google/puff: add MST and LSPCON details to variants devicetreeShiyu Sun
Added device hid info to the MST and LSPCON devices on kaisa, duffy and noibat. BRANCH=None BUG=b:156546414 TEST=None Signed-off-by: Shiyu Sun <sshiyu@chromium.org> Change-Id: I7b54512cd88e7280374c188315cabc2fba197f69 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-06-14mb/google/puff: add MST and LSPCON details to devicetreeShiyu Sun
Added device hid info to the MST and LSPCON devices. BRANCH=None BUG=b:156546414 TEST=Manual tested and able to see update on sysfs and ssdt table Signed-off-by: Shiyu Sun <sshiyu@chromium.org> Change-Id: Iaef6c08f241ea671d1487a8524162dbb438b8e98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-06-14mb/google/hatch/vr/puff: Set up PL2 and PsysPL2Tim Chen
This patch adds correct PL2 baseline setting and PsysPL2 for different SKUs. There is no way to identify the barral jack power rating, the assumption is following that ships with the product: 1. i3/i5/i7: 90W BJ 2. Celeron/Pentium: 65W BJ For Type-C adapter, we don't have Pcritcial (10ms) data, keeps the original settings as 90% of adapter rating for PsyspL2/PL4 and PL2 as min(PL2, 0.9n) where n is adapter rating power. BUG=b:143246320 TEST=Run with U62 and Celeron CPU and ensure the PL2 settings are correct Change-Id: Ib16d4f65707801b430f06892ab45ecfa7551593f Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-06-14mb/google/hatch: Switch USB2 port1 and port3 on NoibatEdward O'Callaghan
Switch USB2 port1 and port3 for noibat due to circuit change. BUG=b:154585046,b:156429564 BRANCH=none TEST=none Change-Id: I711038624f3efe397be73c29a940b3e17802598f Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42296 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-12mb/google/hatch: Remove unused USB2 port from NoibatEdward O'Callaghan
This port isn't packed on the board, so remove from the devicetree. BUG=b:154585046,b:156429564 BRANCH=none TEST=none Change-Id: Ib4aee337f67453adcebff7e93e25db7a838e3b2d Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42269 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-12mb/google/puff: Update i2c[2] and i2c[3] rise and fall timesSam McNally
BRANCH=none BUG=b:158713330 TEST=Flashing the LSPCON firmware works Change-Id: Ib371f6954115145047c70cfd25262026cce087fd Signed-off-by: Sam McNally <sammc@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-06-10mb/google/hatch: drop VBOOT_LID_SWITCH from hatch baseboardMatt DeVillier
Selecting VBOOT_LID_SWITCH under BOARD_GOOGLE_BASEBOARD_HATCH creates a requirement for VBOOT, and prevents building in the non-vboot/non-ChromeOS case. As this symbol is already selected by CHROMEOS below, there's no need for the baseboard (and only one of the two) to select it, so don't. Change-Id: I060e82185997bce451648173dd97dd6a3d5d237f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42137 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-09mb/google/hatch/vr/puff: Set up PL2 and PsysPL2Gaggery Tsai
This patch adds correct PL2 baseline setting and PsysPL2 for different SKUs. There is no way to identify the barral jack power rating, the assumption is following that ships with the product: 1. i3/i5/i7: 90W BJ 2. Celeron/Pentium: 65W BJ For Type-C adapter, we don't have Pcritcial (10ms) data, keeps the original settings as 90% of adapter rating for PsyspL2/PL4 and PL2 as min(PL2, 0.9n) where n is adapter rating power. BUG=b:143246320 TEST=Run with U62 and Celeron CPU and ensure the PL2 settings are correct Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Change-Id: If7de614d58366158a566563990ee1ecc8c0110bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/41555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-06-03mb/google/hatch: Enable the CSE Lite SKU for Puff variantsV Sowmya
This patch enables enables the CSE Lite SKU for all the puff variant boards. BUG=b:143229683 TEST=Build and boot puff with CSE Lite SKU. Cq-Depend: chrome-internal:3046770 Change-Id: I0de6bca162b01870ca554ae97bc4a41cf66fef18 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-03mb/google/hatch: Modify the puff fmd files to support CSE Lite SKUV Sowmya
This patch modified the puff fmd files to support CSE Lite SKU. * Reduce the SI_ALL size to 3MiB since ME binary size is less than 2.5MiB. * Increase the FW_MAIN_A/B size to accommodate the ME_RW update binary with CSE Lite SKU. BUG=b:154561163 TEST=Build and boot puff with CSE Lite SKU. Cq-Depend: chrome-internal:3046770 Change-Id: I4d39a1bdeabf48fc740da67539f48a9ff72c442c Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41198 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02src: Remove unused 'include <bootstate.h>'Elyes HAOUAS
Change-Id: I54eda3d51ecda77309841e598f06eb9cea3babc1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-01mb/google/hatch: Add Noibat variantEdward O'Callaghan
A verbatim copy of variants/puff. BUG=b:156429564 BRANCH=none TEST=none Change-Id: I8c76d468177e1f3fcab53e0790599041b1a944d8 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41851 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-29mb/google/hatch: Select the fmd files for puff baseboardV Sowmya
This patch selects the fmd files based on config BOARD_GOOGLE_BASEBOARD_PUFF and also renames the files to align with basebaord name and layout size. BUG=b:154561163 TEST=Built puff and verified that it selects the right fmd file. Change-Id: Ice6196ca778c6c118ce89e1510a445339a5c3455 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-18 10:14:51 +0000