coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-04-06	mb/google/kahlee: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-18	mainboard/google: Remove copyright notices	Patrick Georgi
2019-09-04	mb/google/kahlee/treeya: Update the memory timing table for Treeya to the 2T ...	Peichao Wang
2019-03-08	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	Julius Werner
2019-01-06	device: Use pcidev_path_on_root()	Kyösti Mälkki
2018-12-19	mb/google/kahlee: Remove board_id check for Liara 2T timings	Martin Roth
2018-11-23	mb/google/kahlee: Enable 2T mode for liara in DVT phase	Chris Wang
2018-11-09	mb/google/kahlee: Tune eDP panel initialization time	Chris Wang
2018-10-24	mb/google/kahlee: Enable 2T mode for liara	chris wang
2018-07-30	mb/google/kahlee/OemCustomize.c: Enable eDP HIGH_VDIFF	Richard Spiegel
2018-02-20	mb/google/kahlee/OemCustomize.c: Disable bank interleave	Richard Spiegel
2017-12-12	soc/amd/common: Move Agesa related headers	Richard Spiegel
2017-11-14	mb/google/kahlee: Remove direct AGESA header includes	Martin Roth
2017-11-10	google/kahlee: Add defines in OemCustomize.c	Marshall Dawson
2017-11-10	google/kahlee: Move DRAM clear override to devicetree	Marshall Dawson
2017-11-04	mainboard/google/kahlee: remove unused FILECODE macro	Aaron Durbin
2017-09-26	binaryPI boards: Fix indirect AGESA.h include	Kyösti Mälkki
2017-09-20	google/kahlee: Prevent AGESA memory clear	Marc Jones
2017-09-20	google/kahee: Fix number of memory channels	Marc Jones
2017-07-27	google/kahlee: Update for single DIMM	Marshall Dawson
2017-07-27	google/kahlee: Start Kahlee mainboard	Marc Jones