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path: root/src/mainboard/google/kahlee/variants
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2018-09-25mb/google/kahlee/variants/liara: Disable NbP-state on LiaraAmanda Huang
To disable NB-Pstate, the system wouldn't auto restart on EVT board when idling. BUG=b:116082728 Change-Id: Iec4f0355cb6eb1c2b0372e3d131cc5e6ba36635e Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-24soc/amd/stoneyridge/romstage.c: Move STAPM code to SOC specificRichard Spiegel
STAPM programming was created inside function OemCustomizeInitEarly(). It should be SOC specific, and called by agesawrapper just before the call to OemCustomizeInitEarly(). BUG=b:116196626 TEST=build and boot grunt Change-Id: I8a2e51abda11a9d60a9057b38f2a484e1c8c9047 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28705 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-21mainboard/google/kahlee: allow oem.bin file to update smbiosMartin Roth
Grunt variants need a way to customize the mainboard vendor based on the platform. For future boards, this can probably be done via CBI, but grunt doesn't support that method. BUG=b:79874904 TEST=Build, boot, see updated mainboard vendor Change-Id: I997dc39c7f36f70cf4320ef335831245889eb475 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/28651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@google.com>
2018-09-18mb/google/kahlee/variants/careena/devicetree.cb: Set STAPM valuesRichard Spiegel
AMD has tested careena, and for the time being is recommending a scalar of 68%, power limit of 7.8 W and time constant of 2500. Using new STAPM configuration code, set the desired values. BUG=b:111561217 TEST=none, code was tested with grunt. Change-Id: I42671ab0e66b21dc4f8c8c326c1fa33328b1390e Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-09-18mainboard/google/kahlee: Set EMMC reset pin to output lowMartin Roth
While the pin was set to a pull-down, with the external pull-up, this wasn't enough to keep the pin low. Set to output low to drive to 0V. TEST=Boot grunt, verify EMMC_BRIDGE_RST is 0V. BUG=b:115661061 Change-Id: Ife014b8a879274df5d892c1de386976808de1df0 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/28649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-09-18mainboard/google/kahlee: Don't set global subsystem IDsMartin Roth
These values override the default subsystem IDs, and aren't needed. BUG=b:113253260 TEST=Boot grunt Change-Id: I3c56534b094ede8d8200b72f4433a891d0094064 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/28652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-09-17mb/google/kahlee/variants/baseboard: Set STAPM percentageRichard Spiegel
Default STAPM percentage causes a lot of thermal throttling on grunt. AMD experimented with 80%, it works for grunt. This is initial code to provide easy change path for other grunt based platforms. BUG=b:111608748 TEST=build and boot grunt. Change-Id: I22863f6ed76152bf872fce3e275f8a7fd8077504 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-12mainboards: Add SMMSTORE region in chromeos configsPatrick Georgi
Only for those that are x86 and also have a RW_LEGACY region. The assumption is that all devices touched have 64k block sizes when choosing size and alignment of the region. Change-Id: I12addb137604f003d1296f34f555dae219330b18 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/28532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-09mainboard/google/kahlee: Reset trackpad & touchscreenMartin Roth
AMD chips don't hold off a reset to the end of I2C transitions, so devices on the i2c bus can be left in a bad state. To avoid this, make sure the trackpad and touchscreen chips get disabled during boot. BUG=b:114411165 TEST=build, reboot watch trackpad enable go low Change-Id: Ie50f4a102249df79517da571a6e768dba804cd57 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/28538 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-05mainboard/google/kahlee: Enable the BCLK bufferMartin Roth
Set GPIO135 high to enable audio through the BCLK buffer. BUG=b:113559558 TEST=None BRANCH=grunt Change-Id: I1dcecf5960d3c91e0c2165e7f8856ff423c06e8c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/28482 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-02mainboard/google/kahlee/var/liara: Enable Synaptics touchpad deviceCrystal Lin
Enable Synaptics touchpad device for liara BUG=b:113309346 BRANCH=master TEST=Verify touchpad on liara works with this change Change-Id: Icdafe34a00fd55d5338fa07ffa304e48e7b85e7b Signed-off-by: Crystal Lin <crystal_lin@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-31mb/google/kahlee/variants/liara: Update Audio/H1/TP i2c timingsChris Zhou
After adjustment on Liara Proto Audio: 399.2 KHz H1: 398.3 KHz TP: 399.0 KHz BUG=b:113319200 BRANCH=master TEST=emerge-grunt coreboot chromeos-bootimage measure by scope Change-Id: Ibba8c823ed8451a804cf731d49e7568a94ac7c6b Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-08-28google/grunt: Reset BayHub EMMC freq to SD base CLK 50MHzKevin Chiu
Bayhub eMMC controller default runs SD base 50MHz at the first power on. After boot into OS, mmc kernel driver will config controller to HS200/208MHz and send MMC CMD21 (tuning block). But Bayhub PCR register 0x3E4[22] (eMMC MODE select) is not clear after system warm reset. So eMMC will still run 208Mhz but there is no block tuning cmd in depthcharge. It will cause two Sandisk eMMC (SDINBDA4-64G-V/SDINBDA4-32G-V) to fail to load kernel and trap in 0x5B error (No bootable kernel found on disk). BUG=b:111964336 BRANCH=master TEST=emerge-grunt coreboot Change-Id: Ic080682e67323577c7f0ba4ed08f8adafca620cc Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/28353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-27mb/google/kahlee: Fix I2C bus 0 timing for GruntAkshu Agrawal
This commit fixes the values and thus fixes the issue of audio device not getting detected on random reboots. Change-Id: I34a4f62815d192005c3324d4f71b0aba377fe738 Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-on: https://review.coreboot.org/28280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2018-08-17google/grunt: Update TP/TS/H1 i2c timingsKevin Chiu
After adjustment on Careena EVT TP: 400.0 KHz TS: 396.8 KHz H1: 396.8 KHz BUG=b:112663934,b:112664258 BRANCH=master TEST=emerge-grunt coreboot measure by scope Change-Id: I9eeaf9290d95969a283f14618878e28faf0ea46f Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/28119 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-17mainboard/google/kahlee: Fix ACPI method Not Serialized errorMarc Jones
Fix the following failure from FWTS: FAILED [LOW] AMLAsmASL_MSG_SERIALIZED_REQUIRED: Test 1, Assembler remark in line 131 Line | AML source -------------------------------------------------------------------------------- 00128| } 00129| } 00130| }) 00131| Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings | ^ | Remark 2120: Control Method should be made Serialized (due to creation of named objects within) 00132| { 00133| Name (RBUF, ResourceTemplate () 00134| { ================================================================================ ADVICE: (for Remark #2120, ASL_MSG_SERIALIZED_REQUIRED): A named object is created inside a non-serialized method - this method should be serialized. It is possible that one thread enters the method and blocks and then a second thread also executes the method, ending up in two attempts to create the object and causing a failure. BUG=b:112476331 TEST= Run FWTS. Change-Id: I6f4f6e7e94b01f673afc97d9415481ee63e406e3 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/28122 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-16google/grunt/aleena: Update Raydium TS device ACPI nodesTim Chen
change I2C irq to EDGE trigger BUG=b:112616824 BRANCH=master TEST=emerge-grunt coreboot Raydium TS is working. Change-Id: I86ec32bb3f2626e65d76c3259e3c4244a970e5de Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-15google/grunt: Remove BayHub EMMC driving strength overrideKevin Chiu
Side effect was observed that after override BayHub EMMC driving strength to the max, EMMC CLK will be reduced to 51.x Mhz from 200 Mhz. This will cause OS installation fail on Samsung EMMC sku. BUG=b:111964336 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I848ab0cae474b15fbc4264c8ade63d5c6b4e489d Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/28084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-13mb/google/kahlee: Remove unneeded blank linePaul Menzel
Change-Id: I189c981f3334836ab24bbc74491e9b58a2d403a4 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/27921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-08-09google/grunt: Override BayHub EMMC driving strengthKevin Chiu
Careena EVT SanDisk EMMC sku has high fail rate of 0x5B reboot failure. It'll need to increase 1.8V EMMC CLK/CMD, Data driving strength for this issue. CLK[6:4] CMD,DATA[3:1] original register value: 0x6B enhanced: 0x7F BUG=b:111964336 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I3db38ff12c566c258895c6643008a0472ca528bb Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/27816 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-06mainboard/google/kahlee: Add PSPP override settingMarc Jones
Add default PSPP AGESA setting for Kahlee/Grunt mainboards. BUG=b:112020107 TEST= build test Change-Id: I8a8605402379de88a04f3a16553c308513fa1531 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/27784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-06mb/google/kahlee: Disable SATA in all boardsRichard Spiegel
Kahlee based boards don't use SATA, so disable SATA on all boards to save power. BUG=b:112139043 TEST=Build and boot grunt, checked the absence of SATA PCI. Change-Id: I6a12c03a5a95b1c8b40609a3fe656df92548b80b Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-30mainboard/google/kahlee: Pad SPD serial Number with spacesMartin Roth
All of the other SPDs are padded with spaces to make them use the full size of the serial number field. The hynix-H5AN8G6NCJR-VKC SPD was not, and that seems to be causing problems with some tools. BUG=b:111903749 TEST=Mosys correctly identifies memory on board using that SPD. Change-Id: I0e831873acab2f6fc7d76e85647198d3b7af4b12 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/27676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
2018-07-28mainboard/google/kahlee: Fix Micron MT40A512M16LY-075:E POST CRC errorKevin Chiu
Fix Micron MT40A512M16LY-075:E DRAM SPD CRC error in AGESA MemSPDChecking: ERROR Event: 04011200 Data: 0, 0, 0, 0 BUG=b:111901461 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I85c82fd9294f9146fc23e649436cbcc337c4c961 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/27657 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-25mb/google/x86-boards: Get rid of power button device in corebootFurquan Shaikh
As per the ACPI specification, there are two types of power button devices: 1. Fixed hardware power button 2. Generic hardware power button Fixed hardware power button is added by the OSPM if POWER_BUTTON flag is not set in FADT by the BIOS. This device has its programming model in PM1x_EVT_BLK. All ACPI compliant OSes are expected to add this power button device by default if the power button FADT flag is not set. On the other hand, generic hardware power button can be used by platforms if fixed register space cannot be used for the power button device. In order to support this, power button device object with HID PNP0C0C is expected to be added to ACPI tables. Additionally, POWER_BUTTON flag should be set to indicate the presence of control method for power button. Chrome EC mainboards implemented the generic hardware power button in a broken manner i.e. power button object with HID PNP0C0C is added to ACPI however none of the boards set POWER_BUTTON flag in FADT. This results in Linux kernel adding both fixed hardware power button as well as generic hardware power button to the list of devices present on the system. Though this is mostly harmless, it is logically incorrect and can confuse any userspace utilities scanning the ACPI devices. This change gets rid of the generic hardware power button from all google mainboards and relies completely on the fixed hardware power button. BUG=b:110913245 TEST=Verified that fixed hardware power button still works correctly on nautilus. Change-Id: I733e69affc82ed77aa79c5eca6654aaa531476ca Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-23mb/google/kahlee: Update i2c timingsMatt Wells
Change the I2c timings to the latest measurements. BUG=b:72442912 TEST=Boot grunt Change-Id: I6f9538d26b77ae952ad585e569b3a836e1a09da2 Signed-off-by: Matt Wells <dawells@google.com> Reviewed-on: https://review.coreboot.org/27553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-20mainboard/google/kahlee: Create Liara variantMartin Roth
This is based on the Grunt variant. BUG=b:111607004 TEST=Build Liara Change-Id: I8f23e972be0d1665c736d61621a0caaa4c4c5551 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/27539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-07-20mainboard/google/kahlee: Create Aleena variantMartin Roth
This is based on the Grunt variant. BUG=b:111606874 TEST=Build Aleena Change-Id: I6fd42db6f9f309c3c375b670cd22f818555e4195 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/27538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-07-17mainboard/google/kahlee: Don't default backlight onMarc Jones
Keep the backlight off until it is needed. BUG=b:72694972 TEST=Backlight turns on at ChromeOS splash screen, not prior. Change-Id: Ia1aba787734e2976146ecd305dd821f0b326f0db Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/27489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-17mainboard/google/kahlee: Enable backlight on resumeMarc Jones
BUG=b:72694972 TEST=Backlight turns on ChromeOS resume Change-Id: I452e2ea94b508b137cf52301df5d2d1ad5c9ab70 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/27488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-17mainboard/google/kahlee: Add mainboard resume functionMarc Jones
Add the mainboard resume function and __weak variant override. Change-Id: I808734208bd1ce81428771ea203709b53db56cd3 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/27486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-16google/grunt: fix thermal zone CPU temperature reportKevin Chiu
there are 3 thermal sensors and index is: 0: 1 Charger 1: 1 SOC 2: 0 CPU it needs to adjust sensor to index 2 to have correct CPU temperature. BUG=b:111284412 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I27afb6c5b64b0c39d6db15e6c61ea16a1fda1ca3 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/27469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-13mainboard/google/kahlee: Add more 3 SPD filesMartin Roth
BUG=b:111195311 TEST=Build grunt, verify SPDs are present Change-Id: Ief5ed5c3ca1d96b36926f1fc84c344a8d66dcda5 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/27437 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-11mainboard/google/kahlee: Update existing SPD filesMartin Roth
Add an extra space after 8th value on each line to make it easier to count the values. Update the empty spd to remove two random 0x80 values. BUG=None TEST=None Change-Id: If330dbf0c133f65aedddc58ecb351a80b0e45a05 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/27423 Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-11mainboard/google/kahlee: Add additional SPDs for variantsMartin Roth
BUG=b:111079089, b:80375243 TEST=Build grunt, verify that SPDs are included. Change-Id: Idb03a3fa0842f7f89bb8c66dedbb8a0b293569be Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/27422 Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-06google/grunt: Update Raydium TS device ACPI nodesKevin Chiu
change I2C irq to EDGE trigger BUG=b:110962003 BRANCH=master TEST=emerge-grunt coreboot Raydium TS is working. Change-Id: Iff3acf4199d23b29dff209ec1c03a731679c6cbe Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/27327 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-15mainboard/google/kahlee: Enable keyboard backlight for careena specific SKUKevin Chiu
Enable keyboard backlight by Careena SKUID Set to 10% as the same as google/snappy project BUG=b:110065836 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I7d302c4f50528b0e6b7ef4d990f342a69cff34f5 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/27021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-11mainboard/google/kahlee: Remove unused baseboard codeMartin Roth
This code is no longer needed. BUG=b:107537694 TEST=Build & boot on grunt Change-Id: I71ad01f0d4c69a618d564e514ed99550b72a6b44 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26778 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-11mainboard/google/kahlee: Remove Kahlee variantMartin Roth
This code is no longer needed. Removing Kahlee options allows some Kconfig options to be optimized. BUG=b:77693343 TEST=Build Grunt, verify that nothing's changed. Change-Id: I4eeeee7f35381bba8760c8a530251c475d0ee29b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-08mainboard/google/kahlee: Turn on backlight for all SKUsMartin Roth
Careena uses a different keyboard backlight method, so let the EC handle the different SKUs and backlight methods. BUG=b:80106042 TEST=None Change-Id: I47f7a9ac13538f0216fbb0f64fdd22f66097820c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-06-08src/mainboard/kahlee: Use common mainboard and romstage filesMartin Roth
Until these need to be separated out, use a common file for mainboard and romstage to make upkeep easier. BUG=b:80106042 TEST=Build Grunt and Careena Change-Id: I65188bee1958d442bfe64637c3b93dc05583a686 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-06-08mb/google/kahlee: Configure EC_PCH_WAKE_L as an SCI sourceDaniel Kurtz
Configuring EC_PCH_WAKE_L as an SCI enabled GPIO allows the EC to wake the AP from S3 on keyboard presses. BUG=b:109759838 TEST=(1) powerd_dbus_suspend (2) press a key on the internal keyboard => system resumes from S3 Change-Id: I30f72460fd588706f91f4fc3ea4ff007c96e9ebe Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/26931 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-07mainboard/google/kahlee: Remove colon from filenamesMartin Roth
Change-Id: I3e0ca62ad88aea5c99f9f0902ad8553656469a1c Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/26936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-03mb/google/kahlee: Remove #include <soc/smi.h>Richard Spiegel
Because of struct sci_source table of events that have to generate SCI or SMI, <soc/smi.h> was included to kahlee/grunt gpio.c files. However, new code transfered most of SCI/SMI/interrupt programming (with exception of events not associated to a GPIO pin), and therefore smi.h is now included by gpio.h. It was also added to some other files where they are not needed. Only smihandler.c truly needs it. Remove the includes. BUG=b:78139413 TEST=build and boot grunt. Change-Id: I64cf0796103a5226ddace03d05d94160bf93aa69 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/26721 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-31mainboard/google/kahlee: Add careena variantMartin Roth
Add Careena variant, based on the grunt board. BUG=b:80106042 TEST=Build Careena Change-Id: I87a24f6d8115aacf5b21181f3820cf2718ad252a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-30mainboard/google/kahlee: move grunt's chromeos.fmd to baseboardMartin Roth
The chrmoeos.fmd file will be common across variants, so move it out of of grunt directory and into the variants/baseboard directory. BUG=b:80106042 TEST=Build grunt Change-Id: I259d85f60c5e19e00f7d9149542bcfdcc6dfaf4f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-30mainboard/google/kahlee: move SPDs to variants/baseboard/spdMartin Roth
The SPD files will be common to many of the mainboards, so move them out of grunt and into the variants/baseboard directory. BUG=b:80106042 TEST=Build grunt, make sure spd.bin is the same. Change-Id: I53975a46a8c7d7e519bb6f7ef6ccd0b817ac4c92 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26523 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-27stoneyridge GPIO: Create and use PAD_INT for interrupt pinsRichard Spiegel
The default interrupt control for GPIO pins within stoneyridge is for edge triggered, high. However, sometimes these need to change, or maybe the interrupt needs to be reported or delivered. This was the case of platform grunt, where the interrupt related bits were being changed afterwards. Ideally all the bits should be programmed through the same procedure. Create several PAD_INT definitions (for general configuration, for trigger configuration and for interrupt type configuration) and change function sb_program_gpios() to accept the output from PAD_INT_XX and program all the necessary bits while keeping compatibility with other PAD_XX definitions. BUG=b:72875858 TEST=Add code to report GPIO and interrupt configuration, build grunt and record a baseline. Add new code, rebuild grunt and record a test output. Compare baseline against test, there should be no change in GPIO or interrupt programming. Remove code that reports GPIO/interrupt configuration. Change-Id: I3457543bdf64ec757fd82df53c83fdc1d03c1f22 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-25mb/google/kahlee: Init APU_BIOS_FLASH_WP_L GPIO to reset stageDaniel Kurtz
GPIO APU_BIOS_FLASH_WP_L is first read in ROM stage to determine the state of the BIOS FLASH Write Protect signal at boot. The result of this read accumulated in the vboot state that's passed on to the upper layers of the stack. Therefore this GPIO must be configured as a "reset stage" GPIO, not a "RAM" stage GPIO. BUG=b:79866233 TEST=firmware_WriteProtect Change-Id: I1d96ab4bbfeaf9db9f74cf0c58cbab2104079bf7 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/26498 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-22mainboard/google/kahlee: Update RW_LEGACY size in fmapMartin Roth
Add the unused space to the RW_LEGACY area. BUG=b:79433466 TEST=None Change-Id: I897d1dcf75466fe9bdb814c8a9db0fecb5c42af6 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-07 22:41:21 +0000