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2021-03-15mb/google/kahlee: remove get_gpe_tableFelix Held
Since no board overrides the weak get_gpe_table function, gpe_configure_sci wasn't called for any variant, so drop the function. TEST=none Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3de204cc808449b625e1fa1e79fe653608e4b88a Reviewed-on: https://review.coreboot.org/c/coreboot/+/51474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-08soc/amd,mb/google/,mb/amd: Move sleepstates.aslRaul E Rangel
This file is common for all the AMD platforms. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I10ee600b4bcd7aaff39bfab075eb4dbc9096b435 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51299 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01mb/: Drop print of MAINBOARD_PART_NUMBERKyösti Mälkki
Change-Id: Ie3870bc666acaea316f00b205de512cf790e720c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2021-02-24mb/amd,google: Rename static functions to mainboard_enableKyösti Mälkki
Let's not have 7 boards of all use a different name for the .enable_dev function in mainboard chip_operations. Change-Id: I07f3569e6af85f4f1635595125fe2881ab9ddd43 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-20AGESA,binaryPI boards: Move common PCBA in ASLKyösti Mälkki
Change-Id: I9d502882c4ddb54af1da42a41591804da2cee0ac Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-20AGESA,binaryPI boards: Drop unused variables in ASLKyösti Mälkki
Change-Id: I1d1323ab8bb8565c05fd50697e29c61f9932a2c7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-20sb,soc/amd: Drop OSFL method in ASLKyösti Mälkki
Variable OSVR had a static value of 3 and OSFL() did not actually call _OSI or _OS methods. The conditional in HDA _INI method of OSVR is dropped and use of DMA NoSnoop attribute remains disabled to retain previous behaviour. For soc/amd/picasso a different decision was made in CB:40782 as HDA _INI method was just dropped and default configuration enables use of DMA NoSnoop attribute. Change-Id: I967b7b2afbb43253cccb4b77f6c44db45e2989e4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50592 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14AGESA,binaryPI boards: Drop OSV in ASLKyösti Mälkki
Not referenced anywhere in ASL. Change-Id: I52ac4722e48e1cc377386316dc034fb45a98181a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50471 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11ACPI: Move PICM declarationKyösti Mälkki
Variable PICM was not inside GNVS region and can use a static initialisation value. For most AMD platforms PICM default changes from 1 to 0. Fix comments about PICM==0 used to indicate use of i8259 PIC for interrupt delivery. Change-Id: I525ef8353514ec32941c4d0c37cab38aa320cb20 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49905 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-04src: Remove useless comments in "includes" linesElyes HAOUAS
Change-Id: Ide5673dc99688422c5078c8c28ca5935fd39c854 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-03src: Remove unused <boardid.h>Elyes HAOUAS
Change-Id: I960870fabde1dacfe52a8a35c253b0bd097d3e10 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-01-28bayhub bh720: Factor out common HS200 init codeAngel Pons
Except for one debug print in sarien, both functions are identical. Move them to driver code to avoid unnecessary redundancy. Change-Id: I82635a289e3c05119eab4ee1f7a6bf3a8a1725c1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-01-28ACPI: Move include for <vc/google/chromeos.asl>Kyösti Mälkki
Change-Id: I4356a8bda71e84afe8c348d366479c5006bf2459 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49796 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-27ACPI: Add top-level ASLKyösti Mälkki
Objects that are created with acpigen need to be declared with External () for the generation of dsdt.asl to pass iasl without errors. There are some objects that are common to all platforms, and some that should be declared only conditionally. Having a top-level ASL helps to achieve this. Change-Id: Ibaf1ab9941b82f99e5fa857c0c7e4b6192c74330 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-27sb,soc/amd: Rename PMOD to PICM in ASLKyösti Mälkki
Use the same variable name as soc/intel to implement a common _PIC method at top-level ASL. Change-Id: I48f9e224d6d0101c2101be99cd18ff382738f0dd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-26soc/amd: Refactor some ACPI S3 callsKyösti Mälkki
Do not pass ACPI S3 state as a parameter, by locally calling acpi_is_wakeup_s3() compiler has better chance for optimizing HAVE_ACPI_RESUME=n case. Test for acpi_s3_allowed() is already included in the implementation of acpi_is_wakeup_s3() and is removed as redunandant. For ramstage, acpi_is_wakeup_s3() evaluates to romstage_handoff_if_resume(). Change-Id: I6c1e00ec3d5be9a47b9d911c73965bc0c2b17624 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49838 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-25mb/google/kahlee: Deduplicate now-equivalent mainboard.cAngel Pons
The only difference is an additional include that is no longer needed. Change-Id: I0053d03aa4d05f5c0fa833d8634419b6667e38a7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49832 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-25bayhub bh720: Configure VIH tuning via devicetreeAngel Pons
There's no need to repeat the same code on every board. Change-Id: I2e19decfe8609fa644e609673a56ee5109bafefa Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49831 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-24arch/x86: Use wildcard for mb/smihandler.cKyösti Mälkki
Change-Id: I306f8cd74af62c0cd30f445d20c47f774f122481 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49247 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-14soc/amd/stoneyridge: use SOC_AMD_COMMON_BLOCK_UARTFelix Held
Since the functions that get called by the coreboot console initialization code aren't in the SOC-specific code anymore, the SOC's uart.c can be included unconditionally in the build now. This also replaces the STONEYRIDGE_UART Kconfig option with the common AMD_SOC_CONSOLE_UART one. Change-Id: I09c15566a402895d6388715e8e5a802dc3c94fdd Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49375 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-13mb/google/kahlee,zork: Use mainboard_fill_gnvs()Kyösti Mälkki
Change-Id: Ic9cdcc497bf1a9f5bfed5e6d95040bfa602b0b89 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48732 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-13mb/google/kahlee: move SMI/SCI GPIO setup to ramstageFelix Held
SMIs and SCIs aren't used before ramstage or the OS, so there should be no need to already set them up in romstage. Not using this GPIO configuration functionality allows untangling the GPIO and smi_util code and only linking smi_util in ramstage in follow-up patches. In romstage the pins get initialized as inputs with pull-up, so that at least that part still matches the configuration before this patch. BUG=b:175386410 Change-Id: I733bb91ef60dc66093781a376a2e9837f5209671 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48608 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-12-02cbfs: Simplify load/map API names, remove type argumentsJulius Werner
This patch renames cbfs_boot_map_with_leak() and cbfs_boot_load_file() to cbfs_map() and cbfs_load() respectively. This is supposed to be the start of a new, better organized CBFS API where the most common operations have the most simple and straight-forward names. Less commonly used variants of these operations (e.g. cbfs_ro_load() or cbfs_region_load()) can be introduced later. It seems unnecessary to keep carrying around "boot" in the names of most CBFS APIs if the vast majority of accesses go to the boot CBFS (instead, more unusual operations should have longer names that describe how they diverge from the common ones). cbfs_map() is paired with a new cbfs_unmap() to allow callers to cleanly reap mappings when desired. A few new cbfs_unmap() calls are added to generic code where it makes sense, but it seems unnecessary to introduce this everywhere in platform or architecture specific code where the boot medium is known to be memory-mapped anyway. In fact, even for non-memory-mapped platforms, sometimes leaking a mapping to the CBFS cache is a much cleaner solution than jumping through hoops to provide some other storage for some long-lived file object, and it shouldn't be outright forbidden when it makes sense. Additionally, remove the type arguments from these function signatures. The goal is to eventually remove type arguments for lookup from the whole CBFS API. Filenames already uniquely identify CBFS files. The type field is just informational, and there should be APIs to allow callers to check it when desired, but it's not clear what we gain from forcing this as a parameter into every single CBFS access when the vast majority of the time it provides no additional value and is just clutter. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ib24325400815a9c3d25f66c61829a24a239bb88e Reviewed-on: https://review.coreboot.org/c/coreboot/+/39304 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02soc/amd: factor out common SMI/SCI enums and function prototypesFelix Held
At least a part or the remaining definitions in the soc-specific smi.h files are also common, but those have to be verified more closely. Change-Id: I5a3858e793331a8d2ec262371fa22abac044fd4a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-13mb/google/kahlee: Configure IRQs as level triggered for HID over I2CKarthikeyan Ramasubramanian
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx BUG=b:172846122 TEST=./util/abuild/abuild Change-Id: Ib2f203b5f5eea5c25cfd4543f5ed9f15101b1735 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-13mb/*/*/dsdt.asl: Drop useless comments in DefinitionBlock()Elyes HAOUAS
Change-Id: I1e0489ec6730760f74102cdd00e4aaa66975d69a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-10-13mainboard/*/*/dsdt.asl: Make DefinitionBlock's AMLFileName uniformElyes HAOUAS
Make output AML file name uniform. Change-Id: Ic6cac4748a6159c695888b2737ada677d91f4262 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-13{src/mb,util/autoport}: Use macro for DSDT revisionElyes HAOUAS
Change-Id: I5a5f4e7067948c5cc7a715a08f7a5a3e9b391191 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-09-23treewide: rename GENERIC_SPD_BIN to HAVE_SPD_BIN_IN_CBFSMichael Niewöhner
The name GENERIC_SPD_BIN doesn't reflect anymore what that config is used for, so rename it to HAVE_SPD_BIN_IN_CBFS. Change-Id: I4004c48da205949e05101039abd4cf32666787df Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45147 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-22mb/google: Drop unneeded empty linesElyes HAOUAS
Change-Id: I4151d1a6ce94763432f307fbc8bc4afe229856ea Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-06mb: remove duplicated Make code for spd.bin generationMichael Niewöhner
Drop duplicated code for spd.bin generation that is provided globally in lib/Makefile.inc. For all affected boards it has been verified that the output binary functionally matches the original one. The changed execution order of Make instructions influenced the cbfs file order. Hence, the rom images can't be compared directly. Thus, the output files of the two timeless abuild runs have been compared. Further, it was verified that the final files in cbfs stay identical, by comparing the extracted cbfs of each board. The boards (possibly) needing modification could be found with something like this (with false positives, though): find src/mainboard -name Makefile.inc | \ xargs egrep 'SPD_BIN|SPD_DEPS' | cut -d: -f1 | sort -u Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: Icd3ac0fd6c901228554115c6350d88bb49874587 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-15mainboard: Drop optional and empty ACPI \_BFS methodsAngel Pons
The ACPI specification, version 2.0 says: _BFS is an optional control method. So, remove them. They have been copy-pasted around quite a bit, and do not do anything useful. Plus, it's deprecated in later ACPI versions. Change-Id: I9ef21f231dd6051d410ac3a0fe554908409c2fa7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43443 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-10AMD mainboards: Drop commented-out includeAngel Pons
This code is not even being build-tested. Drop it before it grows moss. Change-Id: I6f71419ea23b973b0bedb426e20cb3dc460ef68d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43271 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-09ACPI: Drop commented-out DSDT DefinitionBlock instancesAngel Pons
This code is not even being build-tested. Drop it before it grows moss. Change-Id: I9b5589d4596eead83a5897b083ccb85ef05a03d5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43270 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05mb/google/kahlee: Drop macro H1_PCH_INTFurquan Shaikh
This change drops H1_PCH_INT macro for GPIO_9 since it is the same across all variants. Also, the name differed from the schematics version `H1_PCH_INT_ODL` creating confusion. Change-Id: I7b038426a984d8abc460a0da3ee1dc5559d7ad5f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-06-30mb/google/kahlee: Do not enable SCI for H1_PCH_INT_ODLFurquan Shaikh
H1 is not a wake source and hence there is no need to configure SCI GEVENT for it. This change drops PAD_SCI() configuration for GPIO_9 i.e. H1_PCH_INT_ODL. BUG=b:159944426 Change-Id: Iec2285b76f9c5fa1b4b1be15128fea316fa04555 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42874 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-30ACPI: Drop typedef global_nvs_tKyösti Mälkki
Bring all GNVS related initialisation function to global scope to force identical signatures. Followup work is likely to remove some as duplicates. Change-Id: Id4299c41d79c228f3d35bc7cb9bf427ce1e82ba1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42489 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-28soc/amd/common: Access ACPIMMIO via proper symbolsKyösti Mälkki
Using proper symbols for base addresses, it is possible to only define the symbols for base addresses implemented for the specific platform and executing stage. Change-Id: Ib8599ee93bfb1c2d6d9b4accfca1ebbefe758e09 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-24ACPI: Replace uses of CBMEM_ID_ACPI_GNVSKyösti Mälkki
These are the simple cbmem_find() cases. Also drop the redundant error messages. Change-Id: I78e5445eb09c322ff94fe4f65345eb2997bd10ef Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-06-19soc/amd: move acpi_wake_source.asl to common directoryFelix Held
Files are both identical and common for both SoCs. Change-Id: I54b78108d342a0fd03bf70ffe6a09695c5678eb4 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42545 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-19Kconfig: Escape variable to accommodate new Kconfig versionsPatrick Georgi
Kconfig 4.17 started using the $(..) syntax for environment variable expansion while we want to keep expansion to the build system. Older Kconfig versions (like ours) simply drop the escapes, not changing the behavior. While we could let Kconfig expand some of the variables, that only splits the handling in two places, making debugging harder and potentially messing with reproducible builds (e.g. when paths end up in configs), so escape them all. Change-Id: Ibc4087fdd76089352bd8dd0edb1351ec79ea4faa Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-06-02src: Remove unused '#include <cpu/x86/lapic.h>'Elyes HAOUAS
Also, replace 'lapic.h' by 'lapic_def.h' in 'soc/intel/braswell/northcluster.c'. Change-Id: I71cff43d53660dc1e5a760ac3034bcf75f93c6e7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41489 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18mainboard/*/*/Kconfig*: Remove leading blank lines from SPDX headerElyes HAOUAS
Change-Id: I7089b29e881d74d31477e2df1c5fa043fe353343 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41358 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18src: Remove leading blank lines from SPDX headerElyes HAOUAS
Change-Id: I8a207e30a73d10fe67c0474ff11324ae99e2cec6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41360 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-10mb/google/kahlee: Hold WLAN PCIe reset low at boot for mordinKevin Chiu
gpio70 is assigned to use as WLAN rst in new schematic to fulfill RTK RTL8822CE power sequence: WLAN rst will need to be active at least 50ms after WLAN power on. Also in order to keep the rst low in consistency, override default gpio70 to low. BUG=b:154357210,b:154848243 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I98c8afe42b7f92016f83483acbb3b9ae64b159f7 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40805 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-10mb/google/kahlee: Don't reset the touchpad/screen on bootMartin Roth
touchpad & touchscreen power enable gets reset during resume causing unintended wake interrupts, causing dark resume failures. This prevents the board from being shut down after it's been suspended for a long period of time and can end up draining the battery. BUG=b:153173717 TEST=Build only - Needs to be tested by ODMs. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: If403da8853e59eaaf589062c9bd6f10deb626998 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
2020-05-10src/mainboard: Replace GPLv2 long form headers with SPDX headerElyes HAOUAS
Change-Id: I64d9468682a4aae3084b17b8724d035f17d01dff Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-05-09src/: Replace GPL boilerplate with SPDX headersPatrick Georgi
Used commands: perl -i -p0e 's|\/\*[\s*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-only */|' $(cat filelist) perl -i -p0e 's|\/\*[\s*]*.*is[\s*]*free[\s*]*software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*either[\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License,[\s*]*or[\s*]*.at[\s*]*your[\s*]*option.[\s*]*any[\s*]*later[\s*]*version.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-or-later */|' $(cat filelist) perl -i -p0e 's|\/\*[\s*]*.*is[\s*#]*free[\s*#]*software[;:,][\s*#]*you[\s*#]*can[\s*#]*redistribute[\s*#]*it[\s*#]*and/or[\s*#]*modify[\s*#]*it[\s*#]*under[\s*#]*the[\s*#]*terms[\s*#]*of[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*as[\s*#]*published[\s*#]*by[\s*#]*the[\s*#]*Free[\s*#]*Software[\s*#]*Foundation[;:,][\s*#]*either[\s*#]*version[\s*#]*3[\s*#]*of[\s*#]*the[\s*#]*License[;:,][\s*#]*or[\s*#]*.at[\s*#]*your[\s*#]*option.[\s*#]*any[\s*#]*later[\s*#]*version.[\s*#]*This[\s*#]*program[\s*#]*is[\s*#]*distributed[\s*#]*in[\s*#]*the[\s*#]*hope[\s*#]*that[\s*#]*it[\s*#]*will[\s*#]*be[\s*#]*useful[;:,][\s*#]*but[\s*#]*WITHOUT[\s*#]*ANY[\s*#]*WARRANTY[;:,][\s*#]*without[\s*#]*even[\s*#]*the[\s*#]*implied[\s*#]*warranty[\s*#]*of[\s*#]*MERCHANTABILITY[\s*#]*or[\s*#]*FITNESS[\s*#]*FOR[\s*#]*A[\s*#]*PARTICULAR[\s*#]*PURPOSE.[\s*#]*See[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*for[\s*#]*more[\s*#]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-3.0-or-later */|' $(cat filelist) perl -i -p0e 's|(\#\#*)[\w]*.*is free software[:;][\#\s]*you[\#\s]*can[\#\s]*redistribute[\#\s]*it[\#\s]*and\/or[\#\s]*modify[\#\s]*it[\s\#]*under[\s \#]*the[\s\#]*terms[\s\#]*of[\s\#]*the[\s\#]*GNU[\s\#]*General[\s\#]*Public[\s\#]*License[\s\#]*as[\s\#]*published[\s\#]*by[\s\#]*the[\s\#]*Free[\s\#]*Software[\s\#]*Foundation[;,][\s\#]*version[\s\#]*2[\s\#]*of[\s\#]*the[\s\#]*License.*[\s\#]*This[\s\#]*program[\s\#]*is[\s\#]*distributed[\s\#]*in[\s\#]*the[\s\#]*hope[\s\#]*that[\s\#]*it[\s\#]*will[\#\s]*be[\#\s]*useful,[\#\s]*but[\#\s]*WITHOUT[\#\s]*ANY[\#\s]*WARRANTY;[\#\s]*without[\#\s]*even[\#\s]*the[\#\s]*implied[\#\s]*warranty[\#\s]*of[\#\s]*MERCHANTABILITY[\#\s]*or[\#\s]*FITNESS[\#\s]*FOR[\#\s]*A[\#\s]*PARTICULAR[\#\s]*PURPOSE.[\#\s]*See[\#\s]*the[\#\s]*GNU[\#\s]*General[\#\s]*Public[\#\s]*License[\#\s]*for[\#\s]*more[\#\s]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist) perl -i -p0e 's|(\#\#*)[\w*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist) Change-Id: Ia01908544f4b92a2e06ea621eca548e582728280 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41178 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-06treewide: Move "is part of the coreboot project" line in its own commentPatrick Georgi
That makes it easier to identify "license only" headers (because they are now license only) Script line used for that: perl -i -p0e 's|/\*.*\n.*This file is part of the coreboot project.*\n.*\*|/* This file is part of the coreboot project. */\n/*|' # ...filelist... Change-Id: I2280b19972e37c36d8c67a67e0320296567fa4f6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-10 18:56:16 +0000