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Build of the entire smm-class is skipped if we have
HAVE_SMI_HANDLER=n.
Change-Id: I10b4300ddd18b1673c404b45fd9642488ab3186c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34125
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The clock was previously set to 52MHz to workaround the fact that
depthcharge didn't support tuning.
Tuning has now been enabled in depthcharge:
https://chromium-review.googlesource.com/c/chromiumos/platform/depthcharge/+/1655553
BUG=b:122244718
TEST=Verified on grunt that it speeds up boot by 130ms
Change-Id: If847cea2a7848bcd175958db86e652d4f710201a
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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It was determined through testing that 16MB of reserved VRAM is
sufficient. Additional RAM for the graphics driver is allocated out
of system memory.
BUG=b:123579702
TEST=Boot Grunt, watch VRAM usage with graphics driver logging.
Change-Id: I44b640f015b45c0dc3d701929549f3a1082a9268
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33368
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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AMD devices traditionally have the LPC-ISA bus at 14.3 and the
definition has been very consistent. Relocate the feature from
stoneyridge into common/block.
BUG=b:131682806
Change-Id: I8d7175b8642bb17533bb2287b3e3ee3d52e85a75
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32653
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The banked GPIO functionality in the AcpiMmio block has been consistent
since the Mullins product. Move the basic support into a common
directory.
Each product's pin availability, MUXes, and other details must remain
specific to the product.
The relocated source also drops the weak configure_gevent_smi() that
reports SMI is not available. The stoneyridge port relies on SMI
to do its initialization, similar to modern soc/intel devices. This
is the plan for future soc/amd ports, so make a missing function a
build error instead of a runtime warning.
BUG=b:131682806
Change-Id: I9cda00210a74de2bd1308ad43e2b867d24a67845
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Move the stoneyridge AcpiMmio code into soc/amd/common.
The SB800 southbridge introduced the MMIO hardware blocks at 0xfed80000
commonly known as AcpiMmio. Implementations beginning with Mullins
enable decode in PMx04. Older designs use PMx24 and allow for
configuring the base address. Future work may support the older version.
Comparing the documentation for AMD's RRGs and BKDGs, it is evident that
the block locations have not been reassigned across products. In some
cases, address locations are deprecated and new ones consumed, e.g. the
early GPIO blocks were simpler at offset 0x100 and the newer GPIO banks
are now at 0x1500, 0x1600, and 0x1700.
Note: Do not infer the definitions within the hardware blocks are
consistent across family/model products.
BUG=b:131682806
Change-Id: I083b6339cd29e72289e63c9331a815c46d71600d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32649
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The gpio table is only used by depthcharge, and depthcharge rarely
has a need for the "recovery" gpio. On a few boards it does use the
gpio as a signal for confirming physical presence, so on that boards
we'll advertise the board as "presence".
All these strings probably should have been #defines to help avoid
typos (e.g., the "ec_in_rw" in stout seems questionable since everybody
else uses "EC in RW").
Cq-Depend: chromium:1580454
BUG=b:129471321
BRANCH=None
TEST=Local compile and flash (with corresponding changes to depthcharge)
to 2 systems, one with a "presence" gpio and another without. Confirmed
that both systems could enter dev mode.
Change-Id: Id6d62d9e48d3e6646cbc1277ea53f0ca95dd849e
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Correct Micron MT40A512M16TB-062E:J SPD CRC to 0x5330 to fix post hang
in AGESA TestPoint:05 TpProcMemSPDChecking.
BUG=b:127394249
BRANCH=master
TEST=emerge-grunt coreboot chromeos-bootimage
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Change-Id: I8fa49e6e938b3195945b3199438cc53f3e9c92e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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A subsequent patch will move the AcpiMmio support into amd/common.
Take this opportunity to rename the blocks in the 0xfed8xxxx region
with more consistency.
Change-Id: I9a69a6ecfc10f78b4860df05a77a061d2fc8be7d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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This option has been relocated to depthcharge:
https://crrev.com/c/1524806
BUG=b:124141368, b:124192753
TEST=Build and deploy to eve
TEST=util/lint/checkpatch.pl -g origin/master..HEAD
TEST=util/abuild/abuild -B -e -y -c 50 -p none -x
TEST=make clean && make test-abuild
CQ-DEPEND=CL:1524806
BRANCH=none
Change-Id: Ib4a83af2ba143577a064fc0d72c9bc318db56adc
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31909
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Depthcharge is changing how the RW_LEGACY CBFS is handled for alternate
bootloaders, see https://crrev.com/c/1528550 and
https://crrev.com/c/1530303. This means that RW_LEGACY must be marked as
CBFS in the fmap in order to work. All boards except for kahlee(grunt)
have CBFS marked.
BUG=b:128703316
TEST=Build and ran on grunt along with chromium patches on grunt and was
able to list alternate bootloader with ctrl+l
BRANCH=none
Change-Id: I843d565a9503d27e666a34e59aba263ec490c81f
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32019
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Disable the use of AMD's Secure OS through the Kconfig option.
BUG=chromium:903833
TEST=Build google/aleena, verify types 02, 0c, 0d are removed
from PSP directory table
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Iabb0632eef88170dde45dea2e2e15b54b3a06f7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
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We were used to set the same values in the system and board tables.
We'll keep the mainboard values as defaults for the system tables,
so nothing changes unless somebody overrides the system table hooks.
Change-Id: I3c9c95a1307529c3137647a161a698a4c3daa0ae
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Enable ACPI TBMC notification on tablet mode change to support
convertible Aleena devices.
BUG=b:124132058
BRANCH=grunt
TEST=evtest shows tablet mode events
Change-Id: Iaf8ef031d4660f0791b5f664880437e6dfa58dc8
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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variants
BUG=b:127394249
BRANCH=master
TEST=emerge-grunt coreboot chromeos-bootimage
Change-Id: Ibb4beddf186233fd82ec8f3a01bf14d00b1352ff
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31778
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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For Chrome OS (or vboot), The PRESERVE flags should be applied on
following sections:
RO_PRESERVE, RO_VPD, RW_PRESERVE, RW_ELOG, RW_NVRAM, RW_SMMSTORE,
RW_VPD, RO_FSG (b:116326638), SI_GBE (chromium:936768),
SI_PDR (chromium:936768)
With the new PRESERVE flag, we don't need RO_PRESERVE and RW_PRESERVE in
the future. But it's still no harm to use it if there are multiple
sections all needing to be preserved.
BUG=chromium:936768
TEST=Builds google/eve and google/kukui inside Chrome OS source tree.
Also boots successfully on eve and kukui devices.
Change-Id: I6664ae3d955001ed14374e2788d400ba5fb9b7f8
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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MMIO operations are arch-agnostic so the include
path should not be arch/.
Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31691
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I91158452680586ac676ea11c8589062880a31f91
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31692
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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PCI config accessors are no longer indirectly included
from <arch/io.h> use <device/pci_ops.h> instead.
Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This change enables mode change as a wake source for S3.
BUG=b:124132058
Change-Id: I95b1eac800858ab17cdf69bdd3f2c5828516c184
Signed-off-by: Mengqi Guo <mqg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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BUG=b:121354442
TEST=None
Change-Id: I348c7106772eecd513baf9abe60ef19008d0ba4d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/31424
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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We leave it to linker garbage collection to drop
unreferenced code and symbols from final object files.
Function declarations and definitions are to be guarded
with preprocessor directives only as a last resort.
Change-Id: Ie8748ccddc8e31569c58deba5d08c98a04326fa8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Use AGPIO 10 as the EC sync interrupt for MKBP events for sensor data.
On this platform, interrupts are routed via the GPIO controller so need to be
registered using GpioInt instead of Interrupt.
BUG=b:123750725
BRANCH=grunt
TEST=MKBP events still received (with matching EC and kernel changes)
Change-Id: If499d24511bbaa7054207b7e0b98445723332c4f
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Enrico Granata <egranata@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add support Synaptics touch pad for Aleena/Kasumi.
BUG=b:122549449
BRANCH=master
TEST= Check if synaptics touch pad working in ChromeOS.
Change-Id: Icab1b312f1943b27037ef458044ce9e7172919ee
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/31064
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit 3278f859c3dd97a6d6d885a91dfd33d44e95d58b.
Reason for revert:
It turns out all we want to set in RAM stage is GPIO's DEBOUNCE config,
not its SCI configuration.
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
BUG=b:113880780
BRANCH=none
TEST=Boot grunt, does not go to recovery screen
Change-Id: I500934f3e03e66c97873accd4a979a23d4509675
Reviewed-on: https://review.coreboot.org/c/30997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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The general rule is to configure GPIOs used by coreboot in bootblock
(using the reset table), and GPIOs used by OS in RAM stage.
However, GPIO_9 will be used as both, and we need to reconfigure it to
properly set up debounce, however, it is no longer possible to change
bootblock, so we also configure it in RAM stage to make the new
debounce configuration take affect.
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
BUG=b:113880780
BRANCH=none
TEST=Reboot stress test grunt (>100 times); no messages in dmesg like:
tpm tpm0: Timeout waiting for TPM ready
Change-Id: I0f1bca176ed3f9cebf6b9e9e1008905e492a2f03
Reviewed-on: https://review.coreboot.org/c/30922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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define wakeup-delay-ms to 20ms. This avoids the pop
noise heard at the start of capture.
BUG=b:119926436
TEST=with kernel patch
https://lore.kernel.org/patchwork/patch/1029806/
no pop sound heard at start of capture
Change-Id: I299a584ef2ba66d1e752515100cbe3919b2108f6
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/c/30726
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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define wakeup-delay-ms to 20ms. This avoids the pop
noise heard at the start of capture.
BUG=b:119926436
TEST=with kernel patch
https://lore.kernel.org/patchwork/patch/1029806/
no pop sound heard at start of capture
Change-Id: I2593afa69cfb955f6a2b695406855e0f31f28468
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/c/30725
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Does not fix 3rdparty/, *.S or *.ld or yet.
Change-Id: I66b48013dd89540b35ab219d2b64bc13f5f19cda
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/17656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: I2e28b9f4ecaf258bff8a062b5a54cb3d8e2bb9b0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: Icf34b39d80f6e46d32a39b68f38fb2752c0bcebc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/26484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Use 2T memory timings on Liara for all board IDs.
BUG=b:116082728
TEST=Build & boot on Liara
Change-Id: I5814e63db35cf7761f4f20792b0f3cf4120a1b60
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/30285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@google.com>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
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Commit d80884ea5a ("mb/google/kahlee: Disable IOMMU") disabled the IOMMU
in all kahlee variants, but omitted the explaining comment only in
liara's devicetree.cb. Copy this comment to liara.
Change-Id: I564013a16217445003467e2a0579abd50597b205
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/30166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Using ${...} in some places is slightly confusing.
Fixes: 395cbb4f97 ("mb/*/*/Kconfig: Use CONFIG_VARIANT_DIR for devicetree")
Change-Id: Id0856a10d92786a41d45ca697945699f6f4c1f4c
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/30163
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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file Module Part Number
Correct Ram_ID=0b0000 SPD Module Part Number mismatch last alphabet 'C'
to "H5AN8G6NAFR-UHC".
BUG=b:120000816
BRANCH=master
TEST=mosys memory spd print all
Change-Id: I4f4b83589ad6b53c0a24f2637f0fe8b92a1168e3
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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file Module Part Number
Correct to add Ram_ID=0b0001 SPD Module Part Number mismatch last alphabet 'C'
to "H5ANAG6NAMR-UHC".
BUG=b:120000816
BRANCH=master
TEST=mosys memory spd print all
Change-Id: I4d320b2e10c4865456a9a9ccb400db5dd9256b3e
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30177
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Part Number
Correct Ram_ID=0b0011 SPD Module Part Number to "MT40A1G16KNR-075:E" from
"4ATS1G64HZ-2G6E1".
BUG=b:120000816
BRANCH=master
TEST=mosys memory spd print all
Change-Id: I9d582b3753de9a48865eb6eca7e4fbdb31b799ff
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Number
Correct Ram_ID=0b0000 SPD Module Part Number to "H5AN8G6NAFR-UH" from
"HMA851S6AFR6N-UH".
BUG=b:120000816
BRANCH=master
TEST=mosys memory spd print all
Change-Id: I1f6e885638589a35334a9a8f905af4877c5d1f91
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Part Number
Correct Ram_ID=0b0010 SPD Module Part Number to "MT40A512M16JY-083E:B"
from "4ATF51264HZ-2G3B2".
BUG=b:120000816
BRANCH=master
TEST=mosys memory spd print all
Change-Id: I6847a55968260cdbc1588ddeb8d23c515ad87920
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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A new liara specific VBIOS updating eDP power sequence is available now,
Change Kconfig to use it if board is google liara.
BUG=b:120534087
TEST=Build liara, booted, tested eDP test compliance.
Change-Id: I444cfa0bd755480e006f11c0d692b25b96129c29
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/30090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Move the backlight initialization from bootblock to romstage
BUG=b:120436919
TEST=Careena backlight is enabled
Change-Id: Ia4993b993d37afaf9e23d6f3316ba91053732f1d
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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According to aleena thermal testing to set STAPM values.
skin scalar for 80%.
time constant for 2500s.
power limit for 7.8w.
BUG=b:72979852
TEST=test build for thermal check.
Change-Id: I09f1c1052dd317969546ac7d2bbde14cc563c160
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/29795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Correct Ram_ID=0b0001 SPD Module Part Number to "H5ANAG6NAMR-UH" from "HMAA51S6AMR6N-UH".
BUG=b:120000816
BRANCH=master
TEST=mosys memory spd print all
Change-Id: I59d920498ff6b73e9e7b2887771ad6bc6c6c0b66
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/29873
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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The aleena board uses a display that's not compatible with current VBIOS.
A VBIOS specific for aleena has been merged into blobs, so modify Kconfig
so that it loads the new VBIOS when building aleena, but load original VBIOS
for all other boards under kahlee folder.
BUG=b:112618193
TEST=Build each board under kahlee, one at a time. After each build, opened
build/config.h and searched VGA_BIOS_FILE to verify that the string only
changed for aleena, all other boards remained with original string.
Change-Id: Iccd0853692680908d951edd142a2d8e13a561391
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/29870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change the board id detection to support rev5, since the 2T mode still
needed in DVT build.
BUG=b:116082728
TEST=verify by ODM.
Change-Id: Ibb4cc1fd2bb54984cb7a8856ed7b9f49b78eddce
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/29779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Field 'OEMID' & "OEM Table ID" are related to DSDT table
not to mainboard.
So use macro to set them respectvely to "COREv4" and
"COREBOOT".
Change-Id: I060e07a730e721df4a86128ee89bfe168c69f31e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: David Guckian
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We need to default this to low so the speakers don't activate in S3.
BUG=b:118248953
TEST=Used a scope to look at the line and made sure depthcharge still
beeps.
Change-Id: I70d2f4a3261d212b62e784fa7414e45b1d575612
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/29783
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change adds ACPI properties for WDT8752A device.
BUG=b:117174180
BRANCH=master
TEST=Verify touchscreen on delan works with this change
Change-Id: Id1484a482de6282c97f3aac329f217bbcb7dbd18
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
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Correct SPD Module Part Number to "K4A8G165WC-BCTD" from "M471A5244CB0-CTD".
BUG=b:119400832
BRANCH=master
TEST=emerge-grunt coreboot chromeos-bootimage
mosys memory spd print all
0 | DDR4 | SO-DIMM
0 | 1-78: Samsung | 00000000 | K4A8G165WC-BCTD
0 | 4096 | 1 | 64
0 | DDR4-1333, DDR4-1600, DDR4-2400
Change-Id: I29505d3eece2283579499a0afc424c4a28017fa5
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/29557
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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