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path: root/src/mainboard/google/kukui
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2021-05-20mb/google/kukui: Add rt1015 support for katsuSunway
Modify the value of "SPEAKER_GPIO_NAME" in katsu as rt1015p sdb BUG=None BRANCH=kukui TEST=Speaker can work normally in katsu during firmware stage Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com> Change-Id: Ib3672383ab34bb07b4e5eb7f7e8b4549e13c67b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54642 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-11mb/google/kukui: Add discrete EMCP LPDDR4X table for Kakadu/KatsuSunway
Add EMCP LPDDR4X DDR FEPRF6432-58A1930 for ram id 9. BUG=b:186141919 BRANCH=kukui TEST=New Emcp can boot normally on kakadu/katsu Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com> Change-Id: Ieaf05a0a7b0c0671c07b0df29319ebd91fe63e57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54009 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06mb/google/kukui: Add flag for MIPI_DSI_MODE_LINE_END ANX7625Jitao Shi
Config ANX7625 line data end same time on all line. BUG=b:173603645 BRANCH=kukui TEST=Display is normal on Kukui Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Change-Id: Ia1dc217138a98a79ef2f31225b52ba2b1aaf8672 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-04-06mb/google/kukui: fix the issue of getting error panel_idxuxinxiong
Current get panel_id is over sku_id() >> 4, but sku_id is combined with wfc_id/lcm_id/sku_id, so the panel_id value is wfc_id << 4 | lcm_id() in fact. When wfc_id is not 0, the panel_id will be wrong. So only get the low 4 bits for the panel_id. BUG=b:183779755 BRANCH=kukui TEST=emerge-kukui Change-Id: I63e0c8a2719462a9b979afe52a27c78b9fc804e8 Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-06mb/google/kukui: katsu: update the EDID and initial codeSunway
The EDID and initial code are provided by STA (the vendor). BUG=b:183969078 TEST=Boots on Chromebook Katsu and displayed developer firmware screen successfully. Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com> Change-Id: I54e72c072b47d2be264ed7f0700812a6c704a104 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51918 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-31mb/google/kukui/var/cozmo: Add RAM ID tableLucas Chen
Add the RAM ID table offset 0x30 for cozmo. BUG=b:182776048 BRANCH=kukui TEST=emerge-jacuzzi coreboot Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Change-Id: Ia29d38f61975c5e29a901adbfad343153628405f Reviewed-on: https://review.coreboot.org/c/coreboot/+/51845 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28mb/google/kukui: fine tune the data lane trailJitao Shi
ANX7625 requires customized hs_da_trail time. So override the data trail for ANX7625. BUG=b:173603645 BRANCH=kukui TEST=Display is normal on Jacuzzi Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Change-Id: I620035363507daaa19e3c272a44059c17be29af1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Chen-Tsung Hsieh <chentsung@chromium.org>
2021-03-23mb/google/kukui: Add a new config 'Makomo'Sunway
A new board introduced to Kukui family. BUG=None TEST=make # select Makomo BRANCH=kukui Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com> Change-Id: I42b84e2c0926e755ba210fc8baac19f8ed2c4e57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51565 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-17mb/google/kukui: Add new config 'cozmo'Lucas Chen
New board 'cozmo'. BUG=b:181144502 TEST=None BRANCH=kukui Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Change-Id: Ia0ec1d89444d2634bfcfb3475a422f4e4ae92b7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/51437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chen-Tsung Hsieh <chentsung@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-03-08mb/google/kukui: Add Micron 4GB discrete LPDDR4X DDR supportJessy Jiang
Support 4G+128G MT29VZZZAD9GQFSM-046 W.9S9 discrete DDR bootup. BUG=b:162292216 BRANCH=kukui TEST=Boots correctly on Kukui. Signed-off-by: Jessy Jiang <jiangchao5@huaqin.corp-partner.google.com> Change-Id: I5657a007154bc52c6f0f27e1de6e3294a5e74ad7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-02-21mb/: Drop the provided name in chip_opsKyösti Mälkki
Little point to replicate a string already provided both as a global Kconfig and global mainboard_part_number. Change-Id: I1fd138c711ebbb37c39b2c8f554b1f2e1a364424 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com>
2021-02-16mb/google: Remove unused <string.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|strstr\|strtok_r\|strtok\|atol\|strrchr\|skip_atoi\|snprintf' -- src/)|grep '<' Change-Id: I3ba39077014c50c2dfb9fddf78813f1058c45cc1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-06mb/google/kukui: Add byte mode/single rank DRAM support for burnet/escheKevin Chiu
ID#5: Hynix - H9HCNNNFAMMLXR-NEE (Byte mode) ID#7: MICRON - MT53E1G32D2NP-046 WT:A (Single rank) BUG=b:165768895 BRANCH=kukui TEST=1. emerge-jacuzzi coreboot 2. power on test ok Change-Id: Iaa735c23889860218f6f6571cf0bc0b21b304b51 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-02-04mb/google/kukui: kakadu: update the initial code for BOE LCDSunway
The latest initial code is from BOE, the vendor. BUG=b:179206650 BRANCH=kukui TEST=Run long time aging test and the BOE LCD shows normally. Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com> Change-Id: Ibc1bd5147dbda4e3b94023e7ba52ff6a18abba0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/50215 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-25mb/google/kukui: Add panel for Katsuchenzanxi
Declare the following panel for Katsu: - BOE_TV105WUM_NW0 - STA_2081101QFH032011_53G BUG=b:176523929 TEST=build Katsu image passed BRANCH=kukui Change-Id: I59a02198bc0e13f2760677ae4ea3eb05eb883464 Signed-off-by: chenzanxi <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-22mb/google/kukui: Enable MT8183_DRAM_EMCP for katsuSunway
The katsu project will be using eMCP board design. BUG=b:176271935 TEST=Boots on chromebook katsu successfully. BRANCH=kukui Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com> Change-Id: I733a9a79e2ea6501e26bf79bfce2b1934a295342 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48893 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-19mb/google/kukui: Add discrete EMCP LPDDR4X table for Kakadu/Katsuxuxinxiong
Add EMCP LPDDR4X DDR MT29VZZZCD9GQKPR for ram id 8. BUG=b:176262460 BRANCH=master TEST=emerge-jacuzzi coreboot Change-Id: If00478b9b05ab3ec48b6a8dec37e9f2f9f04e188 Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49447 Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-15mb/google/kukui: Add new ddr architecture support for kukuiShaoming Chen
Two configuration files are added: 1. H9HCNNNFAMMLXR-NEE-8GB: new byte mode 2. MT53E1G32D2NP-046-4GB: new single rank mode Also initialize the rank number field 'rank_num' for all configs. BUG=b:165768895 BRANCH=kukui TEST=DDR boot up correctly on Kukui Signed-off-by: Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com> Change-Id: I1786c1e251e8d6e110cbdce79feeb386db220404 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49108 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-01mb/google/kukui: Add panel api after dsi startJitao Shi
Some bridge chip or panel requires dsi signal output before dsi receiver works. BUG=b:168728787 BRANCH=kukui TEST=Display is normal on Kukui Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Change-Id: I3bded27087490f32ee233e615cfad1fd05fb582d Reviewed-on: https://review.coreboot.org/c/coreboot/+/47380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-24mb/google/kukui: Add a new config 'Katsu'Sunway
A new board introduced to Kukui family. BUG=b:176206134 TEST=make # select Katsu BRANCH=kukui Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com> Change-Id: I09fe2b8f6922dfd2af6424830568466fb98f7aee Reviewed-on: https://review.coreboot.org/c/coreboot/+/48874 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-17drivers: Replace set_vbe_mode_info_validPatrick Rudolph
Currently it's not possible to add multiple graphics driver into one coreboot image. This patch series will fix this issue by providing a single API that multiple graphics driver can use. This is required for platforms that have two graphic cards, but different graphic drivers, like Intel+Aspeed on server platforms or Intel+Nvidia on consumer notebooks. The goal is to remove duplicated fill_fb_framebuffer(), the advertisment of multiple indepent framebuffers in coreboot tables, and better runtime/build time graphic configuration options. Replace set_vbe_mode_info_valid with fb_add_framebuffer_info or fb_new_framebuffer_info_from_edid. Change-Id: I95d1d62385a201c68c6c2527c023ad2292a235c5 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-12-15mb/google/kukui: help payload to identify correct speaker amp typeHung-Te Lin
Kukui based devices may use different speaker amplifiers, for example MAX98357A, RT1015, or RT1015Q/automode. To help payloads identifying which component was installed on board, we want to pass the speaker GPIO in different name. This can be set in Kconfig as CONFIG_SPEAKER_GPIO_NAME. BUG=b:174534548 TEST=emerge-kukui coreboot depthcharge chromeos-bootimage BRANCH=kukui Signed-off-by: Hung-Te Lin <hungte@chromium.org> Change-Id: I4b44b026bee4d3b58646eee207aea0120071dd46 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-10lib/edid_fill_fb: Support multiple framebuffersPatrick Rudolph
Currently it's not possible to add multiple graphics driver into one coreboot image. This patch series will fix this issue by providing a single API that multiple graphics driver can use. This is required for platforms that have two graphic cards, but different graphic drivers, like Intel and Aspeed on server platforms or Intel and Nvidia on consumer notebooks. The goals are to remove duplicated fill_fb_framebuffer(), to advertise multiple independent framebuffers in coreboot tables, and better runtime/build time graphic configuration options. Add an implementation in edid_fill_fb that supports registering multiple framebuffers, each with its own configuration. As the current code is only compiled for a single graphics driver there's no change in functionality. Change-Id: I7264c2ea2f72f36adfd26f26b00e3ce172133621 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-12-02cbfs: Simplify load/map API names, remove type argumentsJulius Werner
This patch renames cbfs_boot_map_with_leak() and cbfs_boot_load_file() to cbfs_map() and cbfs_load() respectively. This is supposed to be the start of a new, better organized CBFS API where the most common operations have the most simple and straight-forward names. Less commonly used variants of these operations (e.g. cbfs_ro_load() or cbfs_region_load()) can be introduced later. It seems unnecessary to keep carrying around "boot" in the names of most CBFS APIs if the vast majority of accesses go to the boot CBFS (instead, more unusual operations should have longer names that describe how they diverge from the common ones). cbfs_map() is paired with a new cbfs_unmap() to allow callers to cleanly reap mappings when desired. A few new cbfs_unmap() calls are added to generic code where it makes sense, but it seems unnecessary to introduce this everywhere in platform or architecture specific code where the boot medium is known to be memory-mapped anyway. In fact, even for non-memory-mapped platforms, sometimes leaking a mapping to the CBFS cache is a much cleaner solution than jumping through hoops to provide some other storage for some long-lived file object, and it shouldn't be outright forbidden when it makes sense. Additionally, remove the type arguments from these function signatures. The goal is to eventually remove type arguments for lookup from the whole CBFS API. Filenames already uniquely identify CBFS files. The type field is just informational, and there should be APIs to allow callers to check it when desired, but it's not clear what we gain from forcing this as a parameter into every single CBFS access when the vast majority of the time it provides no additional value and is just clutter. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ib24325400815a9c3d25f66c61829a24a239bb88e Reviewed-on: https://review.coreboot.org/c/coreboot/+/39304 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20soc/mediatek: Move auxadc driver from MT8183 to commonPo Xu
The auxadc (auxiliary analogue-to-digital conversion) is a unit to identify the plugged peripherals or measure the temperature or voltages. The MT8183 auxadc driver can be shared by multiple MediaTek SoCs so we should move it to the common folder. Signed-off-by: Po Xu <jg_poxu@mediatek.com> Change-Id: Id4553e99c3578fa40e28b19a6e010b52650ba41e Reviewed-on: https://review.coreboot.org/c/coreboot/+/46390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-11-16mb/google/kukui: Fix LCD sequence T3 fail issueTao Xia
The T3 that PPVARN_LCD low to LCM_RST_1V8 high is 0.1269ms and it does not meet the LCD specification that the T3 must be larger than 5ms. Because there is a delay between PPVARN_LCD_EN and PPVARN_LCD. An extra 9ms delay should be added on LCM_RST_1V8 in order to meet the specification "ProductSpec_NV105WUM-A51_ V4.3_P2(TLCM).pdf". BUG=b:172201138 BRANCH=kukui TEST=The LCD sequence T3 is larger than 5ms when power on. Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: Iaf7ae494e30c4c207103d949287b335288688c54 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-11-02mb/google/kukui: Enable MT8183_DRAM_EMCP for kakaduSunway
The Kakadu project will be using eMCP board design. BUG=b:171841122 TEST=Boots on chromebook Kakadu successfully. Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com> Change-Id: I44668ce630758e49fbf2c6028f56c01f83ff08f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46871 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-27mb/google/kukui: change Jacuzzi followers LCMID to fixed valueKevin Chiu
The LCM ID is not really used on Jacuzzi followers and the reference design expects ADC to return 0. However, there were hardware design issues so the returned value became unexpected numbers. - Juniper and Kappa returns 1. - Burnet and Esche returns 1 on normal boot, and 0 on recovery boot. - Cerise and Stern usually returns 0, and sometimes 1. To fix that, we are changing LCM ID to fixed value for Jacuzzi followers. BUG=b:170916885,b:171365301 BRANCH=kukui TEST=1. emerge-jacuzzi coreboot 2. check burnet/esche skuid correctly Change-Id: I3b43b9153315ec65e9168c4e84ea844dff14d446 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-10-19mb/google/kukui: Support SKU from camera EEPROMHung-Te Lin
To support camera second source GC5035 for kodama, add world facing camera id as part of the sku id, which is determined by the data in camera EEPROM. For models other than kodama, the camera id is always 0 and hence the sku id is unchanged. BUG=b:144820097 TEST=emerge-kukui coreboot TEST=Correct WFC id detected for kodama with GC5035 camera BRANCH=kukui Change-Id: I63a2b952b8c35c0ead8200d7c926e8d90a9f3fb8 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45811 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-08soc/mediatek: Add function to raise the CPU frequency of MT8192Weiyi Lu
Rename all mt_pll_raise_ca53_freq() into mt_pll_raise_little_cpu_freq(). Implement mt_pll_raise_little_cpu_freq() in MT8192. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Change-Id: I97d9a61f39f2eb27f0c6f911a9199bf0eaae4fbe Reviewed-on: https://review.coreboot.org/c/coreboot/+/45401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-09-22mb/google: Drop unneeded empty linesElyes HAOUAS
Change-Id: I4151d1a6ce94763432f307fbc8bc4afe229856ea Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-08mb/google/kukui: Add LPDDR4X Samsung K4UBE3D4AA-MGCR 4GB supportKevin Chiu
Support 4GB Samsung K4UBE3D4AA-MGCR discrete DDR bootup. BUG=b:162379736 BRANCH=kukui TEST=emerge-jacuzzi coreboot Change-Id: I2f4f084ece067e9884c23004506b450a281a77a6 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45101 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-02mb/google/kukui: Add LPDDR4X support for fennel/cerise/sternxuxinxiong
Modify the BOARD_SDRAM_TABLE_OFFSET as 0x10 BUG=b:162891673 BRANCH=kukui TEST=make Change-Id: I5a4794d6e899e35686c40a553b991643f9e35ea3 Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jianbo Zhang <zhangjianbo@huaqin.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
2020-08-30mb/google/kukui: Add LPDDR4X Samsung K4UBE3D4AA-MGCR 4GB support for ↵Kevin Chiu
burnet/esche Add LPDDR4x DRAM index#0 Samsung K4UBE3D4AA-MGCR 4GB BUG=b:165956924 BRANCH=kukui TEST=emerge-jacuzzi coreboot Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I644b65d77b79891ed65215d810b970fe43b29e3f Reviewed-on: https://review.coreboot.org/c/coreboot/+/44821 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-24mb/google/kukui: Add LPDDR4X MT53E2G32D4NQ-046 8GB support for burnet/escheKevin Chiu
Add LPDDR4x DRAM index#6 MT53E2G32D4NQ-046 8GB BUG=b:159301679 BRANCH=master TEST=1. emerge-jacuzzi coreboot 2. MT53E2G32D4NQ-046 8GB M/B boot successfully 3. check DRAM size: 8GB Change-Id: I16449591ec576b1c613a5dad511bafac2bb46f04 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-08-12mb/google/kukui: revise per-device memory mapping tableHung-Te Lin
In order to help identifying right DRAM info (especially in user space), we want to unify the mapping table and do the device-specific mapping by a virtual offset based on build config. BUG=b:161768221,b:159301679 BRANCH=kukui TEST=emerge-jacuzzi coreboot Change-Id: If89bf18c48d263deb79df3e7a60c33bec000d8a3 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-08-06mb/google/kukui: Add ddr geometry to support 6GB, 8GB DDR bootupHuayang Duan
Set correct DDR geometry for all existing memory modules. BUG=none BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: I9b53ab2bf43e0dfb7448eb37a18faf686267eaed Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-08-06mb/google/kukui: Add a new config 'Fennel'xiatao5
A new board introduced to Kukui family. BUG=b:162478693 TEST=make # select Fennel BRANCH=kukui Signed-off-by: xiatao5 <xiatao5@huaqin.corp-partner.google.com> Change-Id: I1f742a36793f38c37fbd4e1b4cbddbd542e785ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/44061 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Zhaoyou Hong <hongzhaoyou@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-03mb/google/kukui: Add Micron 8GB discrete LPDDR4X DDR supportHuayang Duan
Support 8GB MT53E2G32D4NQ-046 discrete DDR bootup. BUG=b:159301679 BRANCH=kukui TEST=Boots correctly on Kukui. Change-Id: Ide01f029c5ebd6c3ae6350f73f3c60b818d51353 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-08-03mb/google/kukui: indent config names for burnet and escheHung-Te Lin
The 'burnet' and 'esche' in Kconfig.name should have two spaces after the arrow. BUG=None TEST=make menuconfig BRANCH=kukui Change-Id: If7cc31cf459082a797445fb8223b3d9cbde72901 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43986 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-27mb/google/kukui: Add discrete LPDDR4X DDR table support for burnet/escheKevin Chiu
LPDDR4x DRAM table for burnet/esche: [1] = "sdram-lpddr4x-H9HCNNNCPMALHR-4GB" [2] = "sdram-lpddr4x-MT53E1G32D4NQ-4GB" [3] = "sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB" [4] = "sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB" BUG=b:161768221,b:159301679 BRANCH=master TEST=emerge-jacuzzi coreboot Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: Ida7ab877c3f7e10a67680b69a1d724ec734d2928 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-07-26mb/google/kukui: send SKU ID to EC for device-specific configurationHung-Te Lin
For devices sharing same firmware, there may be few customization based on SKU ID - for example being clamshell or form factor. On Kukui and Jacuzzi platforms the SKU ID is defined on AP SOC, so we have to send the information to EC. BUG=b:161767717 TEST=make -j # builds and boots on Juniper BRANCH=kukui Change-Id: I8ffdd9fd1e609c1dd4b0e22dc7aab560ccdc842e Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43788 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23mb/google/kukui: Add new configs 'esche' and 'burnet'Kevin Chiu
new boards introduced to Kukui family. esche: clamshell burnet: 360 convertible BUG=b:161768221 BRANCH=master TEST=emerge-jacuzzi coreboot Change-Id: I2245c34533549bb94c58938fee5778b8a03e2767 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-07-22mb/google/kukui: revise config structure for Jacuzzi followersHung-Te Lin
There are more Jacuzzi followers coming and we want to have a simplified way of adding new boards. Now, detachable and tablets should select BOARD_GOOGLE_KUKUI_COMMON and clamshells should select BOARD_GOOGLE_JACUZZI_COMMON. BUG=None TEST=make menuconfig; make -j # for kukui, krane, jacuzzi, juniper BRANCH=kukui Change-Id: Ifc1eb6a3792f46c5db6b5346902f1114955b28ae Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-07-16mb/google/kukui: Add new config 'willow'Sheng-Liang Pan
New board introduced to Kukui family. BUG=b:159194582 TEST=None BRANCH=kukui Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Icc6bcbd006008a05303693e481a54636f0645887 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43318 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-14mb/google/kukui: Add new configs 'Cerise' and 'Stern'xuxinxiong
New boards introduced to Kukui family. BUG=b:160854400 TEST=make # select Cerise and Stern BRANCH=kukui Change-Id: I5841d57c0891d5191dd96097b90da889855b56c8 Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43320 Reviewed-by: Zhaoyou Hong <hongzhaoyou@huaqin.corp-partner.google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Chen-Tsung Hsieh <chentsung@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22mb/google/kukui: Add Hynix 4GB discrete LPDDR4X DDR supportHuayang Duan
Support 4GB H9HCNNNCPMMLXR-NEE discrete DDR bootup. BUG=b:156691665 BRANCH=none TEST=Boots correctly and stress test passes on Kukui. test cmd: memtester 1000M Change-Id: I0b29cc1cf0d51eb9d6af112858563193ffa88652 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42502 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-13treewide: Add Kconfig variable MEMLAYOUT_LD_FILEFurquan Shaikh
This change defines a Kconfig variable MEMLAYOUT_LD_FILE which allows SoC/mainboard to provide a linker file for the platform. x86 already provides a default memlayout.ld under src/arch/x86. With this new Kconfig variable, it is possible for the SoC/mainboard code for x86 to provide a custom linker file as well. Makefile.inc is updated for all architectures to use this new Kconfig variable instead of assuming memlayout.ld files under a certain path. All non-x86 boards used memlayout.ld under mainboard directory. However, a lot of these boards were simply including the memlayout from SoC. So, this change also updates these mainboards and SoCs to define the Kconfig as required. BUG=b:155322763 TEST=Verified that abuild with --timeless option results in the same coreboot.rom image for all boards. Change-Id: I6a7f96643ed0519c93967ea2c3bcd881a5d6a4d6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42292 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18src: Remove unused 'include <string.h>'Elyes HAOUAS
Unused includes found using following commande: diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|atol\|strrchr\|skip_atoi\|STRINGIFY' -- src/) |grep -v vendorcode |grep '<' Change-Id: Ibaeec213b6019dfa9c45e3424b38af0e094d0c51 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-05-18mainboard/*/*/*.cb: Remove leading blank lines from SPDX headerElyes HAOUAS
Change-Id: Ia0dbf7b946d42bda11b904a9caff5a402b553b33 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-07 12:09:30 +0000