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2020-09-08mb/google/kukui: Add LPDDR4X Samsung K4UBE3D4AA-MGCR 4GB supportKevin Chiu
Support 4GB Samsung K4UBE3D4AA-MGCR discrete DDR bootup. BUG=b:162379736 BRANCH=kukui TEST=emerge-jacuzzi coreboot Change-Id: I2f4f084ece067e9884c23004506b450a281a77a6 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45101 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-02mb/google/kukui: Add LPDDR4X support for fennel/cerise/sternxuxinxiong
Modify the BOARD_SDRAM_TABLE_OFFSET as 0x10 BUG=b:162891673 BRANCH=kukui TEST=make Change-Id: I5a4794d6e899e35686c40a553b991643f9e35ea3 Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jianbo Zhang <zhangjianbo@huaqin.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
2020-08-30mb/google/kukui: Add LPDDR4X Samsung K4UBE3D4AA-MGCR 4GB support for ↵Kevin Chiu
burnet/esche Add LPDDR4x DRAM index#0 Samsung K4UBE3D4AA-MGCR 4GB BUG=b:165956924 BRANCH=kukui TEST=emerge-jacuzzi coreboot Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I644b65d77b79891ed65215d810b970fe43b29e3f Reviewed-on: https://review.coreboot.org/c/coreboot/+/44821 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-24mb/google/kukui: Add LPDDR4X MT53E2G32D4NQ-046 8GB support for burnet/escheKevin Chiu
Add LPDDR4x DRAM index#6 MT53E2G32D4NQ-046 8GB BUG=b:159301679 BRANCH=master TEST=1. emerge-jacuzzi coreboot 2. MT53E2G32D4NQ-046 8GB M/B boot successfully 3. check DRAM size: 8GB Change-Id: I16449591ec576b1c613a5dad511bafac2bb46f04 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-08-12mb/google/kukui: revise per-device memory mapping tableHung-Te Lin
In order to help identifying right DRAM info (especially in user space), we want to unify the mapping table and do the device-specific mapping by a virtual offset based on build config. BUG=b:161768221,b:159301679 BRANCH=kukui TEST=emerge-jacuzzi coreboot Change-Id: If89bf18c48d263deb79df3e7a60c33bec000d8a3 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-08-06mb/google/kukui: Add ddr geometry to support 6GB, 8GB DDR bootupHuayang Duan
Set correct DDR geometry for all existing memory modules. BUG=none BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: I9b53ab2bf43e0dfb7448eb37a18faf686267eaed Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-08-06mb/google/kukui: Add a new config 'Fennel'xiatao5
A new board introduced to Kukui family. BUG=b:162478693 TEST=make # select Fennel BRANCH=kukui Signed-off-by: xiatao5 <xiatao5@huaqin.corp-partner.google.com> Change-Id: I1f742a36793f38c37fbd4e1b4cbddbd542e785ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/44061 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Zhaoyou Hong <hongzhaoyou@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-03mb/google/kukui: Add Micron 8GB discrete LPDDR4X DDR supportHuayang Duan
Support 8GB MT53E2G32D4NQ-046 discrete DDR bootup. BUG=b:159301679 BRANCH=kukui TEST=Boots correctly on Kukui. Change-Id: Ide01f029c5ebd6c3ae6350f73f3c60b818d51353 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-08-03mb/google/kukui: indent config names for burnet and escheHung-Te Lin
The 'burnet' and 'esche' in Kconfig.name should have two spaces after the arrow. BUG=None TEST=make menuconfig BRANCH=kukui Change-Id: If7cc31cf459082a797445fb8223b3d9cbde72901 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43986 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-27mb/google/kukui: Add discrete LPDDR4X DDR table support for burnet/escheKevin Chiu
LPDDR4x DRAM table for burnet/esche: [1] = "sdram-lpddr4x-H9HCNNNCPMALHR-4GB" [2] = "sdram-lpddr4x-MT53E1G32D4NQ-4GB" [3] = "sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB" [4] = "sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB" BUG=b:161768221,b:159301679 BRANCH=master TEST=emerge-jacuzzi coreboot Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: Ida7ab877c3f7e10a67680b69a1d724ec734d2928 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-07-26mb/google/kukui: send SKU ID to EC for device-specific configurationHung-Te Lin
For devices sharing same firmware, there may be few customization based on SKU ID - for example being clamshell or form factor. On Kukui and Jacuzzi platforms the SKU ID is defined on AP SOC, so we have to send the information to EC. BUG=b:161767717 TEST=make -j # builds and boots on Juniper BRANCH=kukui Change-Id: I8ffdd9fd1e609c1dd4b0e22dc7aab560ccdc842e Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43788 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23mb/google/kukui: Add new configs 'esche' and 'burnet'Kevin Chiu
new boards introduced to Kukui family. esche: clamshell burnet: 360 convertible BUG=b:161768221 BRANCH=master TEST=emerge-jacuzzi coreboot Change-Id: I2245c34533549bb94c58938fee5778b8a03e2767 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-07-22mb/google/kukui: revise config structure for Jacuzzi followersHung-Te Lin
There are more Jacuzzi followers coming and we want to have a simplified way of adding new boards. Now, detachable and tablets should select BOARD_GOOGLE_KUKUI_COMMON and clamshells should select BOARD_GOOGLE_JACUZZI_COMMON. BUG=None TEST=make menuconfig; make -j # for kukui, krane, jacuzzi, juniper BRANCH=kukui Change-Id: Ifc1eb6a3792f46c5db6b5346902f1114955b28ae Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-07-16mb/google/kukui: Add new config 'willow'Sheng-Liang Pan
New board introduced to Kukui family. BUG=b:159194582 TEST=None BRANCH=kukui Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Icc6bcbd006008a05303693e481a54636f0645887 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43318 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-14mb/google/kukui: Add new configs 'Cerise' and 'Stern'xuxinxiong
New boards introduced to Kukui family. BUG=b:160854400 TEST=make # select Cerise and Stern BRANCH=kukui Change-Id: I5841d57c0891d5191dd96097b90da889855b56c8 Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43320 Reviewed-by: Zhaoyou Hong <hongzhaoyou@huaqin.corp-partner.google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Chen-Tsung Hsieh <chentsung@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22mb/google/kukui: Add Hynix 4GB discrete LPDDR4X DDR supportHuayang Duan
Support 4GB H9HCNNNCPMMLXR-NEE discrete DDR bootup. BUG=b:156691665 BRANCH=none TEST=Boots correctly and stress test passes on Kukui. test cmd: memtester 1000M Change-Id: I0b29cc1cf0d51eb9d6af112858563193ffa88652 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42502 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-13treewide: Add Kconfig variable MEMLAYOUT_LD_FILEFurquan Shaikh
This change defines a Kconfig variable MEMLAYOUT_LD_FILE which allows SoC/mainboard to provide a linker file for the platform. x86 already provides a default memlayout.ld under src/arch/x86. With this new Kconfig variable, it is possible for the SoC/mainboard code for x86 to provide a custom linker file as well. Makefile.inc is updated for all architectures to use this new Kconfig variable instead of assuming memlayout.ld files under a certain path. All non-x86 boards used memlayout.ld under mainboard directory. However, a lot of these boards were simply including the memlayout from SoC. So, this change also updates these mainboards and SoCs to define the Kconfig as required. BUG=b:155322763 TEST=Verified that abuild with --timeless option results in the same coreboot.rom image for all boards. Change-Id: I6a7f96643ed0519c93967ea2c3bcd881a5d6a4d6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42292 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18src: Remove unused 'include <string.h>'Elyes HAOUAS
Unused includes found using following commande: diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|atol\|strrchr\|skip_atoi\|STRINGIFY' -- src/) |grep -v vendorcode |grep '<' Change-Id: Ibaeec213b6019dfa9c45e3424b38af0e094d0c51 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-05-18mainboard/*/*/*.cb: Remove leading blank lines from SPDX headerElyes HAOUAS
Change-Id: Ia0dbf7b946d42bda11b904a9caff5a402b553b33 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-05-18mainboard/*/*/Kconfig*: Remove leading blank lines from SPDX headerElyes HAOUAS
Change-Id: I7089b29e881d74d31477e2df1c5fa043fe353343 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41358 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13src: Remove unused '#include <stddef.h>'Elyes HAOUAS
Unused includes found using following commande: diff <(git grep -l '#include <stddef.h>' -- src/) <(git grep -l 'size_t\|ssize_t\|wchar_t\|wint_t\|NULL\|DEVTREE_EARLY\|DEVTREE_CONST\ |MAYBE_STATIC_NONZERO\|MAYBE_STATIC_BSS\|zeroptr' -- src/)|grep '<' |grep -v vendor |grep -vF '.h' Change-Id: Ic54b1db995fe7c61b416fa5e1c4022238e4a6ad5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41150 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11mb/google/kukui: fix screen scrolling on devices using anx7625Paul Ma
anx7625 enables MIPI receiver to check EOTP packet as default. If MIPI_DSI_MODE_EOT_PACKET is not set in flags, soc dsi will not send out EOTP packet and some panel models will display abnormal such as scrolling all the time. BUG=b:144824303 BRANCH=kukui TEST=boot damu board, edp panel with anx7625 as bridge boots up without scrolling. Signed-off-by: Paul Ma <magf@bitland.corp-partner.google.com> Change-Id: Iad651202bde2a40024af8c12153143ada2ce2439 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41161 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11mb/google/kukui: Fix backlight flash white before show logoJitao Shi
Turn backlight off before panel poweron. BUG=b:155107047 TEST=make # board = kukui BRANCH=kukui Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Change-Id: I0f31923bd7c1dfa26d4b1bbd0a230ae400b08ca3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41146 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-09src/: Replace GPL boilerplate with SPDX headersPatrick Georgi
Used commands: perl -i -p0e 's|\/\*[\s*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-only */|' $(cat filelist) perl -i -p0e 's|\/\*[\s*]*.*is[\s*]*free[\s*]*software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*either[\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License,[\s*]*or[\s*]*.at[\s*]*your[\s*]*option.[\s*]*any[\s*]*later[\s*]*version.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-or-later */|' $(cat filelist) perl -i -p0e 's|\/\*[\s*]*.*is[\s*#]*free[\s*#]*software[;:,][\s*#]*you[\s*#]*can[\s*#]*redistribute[\s*#]*it[\s*#]*and/or[\s*#]*modify[\s*#]*it[\s*#]*under[\s*#]*the[\s*#]*terms[\s*#]*of[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*as[\s*#]*published[\s*#]*by[\s*#]*the[\s*#]*Free[\s*#]*Software[\s*#]*Foundation[;:,][\s*#]*either[\s*#]*version[\s*#]*3[\s*#]*of[\s*#]*the[\s*#]*License[;:,][\s*#]*or[\s*#]*.at[\s*#]*your[\s*#]*option.[\s*#]*any[\s*#]*later[\s*#]*version.[\s*#]*This[\s*#]*program[\s*#]*is[\s*#]*distributed[\s*#]*in[\s*#]*the[\s*#]*hope[\s*#]*that[\s*#]*it[\s*#]*will[\s*#]*be[\s*#]*useful[;:,][\s*#]*but[\s*#]*WITHOUT[\s*#]*ANY[\s*#]*WARRANTY[;:,][\s*#]*without[\s*#]*even[\s*#]*the[\s*#]*implied[\s*#]*warranty[\s*#]*of[\s*#]*MERCHANTABILITY[\s*#]*or[\s*#]*FITNESS[\s*#]*FOR[\s*#]*A[\s*#]*PARTICULAR[\s*#]*PURPOSE.[\s*#]*See[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*for[\s*#]*more[\s*#]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-3.0-or-later */|' $(cat filelist) perl -i -p0e 's|(\#\#*)[\w]*.*is free software[:;][\#\s]*you[\#\s]*can[\#\s]*redistribute[\#\s]*it[\#\s]*and\/or[\#\s]*modify[\#\s]*it[\s\#]*under[\s \#]*the[\s\#]*terms[\s\#]*of[\s\#]*the[\s\#]*GNU[\s\#]*General[\s\#]*Public[\s\#]*License[\s\#]*as[\s\#]*published[\s\#]*by[\s\#]*the[\s\#]*Free[\s\#]*Software[\s\#]*Foundation[;,][\s\#]*version[\s\#]*2[\s\#]*of[\s\#]*the[\s\#]*License.*[\s\#]*This[\s\#]*program[\s\#]*is[\s\#]*distributed[\s\#]*in[\s\#]*the[\s\#]*hope[\s\#]*that[\s\#]*it[\s\#]*will[\#\s]*be[\#\s]*useful,[\#\s]*but[\#\s]*WITHOUT[\#\s]*ANY[\#\s]*WARRANTY;[\#\s]*without[\#\s]*even[\#\s]*the[\#\s]*implied[\#\s]*warranty[\#\s]*of[\#\s]*MERCHANTABILITY[\#\s]*or[\#\s]*FITNESS[\#\s]*FOR[\#\s]*A[\#\s]*PARTICULAR[\#\s]*PURPOSE.[\#\s]*See[\#\s]*the[\#\s]*GNU[\#\s]*General[\#\s]*Public[\#\s]*License[\#\s]*for[\#\s]*more[\#\s]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist) perl -i -p0e 's|(\#\#*)[\w*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist) Change-Id: Ia01908544f4b92a2e06ea621eca548e582728280 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41178 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-22mb/google/kukui: kakadu: update the EDID and sequenceScott Chao
The EDID and command sequence are from BOE, the vendor. BUG=b:148997748 TEST=Boots on Chromebook Kakadu and displayed developer firmware screen successfully. Change-Id: Ieb510cb28882afc5b8023c2a57b31187e4a09fbd Signed-off-by: Scott Chao <scott.chao@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40396 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-11mb/google/kukui: correct board nameScott Chao
Modify board name from "Kadadu" to "Kakadu" BUG=b:153590144 TEST=CPU log show "Starting depthcharge on Kakadu..." BRANCH=kukui Signed-off-by: Scott Chao <scott.chao@bitland.corp-partner.google.com> Change-Id: Ibf387b0e0153315ff2ab5c19381db44a61c14e96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40283 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-06mb/google/kukui: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I377ee2c9dfa3113f88237bd6ea79031a79f18ad5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40180 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-18mainboard/google: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I09cc279b1f75952bb397de2c3f2b299255163685 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2020-03-07chromeos: stop sharing write protect GPIO with depthchargeJoel Kitching
wpsw_boot is deprecated in favour of wpsw_cur. As such, coreboot no longer needs to share "write protect" GPIO with depthcharge. BUG=b:124141368, chromium:950273 TEST=make clean && make test-abuild BRANCH=none Change-Id: I2fcb7f82aa063fd72928171af5cbef0356ba620c Signed-off-by: Joel Kitching <kitching@google.com> Cq-Depend: chromium:2088434 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39318 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-17mb/google/kukui: fine tune the video timing of panel-BOE_TV101WUM_N53Jitao Shi
Fine tune the video timing of panel-BOE_TV101WUM_N53 to avoid noise. The parameters are based on BOE NV101WUM-N53 preliminary product spec. BRANCH=kukui BUG=b:147378025 TEST=bootup pass Change-Id: Ia9e2cc90f233e87d712c2dc6f4441ca2e5423162 Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38401 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-17mb/google/kukui: Add panel for KakaduCasper Chang
Declare the following panel for Kakadu: - BOE_TV105WUM_NW0 BUG=b:148997748 TEST=build Kakadu image passed BRANCH=kukui Signed-off-by: Casper Chang <casper_chang@bitand.corp-partner.google.com> Change-Id: I394b8cafa8be40e5fd6bf8ceb81b520df73718a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38822 Reviewed-by: Peichao Li <peichao.wang@bitland.corp-partner.google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-14mb/google/kukui: Support panels using ANX7625Hung-Te Lin
For Kukui followers using ANX7625 eDP bridge to access panel. BUG=b:140132295 TEST=make # board = kukui Change-Id: I7dc9c68d076fd0ba4e963cde9414d25c17b332cb Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-23Kconfig: comply to Linux 5.3's Kconfig language rulesPatrick Georgi
Kconfig became stricter on what it accepts, so accomodate before updating to a new release. Change-Id: I92a9e9bf0d557a7532ba533cd7776c48f2488f91 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-11-15mb/google/kukui: Add new board 'kakadu'Hung-Te Lin
Add a new Kukui follower 'kakadu'. BUG=None TEST=make # select kakadu Change-Id: I9f25ce90285828c43435e45d9361ee7128d407fa Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36848 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-12mb/google/kukui: Add new configs 'damu' and 'kappa'Hung-Te Lin
New boards introduced to Kukui family. BUG=None TEST=make # select damu and kappa Change-Id: I7154aeee921114b7d12bf586adca250df19a3883 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-11-01mb/google/kukui: Unselect FATAL_ASSERTElyes HAOUAS
FATAL_ASSERT is used for debugging purpos. Don't select it by default. Change-Id: If4d521827f3d50fb662b89b24d00fb0517e7af2d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-10-20src: Remove unused 'include <string.h>'Elyes HAOUAS
Change-Id: I2a94c3b6282e9915fd2b8136b124740c8a7b774c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-09soc/mediatek/mt8183: Run DRAM full calibrationHuayang Duan
Load the calibration params from flash first and check the correctness of the params. If the params have correct format, perform DRAM fast calibration with these params to reduce bootup time. Otherwise, load the DRAM blob and perform DRAM full calibration. Bootup time of DRAM partial calibration: - 1,349,385 usecs with low frequency - 924,698 usecs with middle frequency - 1,270,089 usecs with high frequency 3,544,172 usecs in total. Bootup time of DRAM fast calibration: - 216,663 usecs with low frequency - 328,220 usecs with middle frequency - 322,612 usecs with high frequency 867,495 usecs in total. BUG=b:139099592 BRANCH=none TEST=emerge-kukui coreboot Change-Id: I8de29b14b1fb24b3b4f351c855c5c4d8f350cc34 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35110 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-10-09soc/mediatek/mt8183: Use cached calibration result for faster bootupHuayang Duan
Load calibration params from flash. If the format of the params is correct, use these calibration params for fast calibration to reduce the bootup time. Bootup time of DRAM partial calibration: - 1,349,385 usecs with low frequency - 924,698 usecs with middle frequency - 1,270,089 usecs with high frequency 3,544,172 usecs in total. Bootup time of DRAM fast calibration: - 216,663 usecs with low frequency - 328,220 usecs with middle frequency - 322,612 usecs with high frequency 867,495 usecs in total. BUG=b:139099592 BRANCH=none TEST=Boots correctly on Kukui Change-Id: I9ef4265dd369a1c276bb02294696556df927e7bc Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35164 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-04mb/google/kukui: Extend FMAP to 8MB layoutHung-Te Lin
The SPI flash component requirement for Kukui family is 8M so we should update FMAP for that: - Add more comments for alignment and size recommendation. - Enlarge RO to 4M, and RW_SECTION_{A,B} both ~1.5M. - BOOTBLOCK: 32K->128K, aligned with other ARM boards. - Preserve RW_DDR_TRAINING for new calibration. - Reorder the sections for better alignment. - RW_MISC to contain RW sections that should be merged when creating AU image. BUG=b:134624821 TEST=Built Kukui image and boots. dump_fmap -h image-kukui.bin: # name start end size RW_LEGACY 00700000 00800000 00100000 RW_SHARED 006f7000 00700000 00009000 RW_UNUSED 006f8000 00700000 00008000 SHARED_DATA 006f7000 006f8000 00001000 RW_SECTION_B 00580000 006f7000 00177000 RW_FWID_B 006f6f00 006f7000 00000100 FW_MAIN_B 00582000 006f6f00 00174f00 VBLOCK_B 00580000 00582000 00002000 RW_MISC 00577000 00580000 00009000 RW_ELOG 0057f000 00580000 00001000 RW_DDR_TRAINING 0057d000 0057f000 00002000 RW_NVRAM 0057b000 0057d000 00002000 RW_VPD 00577000 0057b000 00004000 RW_SECTION_A 00400000 00577000 00177000 RW_FWID_A 00576f00 00577000 00000100 FW_MAIN_A 00402000 00576f00 00174f00 VBLOCK_A 00400000 00402000 00002000 WP_RO 00000000 00400000 00400000 RO_VPD 003f8000 00400000 00008000 RO_SECTION 00000000 003f8000 003f8000 RO_FRID 003f7f00 003f8000 00000100 GBB 003f5000 003f7f00 00002f00 COREBOOT 00021000 003f5000 003d4000 FMAP 00020000 00021000 00001000 BOOTBLOCK 00000000 00020000 00020000 Change-Id: Id342d57dc95c6197d05b8a265742a2866c35ae09 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-10-02mediatek/mt8183: Rename fields of struct sdram_paramsYu-Ping Wu
Two fields of struct sdram_params are renamed for future CL of DRAM full calibration. Field 'impedance' is also removed. BUG=none BRANCH=none TEST=emerge-kukui coreboot Change-Id: I2f9673fd5ea2e62ee971f0d81bdd12aaf565e31c Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35738 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-30mediatek/mt8183: Init SPM driverDawei Chien
To support mt8183 power saving during suspend to RAM, this patch loads SPM firmware to support SPM suspend. SPM needs its own firmware to do these power saving in the right timing under correct conditions. After linux PM suspends, SPM is able to turn off power for the last CPU and do more power saving for the SoC such as DRAM self-refresh mode and turning off 26M crystal. BUG=none BRANCH=none TEST=suspend/resume passes for LPDDR4 3200 Change-Id: I3393a772f025b0912a5a25a63a87512454fbc86e Signed-off-by: Dawei Chien <dawei.chien@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-09-30mb: remove test-only HWIDsHung-Te Lin
The CONFIG_GBB_HWID can be generated automatically now so we can remove the test-only HWIDs set in board config files. BUG=b:140067412 TEST=Built few boards (kukui, cheza, octopus) and checked HWID: futility gbb -g coreboot.rom Change-Id: I4070f09d29c5601dff1587fed8c60714eb2558b7 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35635 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-25mb/google/kukui: Add new build target 'Juniper'Hung-Te Lin
Add the configuration 'Juniper' for the new mainboard. BUG=b:137517228 TEST=make menuconfig; select 'juniper' and build Change-Id: I94e3ac7f6de3fecf177e344cb217eaecf6362d69 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-09-17google/kukui: Pass reset gpio parameter to BL31Tristan Shieh
To support gpio reset SoC, we need to pass the reset gpio parameter to BL31. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui and ATF(BL31) can get this parameter. Change-Id: Iefa70dc0714a9283a79f97d475b07ac047f5f3b0 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-09-12mediatek/mt8183: tune EDID for BOE panelPeichao Wang
BUG=b:140545315 TEST=builds Kodama image and verify display working properly Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I52a56f9bbbbef5937a9601f9371e415c74ac9a7c Reviewed-on: https://review.coreboot.org/c/coreboot/+/35317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2019-09-10mb/google/kukui: Enable MT8183_DRAM_EMCPHuayang Duan
MT8183_DRAM_EMCP is enabled for devices using eMCP to run at a high DRAM frequency (e.g., 3600Mbps). BUG=b:80501386 BRANCH=none TEST=Memory test passes on EMCP platform Change-Id: Icf875427347418f796cbf193070bf047844d2267 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34433 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-26google/kukui: Enable CHROMEOS_USE_EC_WATCHDOG_FLAGYu-Ping Wu
Kukui AP doesn't remember if the last AP reset was due to AP watchdog. We need to enable CHROMEOS_USE_EC_WATCHDOG_FLAG so that it will query the reset reason from EC. BUG=b:109900671,b:118654976 BRANCH=none TEST=1. run 'mosys eventlog clear; stop daisydog; echo > /dev/watchdog' 2. wait for watchdog reset 3. check 'mosys eventlog list | grep watchdog' Change-Id: I053cc7664bbaf0d3fcae26ba9481a0ad700dca90 Signed-off-by: You-Cheng Syu <youcheng@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-08-23mb/google/kukui: Add panel for KodamaPeichao Wang
Declare the following panel for Kodama: - AUO B101UAN08.3 BUG=b:139699622 TEST=builds Kodama image and working properly Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I3f688ffd0ece6afac08d353ab5a6cf1cf876b32f Reviewed-on: https://review.coreboot.org/c/coreboot/+/35001 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-04 21:07:06 +0000