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2019-04-11mb/google/ampton: Fix polarity of EN_PP3300_WLAN_L signal.Tim Wawrzynczak
WiFi enable signal was configured and driven as active-high, but the signal is |To start the server in this Emacs process, stop the existing actually active-low BUG=b:130196983 BRANCH=none TEST=Verified WiFi still works after boot, and also after a suspend/resume cycle. Device powers down correctly using "poweroff". Change-Id: I64a67f73564188ad0548a1a770169ef2bca47453 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32255 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-11mb/google/octopus: Disable WLAN prior the entry of S5Kane Chen
ODM reported issues that some systems can't be shutdown to S5 very occasionally. ODM found issue is gone if they remove the WLAN card. So, this change to disable WLAN before system enters S5. This change is validated by ODM and it does help issue. BUG=b:129377927 Change-Id: Ib8e81022b8c9b63bc75e5cc14121233222da7595 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32246 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Chen Wisley <wisley.chen@quantatw.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-27mb/google/octopus/variants: Remove bipEvan Green
Remove bip, as it is no longer actively developed, and its EC overflowed storage, so the EC build is no longer viable. BUG=b:129283539 BRANCH=none TEST=emerge-octopus coreboot chromeos-bootimage CQ-DEPEND=CL:1538819,CL:*1086038 Signed-off-by: Evan Green <evgreen@chromium.org> Change-Id: Ie9ffa704af3523908858d382e2c188422323550e Reviewed-on: https://review.coreboot.org/c/coreboot/+/32053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-22mb/google/octopus: Add keyboard backlight support for bloogTony Huang
Bloog supports keyboard backlight feature, so enable the ASL code. BUG=b:127736039 BRANCH=octopus TEST=Build and boot bloog, verify that the string 'KBLT' is in the DSDT. Change-Id: Iba66aade090816ea2376cae4baf4aae019cc97f4 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2019-03-20src: Use 'include <string.h>' when appropriateElyes HAOUAS
Drop 'include <string.h>' when it is not used and add it when it is missing. Also extra lines removed, or added just before local includes. Change-Id: Iccac4dbaa2dd4144fc347af36ecfc9747da3de20 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-03-16x86/smbios: Untangle system and board tablesNico Huber
We were used to set the same values in the system and board tables. We'll keep the mainboard values as defaults for the system tables, so nothing changes unless somebody overrides the system table hooks. Change-Id: I3c9c95a1307529c3137647a161a698a4c3daa0ae Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-03-14mb/google/octopus: Create Bloog variantTony Huang
This commit create bloog variant for Octopus. Initial settings are copy from meep. Remove I2C tuning, WACOM digitizer and WEIDA touchscreen. Override GPIO configuration for unused LTE and Pen. BUG=b:127736039 BRANCH=octopus TEST=None Change-Id: I1d04c97cb0622075a25825ba2c835d556c8b0423 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-05mainboard: Enable PRESERVE flag in all vboot/chromeos FMD filesHung-Te Lin
For Chrome OS (or vboot), The PRESERVE flags should be applied on following sections: RO_PRESERVE, RO_VPD, RW_PRESERVE, RW_ELOG, RW_NVRAM, RW_SMMSTORE, RW_VPD, RO_FSG (b:116326638), SI_GBE (chromium:936768), SI_PDR (chromium:936768) With the new PRESERVE flag, we don't need RO_PRESERVE and RW_PRESERVE in the future. But it's still no harm to use it if there are multiple sections all needing to be preserved. BUG=chromium:936768 TEST=Builds google/eve and google/kukui inside Chrome OS source tree. Also boots successfully on eve and kukui devices. Change-Id: I6664ae3d955001ed14374e2788d400ba5fb9b7f8 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-03-05mb/google/octopus: Add 6GB dual-channel memory configurationSeunghwan Kim
Add 6GB dual-channel memory configuration for future use. BUG=b:124634885 BRANCH=octopus TEST=emerge-octopus coreboot Change-Id: I36d6c704ac6708b29cc570a2209eeb32de6148b3 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31460 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-04arch/io.h: Drop unnecessary includeKyösti Mälkki
Change-Id: I91158452680586ac676ea11c8589062880a31f91 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31692 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-18mb/google/laser: Disable touch screen device that according to SKU IDpeichao.wang
We need disable touch screen device on laser SKU ID 6. BUG=none TEST=according to sku_id (Laser(convertible): 5, Laser14(clamshell): 6, Laser14(clamshell + touch):7) distinguish whether disable touch screen device. Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I6953c35a5e8c93d88fe63362156faa351e8ee71f Reviewed-on: https://review.coreboot.org/c/31428 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-15mb/google/octopus: Fix USB ACPI configuration for CNVi BT moduleKarthikeyan Ramasubramanian
CNVi Bluetooth module is at port 8 (zero-indexed) and not at port 9. Fix the device configuration in the devicetree. BUG=b:123296264 BRANCH=octopus TEST=Boots to ChromeOS. Checked the SSDT table to ensure that the reset gpio is exported under the device \_SB_.PCI0.XHCI.RHUB.HS09. Ensured that the kernel btusb driver is able to find the exported GPIO in the devices with CNVi BT module. Change-Id: I302bc87b18a1aaad77bfb73d607ba28b89b79c14 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/31387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-12mb/google/octopus/casta: Tune usb2eye settingSeunghwan Kim
It needs to tune usb2eye setting for these ports: USB2[4] - type-c port USB2[6] - camera BUG=b:122878632 BRANCH=octopus TEST=built and passed usb2eye SI test Change-Id: Iaa3adaab2f391e95730b141dc0237ca62c459e5a Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/31359 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-08drivers/gpio_keys: Remove redundant is_wakeup_source flagKarthikeyan Ramasubramanian
"is_wakeup_source" flag is used to indicate if the concerned device can trigger a wakeup. This flag is redundant with the "wake" GPE event definition. So remove the redundant flag and use the "wake" GPE event to mark the wakeup source. BUG=None BRANCH=None TEST=Boot to ChromeOS. Ensure that the device is marked as wakeup-source in SSDT if wake GPE is configured. Ensure that the system can suspend and the device acts as a wakeup source Change-Id: I99237323639df1cb72e3a81bcfed869900a2eefa Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/31258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-05mb/google/octopus: Add USB ACPI configuration for CNVi BT moduleKarthikeyan Ramasubramanian
This change enables exporting the reset GPIO for CNVi Bluetooth module to the kernel for use in an rf-kill operation. BUG=b:123296264 BRANCH=octopus TEST=Boots to ChromeOS. Checked the SSDT table to ensure that the reset gpio is exported under the device \_SB_.PCI0.XHCI.RHUB.HS09. Ensured that the kernel btusb driver is able to find the exported GPIO in the devices with CNVi BT module. Change-Id: I10f28bfe705da5104d709ae2ed91a8ae003fa639 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/31183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-31mb/google/octopus: Add Bluetooth USB ACPI configurationKarthikeyan Ramasubramanian
Enable USB ACPI driver for octopus boards and add bluetooth USB ACPI configuration in devicetree. This change enables exporting the bluetooth reset GPIO to the kernel for use in an rf-kill operation. BUG=b:123296264 BRANCH=octopus TEST=Boots to ChromeOS Change-Id: Ie40f1ad70f21a6fd398ce23d060e0c588ba6ce41 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/31130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-01-30mb/google/octopus/casta: Correct unused GPIO pad configurationSeunghwan Kim
Real unused GPIO pad is GPIO_123, but GPIO_122 is configured as unused pad. This patch corrects the configuration. BUG=NONE BRANCH=octopus TEST=emerge-octopus coreboot Change-Id: I4473bd66a4162f5aee3b998aacba906824728fc8 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/31135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2019-01-29mb/google/octopus/var/phaser: Hook up Raydium touchscreenHao He
List Raydium touchscreen in the devicetree so that the correct ACPI device are created. BUG=b:121105424 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage reflash the coreboot to DUT, make sure the Raydium touchscreen can work. Change-Id: I9ffb2a858f31a8b003086806de07f4079870cddf Signed-off-by: Hao He <hao.he@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/31116 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-28mb/google/octopus: Fix termination for unused dual voltage pinsShamile Khan
These pins should not have pull downs configured in standby state as that can cause contention on the termination circuitry and lead to incorrect behavior as per Doc# 572688 Gemini Lake Processor GPIOTermination Configuration. BUG=b:79982669 TEST=Checked that code compiles with changes. Change-Id: If3cadc000ec6fc56019ee3f57e556dc819d5e0a5 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/c/30823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-28mainboard/google/octopus/variants/casta: Decrease touchpad I2C CLK frequencySeunghwan Kim
ELAN touchpad supports up to 400KHz, so we need to limit its CLK frequency to 400HKz. BUG=b:123376618 BRANCH=octopus TEST=built and verified touchpad I2C clk frequency gets be lower than 400KHz Change-Id: If7a43fe20c7e5abdf23c8c36e34c072c371563bf Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/31085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-25mb/google/octopus: Override emmc DLL values for AmptonKane Chen
New emmc DLL values for Ampton BUG=b:122307153 TEST=Boot to OS on 5 systems Change-Id: Iadd58d254f4bb384f483c2c3e5615f7569d5211c Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/31048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2019-01-24mb/google/octopus/bobba: Add support to handle PEN_EJECT eventKarthikeyan Ramasubramanian
Enable gpio_keys driver for bobba and add required configuration in the device tree to handle the pen eject event. BRANCH=octopus BUG=b:117953118 TEST=Ensure that the system boots to ChromeOS. Ensure that the stylus tools open on pen eject. Ensure that the system wakes on Pen Eject. Ensure that the system enters S0ix and S3 states after the pen is ejected. Ensure that the system enters S0ix and S3 states when the pen remains inserted in its holder. Ensured that the system does not wake when the pen is inserted. Ensure that the suspend_stress_test runs successfully for 25 iterations with the pen placed in its holder. Change-Id: I768b89d2b45f4dcab6d235b11ce00544a827f22d Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/30108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-23mb/google/octopus: Override emmc DLL values for MeepKane Chen
New emmc DLL values for Meep. BUG=b:122308271 TEST=Boot to OS on 13 Meep system Change-Id: I4247114ed69ff3aa283f0f72d5531ad0f37309ad Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/31021 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-20mb/google/octopus/variants: Disable xHCI compliance mode for FleexAmanda Huang
Some usb devices exhibits signal loss which causes xHCI entering compliance mode. The resolution is to disable xHCI compliance mode. BRANCH=octopus BUG=b:120009029 TEST=Verified usb operation successfully. Change-Id: Ic7fa08c894397598dee3c4ff9a764e43383a0627 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2019-01-20mb/google/octopus/variants/meep: Disable xHCI compliance modeWisley Chen
Some usb devices exhibit signal loss which causes xHCI entering compliance mode. The resolution is to disable xHCI compliance mode. BUG=b:122671995 TEST=check "Disable Link Compliance Mode" bit of "SuperSpeed Port Link control" register and usb operation successfully. Change-Id: Ia2ae7e52391fadc8ed23b8b76c45d410757d22ec Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/30948 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-16buildsystem: Promote rules.h to default includeKyösti Mälkki
Does not fix 3rdparty/, *.S or *.ld or yet. Change-Id: I66b48013dd89540b35ab219d2b64bc13f5f19cda Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/17656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-14mb/google/octopus/variants: Configure PLT_RST_L pad IOSSTATE maskedJohn Zhao
PLT_RST_L was asserted twice at boot-up and a glitch was observed when coming out of suspend mode. Configure PLT_RST_L pad IOSSTATE from HIZCRx1 to be masked. BRANCH=octopus BUG=b:117302959 TEST=Verified no glitch on PLT_RST_L at S3 and PLT_RST_L stays high 3.3v during S0ix. Change-Id: I8c23aadda72be54fb45e67aab2bc8ed51e473bae Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30815 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-14mb/google/octopus/variants: Disable xHCI compliance modeJohn Zhao
Some usb devices exhibits signal loss which causes xHCI entering compliance mode. The resolution is to disable xHCI compliance mode. BRANCH=octopus BUG=b:115699781 TEST=Verified usb operation successfully. Change-Id: I41fecaa43f4b1588a0e4bbfc465d595feb54dd24 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30817 Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-11soc/mainboard: Update mainboard UART KconfigLijian Zhao
After f5ca922 (Untangle CBFS microcode updates) got merged, all mainboard using intel apollolake, cannonlake, coffeelake, glk, kabylake, skylake, icelake and whiskeylake get affected. Using INTEL_LPSS_UART_FOR_CONSOLE instead of UART_DEBUG and set default console for each platform. BUG=N/A TEST=Build and test on Sarien platform, by default we can still get console from cbmem, and enable CONSOLE_SERIAL can get logs from UART port 2. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I550a00144cff21420537bb161c64e7a132c5d2de Reviewed-on: https://review.coreboot.org/c/30853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-10mainboard/google/octopus: configure EC_AP_INT_ODLJett Rink
Enable the EC_AP_INT_ODL interrupt on GPIO_134 for all octopus boards that support it. Also removing unnecessary IO standby support since we don't use this pin to wake up the SoC. BRANCH=octopus BUG=b:122552125,b:120679547 TEST=CTS tests with changes Change-Id: I018864ae5fa400372b5b443e49828e8202b9aa4d Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://review.coreboot.org/c/30788 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-06device: Use pcidev_path_on_root()Kyösti Mälkki
Change-Id: I2e28b9f4ecaf258bff8a062b5a54cb3d8e2bb9b0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-02mb/google/octopus/variants: Add 20ms reset delay for WACOM deviceMarco Chen
Add reset delay in power resource to prevent from failing to bind after unbinding. And boards including yorp series - bobba / phaser and bip series - ampton are affected. BUG=b:121286833 BUG=b:117474421 BUG=b:121019320 BRANCH=None TEST=emerge-octopus coreboot, verified that WACOM touchscreen can re-bind successfully. Change-Id: Icf690fc8e9450d559b642d1c88e29ff5d52c5488 Signed-off-by: Marco Chen <marcochen@chromium.org> Reviewed-on: https://review.coreboot.org/c/30422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-29mb/google/octopus: Override emmc DLL values for FleexBora Guvendik
New emmc DLL values for Fleex. BUG=b:120561055 TEST=Boot to OS, chromeos-install, mmc_test Change-Id: Id0022e9d0f0a7802113bbf193decff3c8aaa04f8 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/30226 Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-28mb/google/octopus: Override emmc DLL values for PhaserBora Guvendik
New emmc DLL values for Phaser. BUG=b:120561055 TEST=Boot to OS, chromeos-install, mmc_test Change-Id: Ie8d56e0faf5c96d980c0614a61fbc6eacf582943 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/30144 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-24Revert "mb/google/octopus/variants/fleex: Update Charger throttling settings"Sumeet Pawnikar
This reverts commit 969ed357f823659a6861a2ca38f3ad9d7b58f949 Reason for revert: According to partner issue b:112448519 comment#80, it impacts skin temperature specifications. Change-Id: I7603c3816f34adebc1f67eff6fad214557544022 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/30366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-12-22Revert "mb/google/octopus: Add custom SAR values for Bobba"Justin TerAvest
This reverts commit a914152fa6072c443ccd18de22412b47a228e754. Reason for revert: According to the partner on this project, custom values like this are no longer necessary. Change-Id: I393eb4997f58abe0f77161999474994f06741519 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/c/30347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-12-19mb/google/octopus: Override emmc DLL values for YorpBora Guvendik
New emmc DLL values for Yorp. BUG=b:120561055 BRANCH=octopus TEST=Boot to OS, chromeos-install, mmc_test Change-Id: I771c959a15959160224f056c0a16aa65bfbba94e Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/30073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-12-19mb/google/octopus/var/ampton: Tune I2C AudioJustin TerAvest
The previous settings caused the I2C frequency for the audio bus to be too high, at 417kHz. The settings in this commit correct the frequency to 396kHz. BUG=b:119423345 Change-Id: Ibed886e6e1b0df4df6b87f6291e515364b3bf718 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/c/30129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-17mb/google/octopus/variants/fleex: Update Charger throttling settingsSumeet Pawnikar
Update dptf settings for Charger throttling. Also, update Power Limit1 minimum value setting from 4.5W to 3W. BUG=b:112448519 BRANCH=octopus TEST=Built and tested on Fleex system Change-Id: I8c2a796ff28254ebef28ed5745b344f925d6e649 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/30080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-12-17mb/google/octopus: Add custom SAR values for BobbaJustin TerAvest
Bobba would prefer to use different SAR values per sku-id for regulatory compliance. This commit uses the newly added interface for custom wifi SAR CBFS filenames. CQ-DEPEND=CL:*729429 BUG=b:120958726 BRANCH=octopus TEST=build Signed-off-by: Justin TerAvest <teravest@chromium.org> Change-Id: I354382d651d65d533459f0ca460ca6fd6de547fd Reviewed-on: https://review.coreboot.org/c/30223 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-12-14mb/google/octopus: Override emmc DLL values for BobbaBora Guvendik
New emmc DLL values for Bobba. BUG=b:120561055 TEST=Boot to OS, chromeos-install, mmc_test Change-Id: I5a0d9587a91b3c71c042cd8ea360c816ea29fb91 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/30176 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-12mb/google/octopus/ampton: Fix the TRACKPAD_INT_ODL GPIO configurationKarthikeyan Ramasubramanian
Update the TRACKPAD_INT1_1V8_ODL GPIO configuration so that it acts as a wakeup source BUG=b:119598593 BRANCH=octopus TEST=Ensure that the system wakes up on trackpad events. Ensure that the suspend_stress_test runs successfully for 25 iterations. Change-Id: I28292682cf9c8037abb87d265e49a60139550db2 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/30171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-11mb/google/octopus/variants/meep: Add 20ms reset delay for WACOM deviceTony Huang
Add reset delay in power resource to prevent bind to fail after unbind. BUG=b:119795901 BRANCH=master TEST=emerge-octopus coreboot, verified that WACOM touchscreen can re-bind successfully. Change-Id: Idcf02b1c931ed64951995403ec9ebe6b8f2db31d Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30099 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-10mb/google/octopus: Update the PEN_EJECT GPIO configurationKarthikeyan Ramasubramanian
PEN_EJECT GPIOs are active high and also require an internal pull-up. Update the GPIO configuration appropriately. BRANCH=octopus BUG=b:117953118 TEST=Ensure that the system boots to ChromeOS. Ensure that the stylus tools open on pen eject. Ensure that the system can enter S0ix and S3 states successfully when the pen is inserted. Ensure that the system wakes on Pen Eject. Ensure that the system does not enter S0ix and S3 states when the pen is placed in its holder. Ensure that the suspend_stress_test runs successfully for 25 iterations with the pen placed in its holder. Change-Id: Ibf9cb214a8ce7561efbb77a7e99d1e386cf064c3 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/30107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-09mb/google/octopus/phaser: Fix trackpad GPE wake configurationKarthikeyan Ramasubramanian
Synaptics Trackpad wake event is incorrectly routed to GPE0_DW2_02. The concerned GPIO is not connected and hence wont trigger a wakeup. Fix the GPE wake configuration for synaptics trackpad. BUG=b:120666158 BRANCH=octopus TEST=Ensure that the wake on trackpad works with Synaptics touch pad. Ensure that the system can enter S0ix successfully(run suspend_stress_test -c 25). Change-Id: I87b8c266266280f61700839d428e6f8938b0f72f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/30105 Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-03mb/google/octopus: Enable mode change as wake source from S3/S0ixFurquan Shaikh
This change enables mode change as a wake source from S3 and S0ix. Thus, any time the device switches between clamshell and tablet mode while it is suspended, it will be treated as a valid user event and hence wake source. BUG=b:120349473 BRANCH=octopus TEST=Verified that octopus wakes up on mode transitions. Change-Id: Ib224df434730f873ce5514303e5d043cbc85a9a4 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/30001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2018-11-30cpu/intel/common: Use a common acpi/cpu.asl fileArthur Heymans
Change-Id: Ifa5a3a22771ff2e0efa14fb765603fd5e0440d59 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: David Guckian
2018-11-29mb/google/octopus: Create Casta variantKarthikeyan Ramasubramanian
This commit create a casta variant for Octopus. The initial settings override the baseboard GPIO configuration for Touchscreen, LTE, Pen and Trace modules. BUG=b:119056117 BRANCH=None TEST=None Change-Id: I5d3f7df66981d84fb47a6aa248480ef53dfd90d0 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/29763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-27mb/google/octopus/var/phaser: Deprecate board id 0Furquan Shaikh
This change gets rid of bid0_override_table as part of clean up effort to deprecate bid0. Additionally, it updates the touchscreen enable GPIO in overridetree and gets rid of code in variant.c to update enable gpio at runtime. BUG=b:119885949 Change-Id: I527973747e7d81ec47997da57eeb15f38d3ac2fd Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/29787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-25 21:07:59 +0000