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path: root/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
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2018-07-11skylake: Remove "IshEnable"li feng
Remove "IshEnable" from soc_intel_skylake_config since it's not used anymore. Enable/disable ISH by checking if ISH device is turned on or not. Refer to https://review.coreboot.org/#/c/coreboot/+/26485/. BUG=b:79244403 BRANCH=none TEST=Built. Change-Id: I4d2889af118659852431c87cb516fd19b577efc5 Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://review.coreboot.org/26521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-06google: Use proper ACPI ID for Semtech chips: STHGwendal Grignou
Change-Id: I85cd567a923cccd2504f351aae276b5f0d9db4de Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://review.coreboot.org/27347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt Delco <delco@google.com> Reviewed-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-21mb/google/poppy/variants/nautilus: Add SAR sensor device into devicetree.cbSeunghwan Kim
This change defines SAR sensor device into devicetree.cb. Since only LTE sku has SAR sensor, we will use GPP_B20 as a device_present_gpio. BUG=None BRANCH=poppy TEST=Verified SAR sensor device is loaded by driver in Chrome OS Change-Id: Ib4969e4b82d18b1b1a599de8226c2d7d4bda7915 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/27149 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-21mb/google/poppy/variants/nautilus: Configure for 2nd nautilus SKUSeunghwan Kim
For supporting new SKU, we need to override GPIO table and device configuration. The board ID of 2nd SKU of nautilus is started from 9, so we would determine SKU with it. BUG=b:80052672 BRANCH=poppy TEST=emerge-nautilus coreboot Change-Id: I7242f23f47010664cc29ea86a126e63c9dd62ccd Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/27147 Reviewed-by: Enrico Granata <egranata@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-18mb/google/poppy/variants/nautilus: Correct USB OC pin configurationSeunghwan Kim
Due to schematic, we need to correct USB OC pin configuration. - OC0 for Type-C Port 1 - OC1 for Type-C Port 0 - OC2 for Type-A Port - OC3 to NC BUG=NONE BRANCH=poppy TEST=emerge-nautilus coreboot Change-Id: Ic71baef646926cc6aadcc5dda7cb14f00e8d3687 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/27099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-06soc/intel/common/block: Add common chip config blockSubrata Banik
Adding common chip config structure which will be used to return data to common code. When common code requires soc data, code used to fetch entire soc config structure. With this change, common code will only get the data/structure which is required by common code and not entire config. For now, adding i2c, gspi and lockdown configuration which will be used by common code. BUG=none BRANCH=b:78109109 TEST=compile code for APL/SKL/CNL. Boot using SKL/APL/CNL and check values are returned properly using common structure. Change-Id: I7f1671e064782397d3ace066a08bf1333192b21a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/26189 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Hannah Williams <hannah.williams@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-05soc/intel/skylake: Add option to skip coreboot MP initSubrata Banik
This patch provides option for mainboard to skip coreboot MP initialization if required based on use_fsp_mp_init. Option for mainboard to skip coreboot MP initialization * 0 = Make use of coreboot MP Init * 1 = Make use of FSP MP Init Default coreboot does MP initialization. Change-Id: I8de24e662963f4600209ad1b110dc950ecfb3a27 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26818 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-27mb/google/poppy,soraka,nautilus: Enable xDCIFurquan Shaikh
This change enables xDCI controller on poppy, nautilus and soraka. BUG=b:78577893 BRANCH=poppy Change-Id: I9b0f81bda889b822479ead4d1acc2b613151a304 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25849 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-18mb/google/poppy/variants: Set VmxEnable to 1Furquan Shaikh
This change sets VmxEnable to 1 to match the kernel setting. If this feature is enabled at the kernel level and not in FSP, then there is an issue where FSP expects it to be disabled so it forces a cold reboot on every warm reboot. BUG=b:78129261 BRANCH=poppy Change-Id: Idedbde1d8eb0c9e959733b7b50e5dec804d61cae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25698 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-28soc/intel/skylake: Limit xDCI feature when VBOOT is enabledDuncan Laurie
Use the common xDCI function to check if the controller is allowed in the current mode before enabling it. Otherwise, disable the PCI device if it has been enabled in devicetree. To make the SOC behavior consistent the XdciEnable config option is removed in favor of direct control by devicetree.cb and the mainboards that had defined it were adjusted accordingly. This was tested on an Eve board with xDCI enabled in devicetree.cb to ensure the xDCI device is enabled in developer mode and disabled in normal mode. Change-Id: Ic3c84beac87452f17490de32082030880834501d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/25365 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-07mb/google/poppy/variant/nautilus: Configure GPP_B0 for WLAN wakeSeunghwan Kim
As per the latest schematics, this change configures GPP_B0 as wake source for WLAN. BUG=NONE BRANCH=master TEST=emerge-nautilus coreboot Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Change-Id: I72b940452cfbbe471279ef117a868a8ae0b65b8b Reviewed-on: https://review.coreboot.org/23526 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-05mb/google/poppy/variants: Set pch_trip_temp to 75CFurquan Shaikh
Similar to Soraka, this change sets the pch_trip_temp value to 75C. This is important so that PMC can shutdown the thermal sensor when CPU is in C-state and DTS temp <= pch_trip_temp. BUG=b:74089135 Change-Id: Ic46fa0681796b821dfb014ab91734c960df7846a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/24968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-03-01mb/google/poppy/variant/nautilus: Change SlowSlewRateForSa settingSeunghwan Kim
If switch to VT2 on nautilus, screen flicker appears. We found if we rollback the change of slew rate setting, then the flicker issue will be gone: https://review.coreboot.org/c/coreboot/+/22588 But nautilus board needs slew rate tuning to reduce EE noise, so we decided to change only SlowSlewRateForSa to 2 (Fast/8) instead of rollback the whole change of the CL:22588. It can remove the flicker on VT2. BUG=b:71397040 BRANCH=master TEST=emerge-nautilus coreboot Change-Id: Id1d4bd8b1316c02c783de708ec4658e030193a26 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/23877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-16mb/google/{soraka,poppy,nautilus}: Set psys_pmax to 45WNaresh G Solanki
Soraka, Poppy & Nautilus are designed to operate at max power of 45 Watt. Hence set psys_max to 45W. BUG=b:66066340 BRANCH=None TEST=Build and boot soraka. Change-Id: If6f624733830b462329b5f539c20e2aea664143e Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/23757 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
2018-02-15mb/google/poppy/variant/nautilus: Enable and configure DPTFSeunghwan Kim
This change enables DPTF and configures the policy. DPTF parameters were provided by internal power team. BUG=b:67877437 BRANCH=master TEST=emerge-nautilus coreboot Change-Id: I31b31d5282ab38278bc68045ce75fdc6192f1144 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/23731 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-31mb/google/poppy/variants/nautilus: Add gpio-keys ACPI node for PENHFurquan Shaikh
This change uses gpio_keys driver to add ACPI node for pen eject event. BUG=b:71329519 TEST=Verified using evtest that pen eject event results in events as expected. Change-Id: Ib293c2ca532c8ed9e2587143b1a69300cd9fa4e9 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-01-26mb/google/poppy/variants/nautilus: Update camera power enable GPIOsFurquan Shaikh
This change updates the camera power enable GPIOs as per the latest schematics. With this update, since one of the enable GPIOs is using a UART0 pin, set UART0 to PchSerialIoSkipInit in devicetree so that FSP-S does not re-configure the UART0 GPIOs. BUG=b:68964831 Change-Id: I5d9126ed8ca2b714f6276f4d3a24c243d7654774 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-17mb/google/nautilus: Add MIPI camera asl files for IMX258 and DW9807Andy Yeh
* Add IMX258 sensor entity * Add DW9807 VCM control entity * Enable CIO2 and IMGu in devicetree.cb TEST: Verified the MIPI camera function on DUT board Change-Id: Iebd41ac3631829bbb0b008761eb67c3db3e94638 Signed-off-by: Andy Yeh <andy.yeh@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/23056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-01-12mb/google/poppy/variants/nautilus: enable digitizer pen deviceSeunghwan Kim
- Add pen device property into devicetree.cb. - Set GPP_C9 to 0 as default. BUG=none BRANCH=master TEST=emerge-nautilus coreboot and check pen device operation Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Change-Id: I050671c8b46fd92b1dd9164be2646727cd67da9f Reviewed-on: https://review.coreboot.org/23010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-22soc/intel/skylake: Add PcieRpClkSrcNumber UPD configuartion supportDivya Chellap
New UPD PcieRpClkSrcNumber introduced in FSP V2.9.2 to configure clock source number of PCIe root ports. This UPD array is set to clock source number(0-6) for all the enabled PCIe root ports, invalid(0x1F) is set for disabled PCIe root ports. BUG=b:70252901 BRANCH=None TEST= Perform the following 1. Build and boot soraka 2. Verify PCIe devices list using lspci command 3. Perform Basic Assurance Test(BAT) on soraka Change-Id: I95ca0d893338100b7e4d7d0b76c076ed7e2b040e Signed-off-by: Divya Chellap <divya.chellappa@intel.com> Reviewed-on: https://review.coreboot.org/22947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-20mb/google/poppy/variants/nautilus: Change USB2 phy settingsh.kim
In order to pass USB2 eye diagram, some USB2 port PHY registers needs to be changed. Port1 (Type-A): USB2_PORT_SHORT Port2 (BT): USB2_PORT_SHORT Port6 (H1): USB2_PORT_SHORT Port7 (Camera): USB2_PORT_SHORT BUG=none BRANCH=master TEST=emerge-nautilus coreboot and do eye-diagram test Signed-off-by: sh.kim <sh_.kim@samsung.com> Change-Id: I174e5bf96a53bb210481fb88298d5341f6c11dec Reviewed-on: https://review.coreboot.org/22686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-19mb/google/poppy/variants/nautilus: Enable AER and LTR for root port 1Furquan Shaikh
Similar to other KBL projects, this change enables AER and LTR for root port 1 on poppy. BUG=b:65570878 Change-Id: Iadad3d2fc46cbba575a776071305925c529a6760 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/22923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-11google/nautilus: Add Maxim98357a supportNaveen Manohar
Adds Maxim98357a support for Nautilus using the generic driver in drivers/generic/max98357 BUG=b:68686020 TEST=With entire merged audio should be enabled on max98357 speaker codec. Change-Id: I958bf7c1395259b3e3fb30332882fd51a48dc0cc Signed-off-by: Naveen Manohar <naveen.m@intel.com> Reviewed-on: https://review.coreboot.org/22458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-05mb/google/poppy,nautilus,soraka: Disable PD on AC_PRESENT in deep SxFurquan Shaikh
This change updates device tree deep_sx_config to disable internal pull-down on AC_PRESENT. BUG=b:69983729 Change-Id: I041900a5262f8fd920856f126185329242a0639a Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-30mb/google/poppy/variants/nautilus: Disable DPTFFurquan Shaikh
This change disables DPTF until the support is properly added in dptf.asl Change-Id: I68f2442e00718a4edbb34661d31d3a415d41c29f Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-11-30mb/google/nautilus: add synaptics touch screen supportChris Wang
Add synaptics touchscreen in the device tree so that the correct ACPI device is created. BUG=b:66462881 BRANCH=master TEST=compiled/verify the touchscreen works Change-Id: I6e89a5db0e9f8ae777eed661f3bf89d653a937e6 Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/22613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-29mb/google/poppy/variants/nautilus: Disable camera devicesFurquan Shaikh
This change disables camera devices until camera support is properly added for nautilus. Change-Id: I7de37cbf9c32fa063f55a2e54986e33b66acfa3b Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-28mb/google/poppy/variants/nautilus: set I2C speed to 400KHzChris Wang
Add "speed_config" for each I2C port configuration to set speed to 400KHz. BRANCH=master BUG=none TEST=compiled/verified Change-Id: Icb48733b87cefc92577547b1eab661a8cbb12be6 Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/22589 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-28mb/google/poppy/variants/nautilus: Change IA/GT/SA slow slew rate settingsChris Wang
Change IA/GT/SA slow slew rate settings. System's audible noise will be reduced with them. - Slow slew rate for IA/GT/SA : fast/16 - Fast PKG C-state ramp for IA/GT/SA: disabled BRANCH=master BUG=none TEST=compiled/verified Change-Id: Ibf11aba7bafb3b02c510905d7d904507eee6394b Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/22588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: shkim <sh_.kim@samsung.com>
2017-11-09mb/google/{poppy,nautilus,soraka}: Disable deep S3Furquan Shaikh
Poppy and variants won't be using deep S3. This change disables deep S3 option in devicetree. BUG=b:69053636 Change-Id: I5fb4a6a0e4216a3648b5ed888f6dc6618f1a9fc4 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22378 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-07mb/google/poppy/variants/nautilus: Enable Dialog DA7219 supportNaveen Manohar
Enable Dialog DA7219 codec i2c device and add required SSDT parameters BUG=b:68686020 TEST=With req'd driver support in kernel v4.4 verify audio on headset Change-Id: Ic815c929f29bec0d26a2981e9933b752c2d84c70 Signed-off-by: Naveen Manohar <naveen.m@intel.com> Signed-off-by: Shruthi Sudhakar <shruthi.sudhakar@intel.com> Reviewed-on: https://review.coreboot.org/22264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-03google/nautilus: enable elan touchpad supportChris Wang
add elan touchpad in devicetree. BRANCH=master BUG=b:66462881 TEST=emerge-nautilus coreboot Change-Id: I30e6797ef06351690ff0b5c78ea76918547167a7 Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/22187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: shkim <sh_.kim@samsung.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-10-10mb/google/poppy/variants/nautilus: add nautilus boardChris Wang
Create Nautilus board which derives from Poppy, a KBL reference board. BRANCH=master BUG=b:66462881 TEST=Build (as initial setup) Change-Id: I6ca5ab821a7ba1746b37dfd3ea1ed367094d4f52 Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/21895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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