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2017-07-28mb/google/soraka: configure GPP_B8 to control WLAN_PE_RSTRizwan Qureshi
WLAN_PE_RST control was moved from EC to SoC, it connected to GPP_B8. Configure GPP_B8 to drive low. TEST=Wifi card is detected and connect to an AP. Change-Id: I6a6ea0ddefe8402284fe37665864c7a1961cbc15 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/20804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-27mainboard/google/poppy: Configure GPIO.1 and GPIO.2 for daisy chain modeV Sowmya
Configure GPIO.1 and GPIO.2 as sensor SDA and SCL respectively for TPS68470 PMIC in daisy chain mode. * GPIO.1: Sensor SDA in daisy chain mode. * GPIO.2: Sensor SCL in daisy chain mode. BUG=b:38326541 BRANCH=none TEST=Build and boot soraka. Dump and verify that the generated DSDT table has the required entries. Verified that sensor probe is successful. Change-Id: I7f9686427772a33c06e4cdaafee9b0349d700639 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/20665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-24mainboard/google/soraka: pull high TOUCHSCREEN_STOP_L pinWisley Chen
After updating to Wacom Firmware version 501, touchscreen can't work. Wacom FW (ver. 501) enables STOP function. STOP Pin: High: Normal Operation Low: Stop Scanning So pull TOUCHSCREEN_STOP_L high BUG=b:37007801, b:37265219 BRANCH=none TEST=manual testing on Soraka board and touchscreen works at boot and after suspend/resume. Change-Id: I8a2bdce1554fd99dea30cf91fa48d0529f40b7b0 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/20664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-23mainboard/google/{poppy,soraka}: Enable S0ixRajat Jain
Enable S0ix for poppy and soraka in their device trees respectively. BUG=b:36630881 BRANCH=none TEST=Verified S0ix and S3 operation on Poppy and Soraka (250+ iterations). Change-Id: I9ba91499e54f729970448af6f71804ad5b3cb836 Signed-off-by: Rajat Jain <rajatja@google.com> Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-22mainboard/google/poppy/variants/soraka: Update GPP_{D1,D2,B7} configFurquan Shaikh
GPP_B7, GPP_D1 and GPP_D2 are not used going forward. Mark them as NC in gpio table. BUG=b:62322846,b:62240755 Change-Id: I7aee08314e6ce96d5913ae315bf75f5c04ab7370 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20672 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-22mainboard/google/poppy/variants/soraka: Define separate gpio tablesFurquan Shaikh
Now that soraka is starting to deviate from the baseboard w.r.t. gpio settings, make a new copy of gpio table before we make any variant-specific changes in it. BUG=b:62240755,b:62322846 BRANCH=None TEST=Verified with gpio_debug=1 in skylake/gpio.c that the gpio configuration before and after this change remains same. Change-Id: I448d18f18b63e9bfb739c518d599de3b9b602dc2 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-13mainboard/google/soraka: add wacom touchscreen supportWisley Chen
Add wacom touchscreen support. BUG=b:37007801, b:37265219 BRANCH=None TEST=manual testing on Soraka board to ensue that touchscreen works at boot and after suspend/resume. Change-Id: I0fbae4782c6442149cda57d23c61ed87546621bb Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/20476 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-12mb/google/soraka: Do not reset PMIC during sleepNaresh G Solanki
1. Due to reset signal, PMIC loses its internal register state. This causes PMIC to be in improper state after sleep. 2. The intent of reset signal is to reset internal state of PMIC (which happens once during power on), hence avoid asserting reset signal when not needed. 3. As per PMIC (TPS68470) datasheet, device can be kept in SLEEP mode when not in use to save max possible power. To fix the same, do not reset PMIC while entering sleep. By keeping PMIC in SLEEP mode, Power consumption is < 1uW (Typ) upto 3.63uW (Max). Refs: TPS68470 datasheet. Measured value: 0.66uW TEST= Build the firmware for Soraka & boot to OS. Do S3 resume & check whether PMIC internal registers state are preserved. Change-Id: I93ce4d76b0376b64ae6d1067aca0fd7467af3582 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/20264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-01mainboards: Remove unused EC event for thermal overloadDuncan Laurie
The Chrome EC event for "thermal overload" was never implemented and is being repurposed as the EC event mask is out of free bits. Remove this from the boards that were enabling it. BUG=b:36024430 TEST=build coreboot for affected boards Change-Id: I6038389ad73cef8a57aec5041bbb9dea98ed2b6e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/20424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-27mainboard/google/soraka: Update VR config settingsRajneesh Bhardwaj
Update Psi2Threshold, IccMax, AcLoadline, DcLoadline VR config settings as per board design. BUG=b:62063434 BRANCH=none TEST=Build and boot soraka. Change-Id: I254bbb88b82ddf278f0ec71bc98873df1d5e0d27 Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Signed-off-by: G Naveen <naveen.g@intel.com> Reviewed-on: https://review.coreboot.org/20309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-27mb/google/soraka: Remove MPS IMVP8 workaroundRajneesh Bhardwaj
Soraka uses MPS2949 IMVP8 controller and does not need the VR workaroud similar to Eve. BUG=None TEST=Build & boot on soraka. Ensure IMVP8 controller goes to low power mode in S3 and S0ix by measuring power. Change-Id: Ib98bb709ecc9e362a5cef437e7319e41f398a73b Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Reviewed-on: https://review.coreboot.org/20255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-27mainboard/google/poppy: Update world facing camera sensorV Sowmya
Update the world facing camera sensor to OV13858 and also add delay of 5ms after xshutdown rising which indicates system ready status. BUG=b:38326541 BRANCH=none TEST=Build and boot soraka. Dump and verify that the generated DSDT table has the required entries. Verified that sensor probe is successfull. Change-Id: I0cd535e6568f104ffaa1092a13667def646df0eb Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/20292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2017-06-27mainboard/google/poppy: Add clock frequency for camera sensorsV Sowmya
Add clock frequency property into _DSD ACPI object and set it to 19.2MHz for camera sensors. Upstream camera kernel has added a check for clock frequency in sensor probe function and without this property sensor probe fails. BUG=b:38326541 BRANCH=none TEST=Build and boot poppy. Dump and verify that the generated DSDT table has the required entries. Verified that sensor probe is successfull. Change-Id: I147b3c932a33ae034868f7f9b616500d24ca71e3 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/20294 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2017-06-20mb/google/poppy: Add camera devices power sequencing through ACPI power ↵V Sowmya
resources This patch controls the camera devices power through ACPI power resource. * Add Opregions for PMIC, * TI_PMIC_POWER_OPREGION * TI_PMIC_VR_VAL_OPREGION * TI_PMIC_CLK_OPREGION * TI_PMIC_CLK_FREQ_OPREGION * Add power resources for sensors and VCM, * OVTH for CAM0 * OVFI for CAM1 * VCMP for VCM * Implement _ON and _OFF methods for sensor and VCM module's power on and power off sequences. BUG=b:38326541 BRANCH=none TEST=Build and boot poppy. Dump and verify that the generated DSDT table has the required entries. Change-Id: I87cd0508ed5ed922211a51f43ee96b6f44cf673d Signed-off-by: V Sowmya <v.sowmya@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/20054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-20mb/google/poppy: Configure ports and endpoints for sensor and CIO2 devicesV Sowmya
Bind the camera sensor and CIO2 devices through the ports and endpoints configuration available in _DSD ACPI object. * Port represents an interface in a device. * Endpoint represents a connection to that interface. BUG=b:38326541 BRANCH=none TEST=Build and boot poppy. Dump and verify that the generated DSDT table has the required entries. Change-Id: I6d822165bb9a0cd6f7d4cdcb36333887953110a3 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/20053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-19mb/google/poppy: Add MIPI camera support.V Sowmya
This patch adds mipi_camera.asl, * Add TPS68470 PMIC related ACPI objects. * Add OV cameras related ACPI objects. * Add Dongwoon AF DAC related ACPI objects. * SSDB: Sensor specific database for camera sensor. * CAMD: ACPI object to specify the camera device type. BUG=b:38326541 BRANCH=none TEST=Build and boot poppy. Dump and verify that the generated DSDT table has the required entries. Change-Id: If32a2a8313488d2f50aad3feaa79e17b1d06c80f Signed-off-by: V Sowmya <v.sowmya@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/19621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-19mainboard/google/{poppy,soraka}: Remove MIPI camera support from devicetree.cbV Sowmya
Remove MIPI camera related register entries from devicetree.cb. BUG=b:38326541 BRANCH=none TEST=Build and boot poppy and soraka. Change-Id: Ic6a6a98d4c8ed6cba760eae5fd87bc2a3f15d7d2 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/19619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-19mb/google/poppy: Add option to disable TPMNaresh G Solanki
Disable TPM when VBOOT_MOCK_SECDATA is enabled. BUG=None BRANCH=None TEST= Build image using USE="mocktpm" emerge-poppy coreboot depthcharge vboot_reference chromeos-bootimage . Verify boot is successful with mock tpm. Change-Id: Iee527ed17cffb7d25d9089e48a194d99ac8c3cd1 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/20158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-14mainboard/google/{poppy,soraka}: Disable unused GSPI1 interfaceFurquan Shaikh
TEST=Verified that board still boots to OS without any error. Change-Id: I02d2a6cbcab92766a35993bfd20aaeed4ca22c90 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-14mainboard/google/{poppy,soraka}: Enable generation of SPI TPM ACPI nodeFurquan Shaikh
Now that we dynamically disable TPM interface based on config options, add support for generation of SPI TPM ACPI node if SPI TPM is used. Change-Id: I87d28a42b48ba916c70e45a061c5efd91a8a59bf Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-14mainboard/google/poppy: Disable unused TPM interface dynamicallyFurquan Shaikh
Based on the config options selected, decide at runtime which TPM interface should be disabled so that ACPI tables are not generated for that interface. TEST=Verified that unused interface does not show up in ACPI tables. Change-Id: Iee8f49e484ed024c549f60c88d874c08873b75cb Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20141 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-06-09mb/google/soraka: Update UF camera i2c addressNaresh G Solanki
Update user facing camera i2c address to 0x36. BUG=None TEST=Build & boot on soraka. Make sure user facing camera is detected. Change-Id: I4645ae5734faef4b6a821c04ab817a7b99da6e4b Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/20023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
2017-06-07mainboard/google/poppy: Add support for ELAN deviceFurquan Shaikh
Add support for ELAN 5515 device. BUG=b:62331218 Change-Id: Id91a41743330c9e356293cfda7b2e3743dcd480c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20040 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-04mb/google/poppy: Update camera sensorNaresh G Solanki
Update camera sensor detail to OV 13858 Also update i2c address of OV5670 BUG=None TEST= Build & boot to ChromeOS. Check for both the camera detection. Change-Id: I3b6192815201f605d3ebdb4bf54db26a8e837b35 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/20021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-01mainboard/google/poppy: Enable H1 I2C TPMFurquan Shaikh
Enable H1 I2C TPM in Kconfig and devicetree for poppy. CQ-DEPEND=CL:513513,CL:*381534 BUG=b:36265511 BRANCH=None TEST=Compiles successfully. Change-Id: I4c6c94fa05abf9f5374505ded5956e879ac79726 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicolas Boichat <drinkcat@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-31mainboard/google/poppy: Power down camera rails when suspendingFurquan Shaikh
BUG=b:62147763 Change-Id: Iba88fed972b847448e01fcfca8c7129d950244c2 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-26mainboard/google/poppy: Add PowerResource for touchscreen deviceFurquan Shaikh
1. Do not enable touchscreen device by default in gpio configuration. 2. Select use of PowerResource for touchscreen device in devicetree so that the ACPI subsystem can take care of powering on/off the device. When system enters suspend, touchscreen device is powered off and on resume, it is powered back on. BUG=b:62028489 TEST=Verified 100 cycles of suspend-resume. Touchscreen still works on poppy. Change-Id: Ia0bebc7259b10cc60a9fa5b53542dfdd9685663e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19829 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-24mb/google/soraka: Update camera sensor for sorakaNaresh G Solanki
Soraka uses OV 13858 sensor. Hence update the same. Change-Id: I4dd39a25da47e379cca3f8748250b3ce1ff61e50 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/19639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-05-24mb/google/poppy: Update SPD dataNaresh G Solanki
Though SPD is rightly selected (i.e., H9CCNNNBKTALBR-NUD), it displays wrong part number during boot in coreboot logs. So correct part number info within the SPD. TEST= Build for Soraka & make sure part number is rightly printed. Change-Id: I67f676fb6ee9d685fa7aa41fdc4b00355e6d33c7 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/19692 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-19mainboard/google/poppy/variants/soraka: Add SPD for K3QFAFA0CM-AGCFFurquan Shaikh
BUG=b:37712455 Change-Id: Ia3d13ac7c18be8fa92603b6501a2e5df476adcf0 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19766 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-19mainboard/google/poppy: Fix SPD for micron MT52L256M64D2PP-107Furquan Shaikh
Fix SPD as per the vendor-provided data. BUG=b:37712790 Change-Id: Ib87c316479f4a05e64ca4acb540d7aacfa7338e9 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-17mainboard/google/poppy/variants/soraka: Enable H1 I2C TPMFurquan Shaikh
1. Add a separate devicetree file for soraka variant and add H1 node. 2. Enable H1 TPM for soraka. BUG=b:36265511 Change-Id: Id9947dce9b7f755971f0199f043af8d251d275ab Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19519 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
2017-05-17mainboard/google/poppy: Correct I2C bus number for TPMFurquan Shaikh
TPM is on I2C bus 1. Fix that. BUG=b:36265511 Change-Id: I7fb696ca7281a0c099dd325d794dd4551cf20a53 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19710 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-05mb/google/poppy: Add eMMC as thermal sensorSumeet Pawnikar
This patch adds the eMMC as one of the thermal sensor under DPTF. Also, updates few comments for better interpretation and mapping. BUG=None BRANCH=None TEST=Built for poppy. Change-Id: I6d05bb7a2f857dc5bc98227c8327b2ff1bd5b913 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/19524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-05-05mainboard/google/poppy: Enable MODE_CHANGE event in SCI_MASKFurquan Shaikh
This is required to ensure that SCI is generated whenever a host event is set for MODE_CHANGE. Thus, when wake from MODE_CHANGE event occurs, eSPI SCI is generated which results in kernel handler reading host event from the EC and thus causes the wake pin to be de-asserted. BUG=b:37223093 TEST=Verified that wake from mode change event works fine in suspend mode and there is no interrupt storm for GPE SCI after resume. Change-Id: I1dd158ea0e302d5be9bcaa531cd1851082ba59fd Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jenny Tc <jenny.tc@intel.com>
2017-05-03mainboard/google/poppy: Add support for cr50 I2C TPMFurquan Shaikh
1. Add support for using cr50 I2C TPM on poppy. This will not be enabled until the next build. 2. Also, configure GPIOs for SPI and I2C TPM only if the corresponding Kconfig options are set. BUG=b:36265511 TEST=Verified on a reworked board that I2C TPM communication works fine. Change-Id: I3b293b8d410a6973a6dfea393c17d0be425b6a28 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-03mainboard/google/poppy: Update GPIO table for next buildFurquan Shaikh
Update GPIO table to match the schematics for next build. Change-Id: I949a14bfaa7972f2257a0b11ee81dcb0771e2f7f Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-04-28mainboard/google/soraka: Add support for memory configs 1,2,7 and 8Furquan Shaikh
BUG=b:37712455 Change-Id: I3209aaef774712edab5e9f656ee84bfb6917b1c1 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19472 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-04-28mainboard/google/poppy: Add SPDs for memory config 1 and 2Furquan Shaikh
BUG=b:37712790 Change-Id: I7764b4ec55b0beea82eeb6c379ef38ceeb1fb04e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19471 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-28mainboard/google/poppy: Enable separate MRC cache for recovery modeFurquan Shaikh
Enable separate MRC cache for recovery mode. This requires change in flash layout to accomodate another region for RECOVERY_MRC_CACHE. BUG=b:37682566 TEST=Verified following scenarios: 1. Boot into recovery does not destroy normal mode MRC cache. 2. Once recovery MRC cache is populated, all future boots in recovery mode re-use data from the cache. 3. Forcing recovery mode to retrain memory causes normal mode to retrain memory as well. Change-Id: I4c748a316436001c5a33754084ab4a74243e21df Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19457 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-27google/poppy: Enable PD MCU deviceShamile Khan
In order for PD charge events to properly notify the OS when a charger is attached we need to enable the PD MCU device and event source from the EC. Without this change the charging still happens, but the OS does not notice and update the charge state icon in the Chrome OS UI. BUG=b:35586577 BRANCH=none TEST=On a poppy board that has the VBUS rework applied, plug in a charger to either port and see charge status updated to indicate charging in the power_supply_info tool and the Chrome OS UI. Change-Id: I59dcfc1cb5d11841f56cac7f4ffe461c2f9ec52a Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/19441 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
2017-04-24mainboard/google/poppy: use intel common tis_plat_irq_status()Aaron Durbin
Utilize the intel/common code for tis_plat_irq_status() to remove dependencies and code duplication on for bringing up a board requiring tis_plat_irq_status(). Change-Id: I2aaa1d7d3ce171dc1788438ff9990fce533deb6c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19371 Tested-by: build bot (Jenkins)
2017-04-24Kconfig: provide MAINBOARD_HAS_TPM_CR50 optionAaron Durbin
The CR50 TPM can do both SPI and I2C communication. However, there's situations where policy needs to be applied for CR50 generically regardless of the I/O transport. Therefore add MAINBOARD_HAS_TPM_CR50 to encompass that. Additionally, once the mainboard has selected CR50 TPM automatically select MAINBOARD_HAS_TPM2 since CR50 TPM is TPM 2.0. Change-Id: I878f9b9dc99cfb0252d6fef7fc020fa3d391fcec Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19370 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2017-04-19mainboard/google/poppy/variants/soraka: add soraka boardYH Lin
Create Soraka board which derives from Poppy, a KBL reference board. More Soraka specific changes need to be done later on. BRANCH=master BUG=b:36995255 TEST=Build (as initial setup) Change-Id: I8af68d2cf475df56336aa0e3bebe86a54ece1999 Signed-off-by: YH Lin <yueherngl@chromium.org> Reviewed-on: https://review.coreboot.org/19343 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-19mainboard/google/poppy: Provide nhlt variant APIFurquan Shaikh
Move current NHLT configuration implementation to baseboard so that variants can leverage it or provide their own configuration. BUG=b:37375693 Change-Id: I2a4317c112f9e3614bd01eb6809727b73328d29d Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19326 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-19mainboard/google/poppy: Provide memory configuration variant APIFurquan Shaikh
Add support for memory configuration by providing weak implementation from the baseboard. All SPD files are present under spd/ directory. SPD_SOURCES must be provided by the variants to ensure that required SPD hex files are included in the SPD binary. BUG=b:37375693 Change-Id: Ic9bcc03d5a35bebd14061680f264ac072b3c0634 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19325 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-19mainboard/google/poppy: Provide cros_gpio variant APIFurquan Shaikh
Add support for ChromeOS GPIO ACPI table information by providing weak implementation from the baseboard. BUG=b:37375693 Change-Id: I641afe6bb45f106ddebde081a8ac2c64278ebeb9 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19324 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-19mainboard/google/poppy: Add variant API for board_id and gpioFurquan Shaikh
Provide APIs for board_id() and gpio table functionality. Default weak implementations are provided from the baseboard. BUG=b:37375693 Change-Id: Ic3c946e6cb12b3c8ef3e83a1037ed0fc8cffbded Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19323 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-19mainboard/google/poppy: Provide baseboard and variant conceptsFurquan Shaikh
In order to be able to share code across different poppy variants, provide the concept of baseboard and variants. New directory layout: variants/baseboard - code variants/baseboard/include/baseboard - headers variants/poppy - code variants/poppy/include/variant - headers New boards would then add themselves under their board name within "variants" directory. This is purely an organizational change. BUG=b:37375693 Change-Id: If6c1c5f479cfffe768abf27495d379744104e2dc Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19322 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-19mainboard/google/poppy: Prepare sharing directory for variantsFurquan Shaikh
Clean up Kconfig file in order to support variants for poppy. Add BOARD_GOOGLE_BASEBOARD_POPPY that can be set by various poppy variants to use the common baseboard configs. BUG=b:37375693 Change-Id: I399ecc8c3efb3af26e1fcf60fe2c75b24769fc0f Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19321 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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