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Add VBT file, and override use via Kconfig since all Reef variants
use the same VBT file.
VBT extracted from firmware in ChromeOS recovery image.
Test: built/boot google/reef w/FSP display init
Change-Id: I31156ec7371c0443719fdd9ddac6ed4960c83767
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add a FMAP which supports SMMSTORE and non-ChromeOS payloads,
since Apollo Lake-based devices like Reef cannot use an
automatically-generated FMAP due to strict layout requirements.
Change-Id: If570f92f4f81c0e29777c87756fc5e45af549064
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Kconfig became stricter on what it accepts, so accomodate before
updating to a new release.
Change-Id: I92a9e9bf0d557a7532ba533cd7776c48f2488f91
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The CONFIG_GBB_HWID can be generated automatically now so we can remove
the test-only HWIDs set in board config files.
BUG=b:140067412
TEST=Built few boards (kukui, cheza, octopus) and checked HWID:
futility gbb -g coreboot.rom
Change-Id: I4070f09d29c5601dff1587fed8c60714eb2558b7
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35635
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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After f5ca922 (Untangle CBFS microcode updates) got merged, all
mainboard using intel apollolake, cannonlake, coffeelake, glk,
kabylake, skylake, icelake and whiskeylake get affected.
Using INTEL_LPSS_UART_FOR_CONSOLE instead of UART_DEBUG
and set default console for each platform.
BUG=N/A
TEST=Build and test on Sarien platform, by default we can still get
console from cbmem, and enable CONSOLE_SERIAL can get logs from UART
port 2.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I550a00144cff21420537bb161c64e7a132c5d2de
Reviewed-on: https://review.coreboot.org/c/30853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Until now, chromeec was doing keyboard initialization for the boards
that have DRIVERS_PS2_KEYBOARD selected. However, coreboot does not
leave the keyboard controller in a default reset state. This could
result in payloads or OS failing to probe the controller as there
could be stale data buffered in the controller during the handoff.
Since the boards using chromeec already perform keyboard
initialization in payload, there is no need to initialize the keyboard
in coreboot too. This change gets rid of DRIVERS_PS2_KEYBOARD
selection from all google mainboards using chromeec.
BUG=b:110024487
TEST=Keyboard works fine after booting to OS even if user hits keys
during BIOS to OS handoff.
Change-Id: I1f49b060eb005c0f2b86f9d68d6758954eeb3cf0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27291
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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* Remove 2nd software stack in pc80 drivers directory.
* Create TSPI interface for common usage.
* Refactor TSS / TIS code base.
* Add vendor tss (Cr50) directory.
* Change kconfig options for TPM to TPM1.
* Add user / board configuration with:
* MAINBOARD_HAS_*_TPM # * BUS driver
* MAINBOARD_HAS_TPM1 or MAINBOARD_HAS_TPM2
* Add kconfig TPM user selection (e.g. pluggable TPMs)
* Fix existing headers and function calls.
* Fix vboot for interface usage and antirollback mode.
Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/24903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Instead of duplicating code across multiple mainboards, use newly
added helper function to read boardid from Chrome EC.
Change-Id: I1671c0a0b87d0c4c45da5340e8f17a4a798317ca
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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It is a copy from baseboard/devicetree.cb (coreboot.org ToT)
BUG=b:64880573
BRANCH=master
TEST=emerge-coral coreboot chromeos-bootimage
Change-Id: I5db730c1974a96547fe7fda63689b7c5bfaefc66
Signed-off-by: Tim Chen <Tim-Chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/21130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch assigns the code of coral family, such that,
the 'mosys platform family' returns 'Google_Coral'.
BUG=b:64467244, b:64501879
BRANCH=none
TEST=Examine 'mosys platform family' w/ new firmware.
Change-Id: I1d8f8ca2166a1d80855608cf5b64b0cc7bf3dc93
Signed-off-by: Harry Pan <harry.pan@intel.com>
Reviewed-on: https://review.coreboot.org/21136
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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A new variant copied from reef.
Allow override of the SKU.
Change-Id: Ibe160e75aa23623812f0fb9121d1d8226afc00d8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/20020
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable SAR and DSAR for reef.
BUG=b:37612675
TEST=`emerge-reef coreboot`
Change-Id: Ie0a59f8fcc9fb104328ee6d276ecab4193ec8eb8
Signed-off-by: Wei-Ning Huang <wnhuang@google.com>
Reviewed-on: https://review.coreboot.org/19579
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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DRIVER_TPM_I2C_IRQ has been removed. TPM_TIS_ACPI_INTERRUPT now specifies
the TPM2 ACPI interrupt used by intel's tis_plat_irq_status() routine.
BRANCH=none
BUG=b:36786804
TEST=Boot reef w/ serial enabled firmware, verify verstage sees
"cr50 TPM".
Change-Id: If66a2a1d461a411e112589c84a434066d48b9399
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/19410
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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TPM_TIS_ACPI_INTERRUPT specifies the TPM2 ACPI interrupt used by intel's
tis_plat_irq_status() routine.
BRANCH=none
BUG=b:36786804
TEST=Boot reef w/ serial enabled firmware, verify verstage sees
"cr50 TPM".
Change-Id: Ic69add8a3ce35be64fb37db4ed40163f6144fc9c
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/19408
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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The CR50 TPM can do both SPI and I2C communication. However,
there's situations where policy needs to be applied for CR50
generically regardless of the I/O transport. Therefore add
MAINBOARD_HAS_TPM_CR50 to encompass that. Additionally,
once the mainboard has selected CR50 TPM automatically select
MAINBOARD_HAS_TPM2 since CR50 TPM is TPM 2.0.
Change-Id: I878f9b9dc99cfb0252d6fef7fc020fa3d391fcec
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19370
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
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This patch attempts to finish the separation between CONFIG_VBOOT and
CONFIG_CHROMEOS by moving the remaining options and code (including
image generation code for things like FWID and GBB flags, which are
intrinsic to vboot itself) from src/vendorcode/google/chromeos to
src/vboot. Also taking this opportunity to namespace all VBOOT Kconfig
options, and clean up menuconfig visibility for them (i.e. some options
were visible even though they were tied to the hardware while others
were invisible even though it might make sense to change them).
CQ-DEPEND=CL:459088
Change-Id: I3e2e31150ebf5a96b6fe507ebeb53a41ecf88122
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18984
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Create the initial Nasher variant which refers to the Reef.
Nasher is APL board that derives from reference board Reef.
BRANCH=master
BUG=b:36389286
TEST=Build (as initial setup)
Signed-off-by: YH Lin <yueherngl@chromium.org>
Change-Id: I7962aa8246890149988c7f02dcd90d820df7b901
Reviewed-on: https://review.coreboot.org/18928
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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It is a copy from baseboard/devicetree.cb (coreboot.org ToT)
BUG=b:35775065
BRANCH=reef
TEST=emerge-sand coreboot
Change-Id: I5ba86e54ccfbf5af7bf0e9ad8fe7bf22020e48ee
Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com>
Reviewed-on: https://review.coreboot.org/18703
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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verstage can be pretty chatty so bump the pre cbmem console size
when building for Chrome OS so that all messages can be observed.
BUG=b:35775104
BRANCH=reef
TEST=Booted and noted no cutoff of console when sec data being saved.
Change-Id: I0ce2976572dedf976f051c74a3014d282c3c5f4c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/18679
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Wacom I2C driver does the same thing as I2C HID driver, other than
defining macros for Wacom HID. Instead of maintaining two separate
drivers providing the same functionality, update all wacom devices to
use generic I2C HID driver.
BUG=None
BRANCH=None
TEST=Verified that ACPI nodes for wacom devices are unchanged.
Change-Id: Ibb3226d1f3934f5c3c5d98b939756775d11b792c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18401
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Change config option selection from "config xyz default y" to "select
xyz" if the config option has no dependencies.
BUG=None
BRANCH=None
TEST=Verified that config option selection remains unchanged.
Change-Id: I259ae40623b7f4d5589e2caa0988419ba4fefda4
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18400
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Since we are not using gpio regulators on reef anymore, remove the
selection from Kconfig as well.
BUG=None
BRANCH=None
TEST=Compiles successfully.
Change-Id: Iae7d88dec3ac476d65b292f97a6ba3add71ce07a
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18399
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Create the initial Sand variant which refers to the Reef.
Sand is APL board that derives from reference board Reef.
BRANCH=master
BUG=chrome-os-partner:62200
TEST=Build (as initial setup)
Signed-off-by: YH Lin <yueherngl@chromium.org>
Change-Id: Iba8c5653b6176676c759d2b48063f0c0c6cde625
Reviewed-on: https://review.coreboot.org/18324
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Apollolake boards should use DMIC-4ch configuration in Kernel side and
use CaptureChannelMap in userspace to distinguish boards with different
number of DMIC's. So, NHLT DMIC 1-ch & 2-ch endpoint configuration will
not be required and hence removed.
BUG=chrome-os-partner:60827
TEST=Verify internal mic capture
TEST='arecord -Dhw:0,3 dmic_4ch.wav -f S16_LE -r 48000 -c 4 -d 10' works
Change-Id: Ibe81290906c9e379ae49e437648ee9cd6f123ff8
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/18252
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Add weida touchscreen as 2nd touchscreen source
BUG=chrome-os-partner:61865
BRANCH=reef
TEST=emerge-snappy coreboot, and verified that touchscreen works on
snappy.
Change-Id: If76312a62e97da9d5de18ad895e90ee6b0f0c6ae
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/18166
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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ELAN touchscreen device expects firmware to export GPIOs and ACPI
regulators for managing power to the device. Thus, provide the
required ACPI elements for OS driver to properly manage this device.
BUG=chrome-os-partner:60194
BRANCH=None
TEST=Verified that touchscreen works properly on boot-up and after
suspend/resume.
Change-Id: I298ca5de9c0ae302309d87e3dffb65f9be1e882e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17799
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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For Chrome OS the normal MRC cache should be cleared when a hardware
retrain recovery request is observed. The reason is that since there
are 2 different MRC cache slots there needs to be a mechanism which
allows an end user make a system bootable again if the MRC settings
happen to not allow the system to boot any longer. Therefore, one
just needs to enter recovery with the hardware retrain flag and
the system normal MRC cache slot will be invalidated.
BUG=chrome-os-partner:60592
BRANCH=reef
Change-Id: I6ad32ed0dd217d66404b77467a88689a06044544
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17871
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Instead of defining the same functions for reading/clearing boot-mode
switches from EC in every mainboard, add a common infrastructure to
enable common functions for handling boot-mode switches if
GOOGLE_CHROMEEC is being used.
Only boards that were not moved to this new infrastructure are those
that do not use GOOGLE_CHROMEEC or which rely on some mainboard specific
mechanism for reading boot-mode switches.
BUG=None
BRANCH=None
TEST=abuild compiles all boards successfully with and without ChromeOS
option.
Change-Id: I267aadea9e616464563df04b51a668b877f0d578
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17449
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Reef board uses GPIO_17 as DMIC config pin.
This pin distinguishes board with Quad DMIC's or Mono DMIC.
This patch adds necessary DMIC endpoints to support either of
those configurations.
CQ-DEPEND=CL:*304339,CL:409774
BUG=chrome-os-partner:56918
BRANCH=none
TEST=Verify Mono and Quad Channel DMIC record
Change-Id: I5b2825b5f39f8962985a129f8ec65265fb18f0b2
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/17158
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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Wacom I2C driver can be used by devices other than
touchscreen. e.g. digitizer. So there is no need to name the driver
with touchscreen specific attributes. Only a separate descriptor name
is required that needs to be set by mainboard correctly.
BUG=chrome-os-partner:56246
BRANCH=None
TEST=Compiles successfully.
Change-Id: I0d32a4adae477373b3f4c5f3abbe188860701194
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17341
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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1. Add RECOVERY_MRC_CACHE region to reef FMAP.
2. Implement helper function for getting event for recovery mode with
memory retraining.
3. Select HAS_RECOVERY_MRC_CACHE.
BUG=chrome-os-partner:59352
BRANCH=None
TEST=Verified recovery mode behavior with and without memory training
request on reef.
Change-Id: I91abc9f8122f1aa3980c6372ab557e56a7a92730
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17243
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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BUG=chromium:663243
Change-Id: Ic78a6aac11a8e842911245c59e8ced7ed2c4e27a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17291
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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BUG=chrome-os-partner:57846
Change-Id: Ibd3ef8cebcf99ee2186dfed98b04373dd17e798e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17093
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
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Create the initial Snappy variant which refers to the Reef device.
Snappy, an Apollolake-platform, is deviated from reference board Reef.
BRANCH=master
BUG=None
TEST=Built & booted
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Change-Id: I6f32c0b1a154edbd8c4822acdbdbdbeb4a0098e6
Reviewed-on: https://review.coreboot.org/17043
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Create the initial Pyro variant which refers to the Reef.
Pyro is APL Chrome board that deviate from reference board Reef.
BRANCH=master
BUG=None
TEST=Build
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Change-Id: I9beed1f6895e8891d3d51b563edfe172f566718b
Reviewed-on: https://review.coreboot.org/16855
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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For all mainboard variants use the "Google_Reef" family by default
which is populated in SMBIOS tables. A variant can provide their own
value if needed, but "Google_Reef" can reside as the family without
having to add conditions for each variant when MAINBOARD_FAMILY
have to be overridden.
BUG=chrome-os-partner:56677
Change-Id: Ic214eae1e6473b32f4cb442c09c34355357e1257
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16813
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
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These default values weren't being set with the default
keyword so were ending up with different values.
from the default generated config file before this change:
CONFIG_DRIVER_TPM_I2C_BUS=0x9
CONFIG_DRIVER_TPM_I2C_ADDR=0x2
CONFIG_DRIVER_TPM_I2C_IRQ=-1
Change-Id: I19514d0c9b2a9b7e479f003a4d3384e073f4d531
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16828
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Enable the cr50 TPM and interrupt as GPE0_DW1_28 for use during
verstage. The interrupt is left in APIC mode as the GPE is
still latched when the GPIO is pulled low.
BUG=chrome-os-partner:53336
Change-Id: Ib0247653bdcbaccb645cd16b81d7ec3c38f669af
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16673
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This reverts commit 24de342438208d9b843e87627f15b9a272285b0f.
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Enable the cr50 TPM and interrupt as GPE0_DW1_28 for use during
verstage. The interrupt is left in APIC mode as the GPE is
still latched when the GPIO is pulled low.
BUG=chrome-os-partner:53336
Change-Id: I28ade5ee3bf08fa17d8cabf16287319480f03921
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
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Move the current devicetree.cb to be under variants/baseboard.
New variants can provide their own devicetree as needed.
BUG=chrome-os-partner:56677
Change-Id: Ib109ca4be883884b318264500d14aa8d40e3072a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16510
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Enable the I2C based TPM on the reef board at
bus 2 and address 0x50.
This makes vboot functional without needing MOCK_TPM and
results in the following in the SSDT:
Device (TPMI)
{
Name (_HID, "GOOG0005") // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
Name (_DDN, "I2C TPM") // _DDN: DOS Device Name
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
I2cSerialBus (0x0050, ControllerInitiated, 0x00061A80,
AddressingMode7Bit, "\\_SB.PCI0.I2C2",
0x00, ResourceConsumer)
Interrupt (ResourceConsumer, Edge, ActiveLow, Exclusive)
{
0x00000039
}
})
}
Change-Id: Ia9775caabeac3e6a3bd72de38f9611b4cea7cea4
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16398
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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To further the ability of multiple variant boards to share code
provide a place to land the split up changes. This patch provides
the tooling using a new Kconfig value, VARIANT_DIR, as well as
the Make plumbing. The directory layout with a single variant,
reef (which is also the baseboard), looks like this:
variants/baseboard - code
variants/baseboard/include/baseboard - headers
variants/reef - code
variants/reef/include/variant - headers
New boards would then add themselves under their board name
within the 'variants' directory.
No split has been done with providing different logic yet.
This is purely a organizational change.
BUG=chrome-os-partner:56677
Change-Id: Ib73a3c8a3729546257623171ef6d8fa7a9f16514
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16418
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Instead of completely duplicating the a reference board's directory
when doing a variant or follower device start providing a means to
share code within a single directory. This change just starts the
process from the Kconfig side, but subsequent patches will follow
which disentangles the board specific pieces from and common
logic.
BUG=chrome-os-partner:56677
Change-Id: I96628920d78012e488ec008e35daac9c1be0cf79
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16417
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Provide GBB's hardware ID (used on Chrome OS devices) because it will be
dropped from depthcharge.
BRANCH=none
BUG=none
TEST=none
Change-Id: I4851c1bdb21863983277d3283105c88b85a6166b
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 705251d2899bc006e21ff3e34a3fc3eba2dd4d00
Original-Change-Id: I7488533b83b8119f8c85cbf2c2eeddabb8e9487d
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/372579
Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16363
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Provide a default value of 0 in drivers/spi as there weren't
default values aside from specific mainboards and arch/x86.
Remove any default 0 values while noting to keep the option's
default to 0.
BUG=chrome-os-partner:56151
Change-Id: If9ef585e011a46b5cd152a03e41d545b36355a61
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16192
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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All the mainboards share the same config options for CHROMEOS. Instead
of duplicating those in every mainboard, move the CHROMEOS config to SoC
and make it dependent on MAINBOARD_HAS_CHROMEOS.
BUG=chrome-os-partner:55431
Change-Id: I2d54ff6beac9fca7596a8f104e3c1447cada5c05
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15821
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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This device has a built-in keyboard that should be enabled by default
or it will not work in firmware. This was tested to ensure that TAB
(display info) and Ctrl+D (enter developer mode) are functional at the
Chrome OS recovery screen.
BUG=chrome-os-partner:55549
Change-Id: I60156f1fc001b88deac69e03e02e9d8277fbc38d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15782
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The Chrome OS options that will be shipped on this platform were
being set in the chromium repo with an external config file. Set
the options in the mainboard Kconfig file so there's no discrepancy
as to what will be used.
Change-Id: I05f0d1245611c16f54273728519a08e6edff3429
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15733
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Use the device driver for DA7219 device configuration in the SSDT and
remove the static copy in the DSDT.
Tested on reef to ensure that the generated SSDT contents are
equivalent to the current DSDT contents.
Change-Id: I288eb05d0cb3f5310c4dca4aa1eab5a029f216af
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15539
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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