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path: root/src/mainboard/google/samus
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2015-08-21ChromeOS: Fix Kconfig dependenciesMartin Roth
Add CHROMEOS dependencies to selects for the following Kconfig symbols: CHROMEOS_RAMOOPS_DYNAMIC CHROMEOS_RAMOOPS_NON_ACPI CHROMEOS_VBNV_CMOS CHROMEOS_VBNV_EC CHROMEOS_VBNV_FLASH EC_SOFTWARE_SYNC LID_SWITCH RETURN_FROM_VERSTAGE SEPARATE_VERSTAGE VBOOT_DISABLE_DEV_ON_RECOVERY VBOOT_EC_SLOW_UPDATE VBOOT_OPROM_MATTERS VBOOT_STARTS_IN_BOOTBLOCK WIPEOUT_SUPPORTED This gets rid of these sorts of Kconfig errors: warning: BOARD_SPECIFIC_OPTIONS selects CHROMEOS_VBNV_EC which has unmet direct dependencies (MAINBOARD_HAS_CHROMEOS && CHROMEOS) Note: These two boards would never actually have CHROMEOS enabled: intel/emeraldlake2 has MAINBOARD_HAS_CHROMEOS commented out google/peach_pit doesn't have MAINBOARD_HAS_CHROMEOS Change-Id: I51b4ee326f082c6a656a813ee5772e9c34f5c343 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11272 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-30Add Kconfig flag to specify if there's a lid switchPatrick Georgi
Not all devices have a lid switch, so we need to state this somehow. Since the alternative would be to extend get_lid_switch()'s semantics to become a tri-state (open, closed, N/A), do this through Kconfig. BRANCH=none BUG=chromium:446945 TEST=none Change-Id: Icc50f72535f256051a59925a178fb27b2e8f7e55 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d20a1d1a22d64546a5d8761b18ab29732ec0b848 Original-Change-Id: Ie8ac401fbaad5b5a9f1dec2b67847c81f4cc94aa Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/273850 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Queue: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10692 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30Expose get_lid_switch() in romstagePatrick Georgi
The function was used locally and in ramstage to set some coreboot tables. It's also needed in romstage to deal with "lid closed" behaviour. BRANCH=none BUG=chromium:446945 TEST=none Change-Id: I8ad7061328c45803699321aa9f5edb0ed2288a8d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 78281a104fb9d79696a6ceb2a9a89a391146a424 Original-Change-Id: I56314b9dc9062dd61671982e7ec0ff15d7eb1bae Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/273609 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Queue: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10691 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-24Kconfig: Get rid of obsolete symbolsMartin Roth
CAR_MIGRATION was removed in commit: cbf5bdfe - CBMEM: Always select CAR_MIGRATION ALT_CBFS_LOAD_PAYLOAD was removed in commit: cf6c9cc2 - Kill ALT_CBFS_LOAD_PAYLOAD MARK_GRAPHICS_MEM_WRCOMB was removed in commit: 30fe6120 - MTRR: Mark all prefetchable resources as WRCOMB. EXTERNAL_MRC_BLOB was removed in commit: 0aede118 - Drop unused EXTERNAL_MRC_BLOB CACHE_ROM is only in Google's codebase. LID_SWITCH is only in Google's codebase. DEFAULT_POST_DEVICE_LPC is only in Sage's codebase. ROMSTAGE_RTC_INIT is only in Sage's codebase, or was never used. HUDSON_NOT_LEGACY_FREE never existed as far as I can tell. MAINBOARD_DO_EDID never existed as far as I can tell. Change-Id: I636ea7584fb47885638dbcd9ccedfafb1ca2c640 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10616 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-06-02cbfs: new API and better program loadingAaron Durbin
A new CBFS API is introduced to allow making CBFS access easier for providing multiple CBFS sources. That is achieved by decoupling the cbfs source from a CBFS file. A CBFS source is described by a descriptor. It contains the necessary properties for walking a CBFS to locate a file. The CBFS file is then decoupled from the CBFS descriptor in that it's no longer needed to access the contents of the file. All of this is accomplished using the regions infrastructure by repsenting CBFS sources and files as region_devices. Because region_devices can be chained together forming subregions this allows one to decouple a CBFS source from a file. This also allows one to provide CBFS files that came from other sources for payload and/or stage loading. The program loading takes advantage of those very properties by allowing multiple sources for locating a program. Because of this we can reduce the overhead of loading programs because it's all done in the common code paths. Only locating the program is per source. Change-Id: I339b84fce95f03d1dbb63a0f54a26be5eb07f7c8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9134 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-27Move TPM code out of chromeosVladimir Serbinenko
This code is not specific to ChromeOS and is useful outside of it. Like with small modifications it can be used to disable TPM altogether. Change-Id: I8c6baf0a1f7c67141f30101a132ea039b0d09819 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10269 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-05-19Move smi trap sample to documentation, don't keep it in every mobo.Vladimir Serbinenko
Sample code belongs to documentation, not copied 100x over prodcution code. Change-Id: I6bb318d76057d02bd6ac5641d12d56ab6d60b745 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10229 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-30intel/broadwell: Don't select MONOTONIC_TIMER_MSRPatrick Georgi
That's a Haswell exclusive, used nowhere else, but confusing when hunting for the monotonic timer used on that SoC. Change-Id: I60ec523e54e5af0d2a418bcb9145de452a3a4ea9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10034 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-28boards: remove VBOOT_(REFCODE|RAMSTAGE|ROMSTAGE)_INDEXAaron Durbin
These options will need to just be selected in within the .config files. There's not need in duplicating all these options. Change-Id: I7b670bc59a3b35e39eee4faecaf4aa779d47a3bb Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9959 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-22mainboards: Add CHROMEOS_VBNV_* where appropriatePatrick Georgi
For boards with MAINBOARD_HAS_CHROMEOS, we should also state what kind of storage is available for vboot's non-volatile data. The flags are taken from the chromium repository and have no effect with CHROMEOS disabled. Change-Id: I1747ad26c8c7f6d4076740ec2800dbd52c5d6b3d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9952 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-21Unify byte order macros and clrsetbitsJulius Werner
This patch removes quite a bit of code duplication between cpu_to_le32() and clrsetbits_le32() style macros on the different architectures. This also syncs those macros back up to the new write32(a, v) style IO accessor macros that are now used on ARM and ARM64. CQ-DEPEND=CL:254862 BRANCH=none BUG=chromium:444723 TEST=Compiled Cosmos, Daisy, Blaze, Falco, Pinky, Pit, Rambi, Ryu, Storm and Urara. Booted on Jerry. Tried to compare binary images... unfortunately something about the new macro notation makes the compiler evaluate it more efficiently (not recalculating the address between the read and the write), so this was of limited value. Change-Id: If8ab62912c952d68a67a0f71e82b038732cd1317 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fd43bf446581bfb84bec4f2ebb56b5de95971c3b Original-Change-Id: I7d301b5bb5ac0db7f5ff39e3adc2b28a1f402a72 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/254866 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9838 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-18kconfig: automatically include mainboardsStefan Reinauer
This change switches all mainboard vendors and mainboards to be autoincluded by Kconfig, rather than having to be mentioned explicitly. This means, vendor and mainboard directories are becoming more "drop in", e.g. be placed in the coreboot directory hierarchy without having to modify any higher level coreboot files. The long term plan is to enable out of tree mainboards / components to be built with a given coreboot version (given that the API did not change) Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Change-Id: Ib68ce1478a2e12562aeac6297128a21eb174d58a Reviewed-on: http://review.coreboot.org/9295 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-04-14samus: Declare TPM in devicetree.cb and include ACPI deviceDuncan Laurie
This adds the TPM device to the devicetree and configures an active high edge triggered interrupt at IRQ10 and adds the ACPI Device for the TPM into the DSDT. It also cleans up the EC PNP ID to use the EISAID for an EC since there are now two PNP devices declared, and removes the unused ENABLE_TPM define at the top of the DSDT. BUG=chrome-os-partner:33385 BRANCH=samus TEST=build and boot on samus, ensure TPM is functional at IRQ10 CQ-DEPEND=CL:226661 Change-Id: I4b9b016014d136fbf9a37003003632821ae93a53 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 0420e27b05d0f1568efa9beb849e0e8ff5995c86 Original-Change-Id: I2660cb30ac535da0b255603a619b9c09681ca947 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/226663 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9471 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-14wtm2/samus: fix coreboot compilation error with tpmp removedHarry Pan
Since CL:226662, all TPMP accessing should be removed as well, else it will cause wtm2 coreboot failed on build. BUG=none BRANCH=none TEST=./setup_board --board=fox_wtm2 && emerge-fox_wtm2 coreboot CQ-DEPEND=CL:226662 Change-Id: Ib25f2d32997ef82b0ebf049803f2c5002a0a3abf Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: c99456bf42544518e2a36b6e0bbfe7f4ee1b4aff Original-Change-Id: Ia0eebb1924bbb23979c880f7d05600a0cf1e4ca3 Original-Signed-off-by: Harry Pan <harry.pan@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/232165 Original-Reviewed-by: Wei Shun Chang <wei.shun.chang@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9477 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10samus: Log EC panics to eventlogShawn Nematbakhsh
Log the new EC panic host event. BUG=chrome-os-partner:36985 TEST=Manual on Samus. Trigger EC panic, verify that "Panic Reset in previous boot" is seen in /var/log/eventlog. BRANCH=Samus Change-Id: If59c522bd06f308a7ee6c5ff69ea427fcea361c9 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: dae4eb50b3607c5141a77fce6709107283f5dc36 Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Change-Id: I89b358a81a962fd463101d84b6bcf3b0a12830c7 Original-Reviewed-on: https://chromium-review.googlesource.com/252391 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: http://review.coreboot.org/9508 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10samus: Enable vr_slow_rampShawn Nematbakhsh
Enable slow ramp rate to reduce idle noise / crackle. BUG=None TEST=Performance/noise/power tested by others. BRANCH=Samus Change-Id: I3b0083bdb19f96fc018356bd744fdff3baaf8962 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 041fca21b863d3fd94dd5bebf89fe48f5ac74285 Original-Change-Id: Id7e55f3710304369a79150129db18300ae38f93a Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/248791 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9506 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10samus: Use codec internal 1.8V as DACREF sourceBen Zhang
This is needed for audio playback after we disconnect PP1800_CODEC from DACREF to avoid noise coupled on PP1800_CODEC, which makes recording noisy. For recording, DACREF comes from mic vref pump voltage. For playback, DACREF comes from internal 1.8V. BUG=chrome-os-partner:32953 BRANCH=samus TEST=Set MICBIAS to 2.970V on Samus, playback/recording is clean Change-Id: I65fb6dbfab54c7c4de6496fd4a0d666baead28ec Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 3e62a61f6cf6042f6d653a827698b55ac86e2d2b Original-Change-Id: I27430691e469dd7f4056d99438ce080062b58b9a Original-Signed-off-by: Ben Zhang <benzh@chromium.org> Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/241179 Reviewed-on: http://review.coreboot.org/9500 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10samus: Set MICBIAS1 to 2.970VBen Zhang
The default micbias1 voltage is 1.476V (1.8V * 0.82) which does not match what's specified on the schematic. This patch sets the voltage to 2.970V (3.3V * 0.90) according to the schematic. BUG=chrome-os-partner:32953 BRANCH=samus TEST=Set MICBIAS to 2.970V on Samus and verified with a scope Change-Id: I1ced834a5afe2de3fccf4bcff8ec9c8e5718f60a Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 176f9272801a3de5ed6fc05ade06042e2a2c0a5c Original-Change-Id: Icdbc1b5f65fe28591d54544372bdc2dacb50e9c1 Original-Signed-off-by: Ben Zhang <benzh@chromium.org> Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/241178 Reviewed-on: http://review.coreboot.org/9499 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10samus: Adjust SATA Gen3 TX voltage amplitudeDuncan Laurie
Reduce the SATA Gen3 TX voltage amplitude by 210mV based on the provided test results to help with SATA validation. BUG=chrome-os-partner:34121 BRANCH=samus TEST=build and boot on samus and ensure SATA is still working, firmware image will be provided for full validation. Change-Id: I574d2f457b7b6831a339602a4165e959a0e2ee7d Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 9500ec152d8f9c90513811b1a92d1a8c155f514a Original-Change-Id: I233fa1a9a7f2877a97ef6834304680f82b958e82 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/241800 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9496 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10samus: Add clear_recovery_mode_switch functionDuncan Laurie
In order for recovery request to be cleared with software sync disabled we need to implement this function in the mainboard. BUG=chrome-os-partner:28234 BRANCH=samus TEST=boot in recovery with software sync disabled, ensure that the next boot will not boot in recovery again. Change-Id: Ie9c845396dfc6ab65296b2f18a86e23590c833d6 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 430f85608cc3b59a68a86dba64ffe428bfc216a9 Original-Change-Id: Iac15b6a1b23cc971231339439bceb013f4a031bd Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/241052 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9492 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10samus: Set current backlight PWM valueDuncan Laurie
With recent changes in the 3.14 kernel and the switch to not using X the panel backlight is not geting turned on until chrome is started which means the splash screen is not visible. If we set the backlight PWM in coreboot then it will at least turn on for the early boot process. BUG=chrome-os-partner:31549 BRANCH=samus TEST=boot on samus in normal mode and see the boot splash logo Change-Id: I81e6b90617acb181b4de3365f8f56ec3b846b78b Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: f850fe3faff268a64f18e6bd176ec1126b921e3b Original-Change-Id: I622bef8af9bb6b753fe228b33ecdc4aae76af131 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/240853 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9491 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10samus: Add ACPI binding for rt5677 codec SPIBen Zhang
We'll need to find a real ACPI device ID for the rt5677 SPI driver. "RT5677AA" is temporary. BUG=chrome-os-partner:33495 BRANCH=samus TEST=load firmware via SPI; hotword detection works Change-Id: I6dc55c4641c27a38570debe841a6afeb048eb868 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: f0d7013b62c78deb82db1a431f079c79eded5270 Original-Change-Id: Ifb4a1b12776669e21c0b7c4679246717d72981ad Original-Signed-off-by: Ben Zhang <benzh@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/235902 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9486 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10samus: Add RT5677 ACPI/DT bindings with _DSDDuncan Laurie
To support the ACPI device specific properties that conform to the existing devicetree bindings for this codec (in upstream kernels) add a _DSD object to the existing codec device. BUG=chrome-os-partner:29649 BRANCH=samus TEST=build and boot on samus Change-Id: Ice808ba7bf2f0378ac5a38afd27dbf6c8cac0da5 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: b3fc2d7e5a5878b1fff7627f803b883b38fea28d Original-Change-Id: I344636171a3086a72087314503bfc99de5945b1f Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/238857 Original-Reviewed-by: Ben Zhang <benzh@chromium.org> Reviewed-on: http://review.coreboot.org/9483 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10samus: Move board version to a separate fileDuncan Laurie
This combines the board version reading and parsing to a separate file that is compiled in both romstage (for early serial output) and ramstage (for smbios tables). It also adds a new board version that is wrapped back to number zero as we are running out of available IDs. BUG=chrome-os-partner:32895 BRANCH=samus TEST=build and boot on samus EVT1 and EVT2 and check for proper board versions reported in console and smbios. Change-Id: I8c8f17708ced7167277a98529ff4597589f53095 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 3ab8bba1021a8dd41dd2210ba73efd2231eb596c Original-Change-Id: I2aa03e7486a9581f94dc4e12f6f29eb0c5b3bdbb Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/229041 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9473 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-07broadwell: Change all SoC headers to <soc/headername.h> systemJulius Werner
This patch aligns broadwell to the new SoC header include scheme. BUG=None TEST=Tested with whole series. Compiled Auron and Samus. Change-Id: I0cb6aa3d17ce28890e586be1c2c7ad16d91dd925 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 23bcaa8110c4b63999c6ebf370045e9bef87ce6e Original-Change-Id: I613ec0e2b970c75d1f8f7d9bb454bcf11abc78f0 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224507 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9364 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-04-04samus: Disable USB Port 5Duncan Laurie
This device is not used in current builds and should be disabled to help EMI. BUG=chrome-os-partner:34117 BRANCH=samus TEST=build and boot on samus Change-Id: I5c34f1f6c84d9de04a42e16fa32f57d4f9d1e478 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 00a9b2ad8512f84beff7358dad0ec028478c57d2 Original-Change-Id: I62541e343dcaa3cd31c81b73d8c27a5efcf3ad60 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/234403 Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9282 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Add new memory typeDuncan Laurie
Add a new memory type for the next build, and rename the existing ones to drop the Gb suffix. BUG=chrome-os-partner:33924 BRANCH=samus TEST=build and boot on samus Change-Id: Iedcd3823aa80c93fc2aadbc486d74b40c9bd4279 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: bcc9827965182a7d0d5325189d55eb76f5c2f0e7 Original-Change-Id: I47d2b7e58f51f3ee00cd7797da3f8353f509f8b5 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/230769 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9278 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Set codec PDM clock output to 3MHzBen Zhang
Currently the rt5677 codec outputs 6MHz PDM clock which is out-of-spec for the speaker amp SSM2537. The amp's GAIN_FS pin is pulled down to PGND with a 47k resistor, so the expected PDM clock is 64*FS (~3MHz) according to its datasheet. The corresponding kernel patch that adds the PDM clock config option is https://chromium-review.googlesource.com/#/c/230303/ BUG=chrome-os-partner:33303 BRANCH=samus TEST=flash coreboot with this patch and see PDM CLK went from 6MHz to 3MHz on samus with a scope. Change-Id: Icf2c61930175bede1ee8ebc2b0fb17c2938b806c Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: b9ba4597515b2fbcc72fa22e296357c454175648 Original-Change-Id: I09acdf47bab4f641981491a84197de234918435e Original-Signed-off-by: Ben Zhang <benzh@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/230344 Original-Reviewed-by: Dylan Reid <dgreid@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9277 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Change touchscreen bootloader mode i2c addressDuncan Laurie
This value apparently changed to 0x27 in the hardware but was never adjusted in firmware. BUG=chrome-os-partner:33790 BRANCH=samus TEST=build and boot on samus Change-Id: Ib610fc6522715e3c841c337d420ec63563bec798 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: e01d3b47bf49861e9d53fc8db41890fe4c91ff9b Original-Change-Id: I10ca7b77068491e143f8bf2463b481eada910618 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/230232 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9274 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Enable GSPI0 interfaceDuncan Laurie
This will be connected to the coded for firmware upload. BUG=chrome-os-partner:33495 BRANCH=samus TEST=build and boot on samus, check that GSPI driver is loaded Change-Id: Ife41394e31af9dab03495b34609cb119525f9b19 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: bbf26154da675845251c54f71d1df9df8d2a4fd5 Original-Change-Id: I25c91145aef8ca2aef229ffb27e8a45df659982e Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228835 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9273 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Enable GPIO9 as touchpad wakeDuncan Laurie
With EVT2 systems GPIO9 is now used for touchpad wake. BUG=chrome-os-partner:32232 BRANCH=samus TEST=suspend/resume by touchpad on samus, with kernel workaround to disable setting of T19 in atmel driver mxt_suspend() 51 | 2014-11-03 12:41:34 | ACPI Enter | S3 52 | 2014-11-03 12:41:37 | ACPI Wake | S3 53 | 2014-11-03 12:41:37 | Wake Source | GPIO | 9 Change-Id: I67c1a6591dc287fc780889950e78c731a5a65d44 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 8512a6e5266edaf77d300f47bd26c501f00361d7 Original-Change-Id: I8120747986e694b64d464826f87c9afa68af157a Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/227157 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9271 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Update thermal max for broadwellDuncan Laurie
Broadwell Tj_max is 105C, update accordingly. BUG=chrome-os-partner:28234 BRANCH=samus TEST=build and boot on samus Change-Id: I001e17287ebbcbfdd909428e149a95878734dab9 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: fb1de7a9e1d84f592b785a1b495e4aaf434f23a2 Original-Change-Id: If6a3fd682f4ee9b8010982870a61b76e33010fd4 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/226952 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9270 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Assign GPIO2 to HP_AMP_SHDN_LBen Zhang
BUG=chrome-os-partner:29649 BRANCH=samus TEST=Audio playback to headphone works Change-Id: I35efa3b97abbba50cbee4c25acfaeb155fc1238f Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: e2c0ede19c6b700c8d0bf01ff9d3a54984c5d784 Original-Change-Id: Ib51aace52026688dc8972047e5d934c80138ff80 Original-Signed-off-by: Ben Zhang <benzh@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/221294 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9269 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Make codec interrupt active highBen Zhang
The codec interrupt needs to be active high because multiple interrupt sources share this line: 1) Headphone plug detect 2) Mic present 3) Hotword detect These interrupt sources are OR-ed together. BUG=chrome-os-partner:29649 BRANCH=samus TEST=Jack detection works on samus Change-Id: If35fe8493ab30d878d9fac2251acee62c776b0eb Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 348608fe61f7848db2bfd22502a0c259d24f8980 Original-Change-Id: Ief0a291d9455f2d03789198153781ff8133aa1ce Original-Signed-off-by: Ben Zhang <benzh@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220588 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9268 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Add codec platform data for jack detectBen Zhang
GPIO IRQ support has been added in upstream rt5677 driver, with new jack detect platform config options. BUG=chrome-os-partner:29649 BRANCH=samus TEST=headphone and mic detect works on Samus Change-Id: I68a675ccd1fec3e5329d57aadad3229053092026 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 4b90fa2f557f603661e25c9e1b4712eea15c8502 Original-Change-Id: I379087b8acdb13e65776a18c9ee3a58d4cb4e73c Original-Signed-off-by: Ben Zhang <benzh@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224513 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9266 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Change GPIO controller label to INT3437:00Duncan Laurie
This matches the label exported by the GPIO controller in the kernel and allows more speicific matches if there are other devices that also export GPIOs. BUG=chrome-os-partner:33098 BRANCH=samus TEST=crossystem wpsw_cur returns 1 Change-Id: I96f8d0f7f9fd584be4a6f14d13e04db0a88951a8 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 736679136a0a72874304eaeae1ac58633cd2ce14 Original-Change-Id: I655549d0f0eca341581bfbf845162d8b9f5e993d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224136 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9265 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Enable update screen for software syncDuncan Laurie
Since the PD software sync is slow enable support for displaying a screen telling the user that something is happening. BUG=chrome-os-partner:32379 BRANCH=samus TEST=manual testing: 1) in normal mode, with EC/PD in RW, ensure that they are rebooted to RO and the VGA Option ROM is loaded and the wait screen is displayed, and then the system is rebooted at the end and the VGA Option ROM is not loaded. 2) same as #1 with EC/PD in RO already, same result 3) same as #1 with system in developer mode, same result except there is no reboot at the end of software sync 4) same as #1 with system in developer mode and EC/PD in RO, ensure that there is no extra reboot at the beginning or end of software sync. Change-Id: Ib6c4cc03952768ece76832efc84f665c52191ffb Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 6971d74ff50ced0ef94d5fec26c0e6a071d207b2 Original-Change-Id: I125744f58c6b84df1af3943d9be98fe55c7117d5 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223850 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9264 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Add smbios_mainboard_version to define board versionDuncan Laurie
Instead of having this in mosys just have coreboot report the board version in SMBIOS tables. BUG=chrome-os-partner:32359 BRANCH=samus TEST=build and boot on samus, check /sys/class/dmi/id/product_version Change-Id: I09d235752f4c870f99fb8c6a280e2bf9aba7e137 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 08413589ba84b07ff64c9116ca5fcc991cee3b89 Original-Change-Id: Ib851d2e79ed721dcbc1c2f2eda6da50cac064cf3 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223096 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9263 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Add codec platform info in ACPIDuncan Laurie
This is the specific codec setup platform data for samus. BUG=chrome-os-partner:29649 BRANCH=samus TEST=emerge-samus coreboot Change-Id: I00d4a2f73810f5f7bad49922321fb1c340289770 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 813c45bc3fdd7a2fb84df0e24bd470003bf4eafa Original-Change-Id: I5e2a8fad58bb8a3d02ccece0b1f6fe52f56c94ea Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/221539 Original-Reviewed-by: Ben Zhang <benzh@chromium.org> Reviewed-on: http://review.coreboot.org/9261 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02samus: Fix codec interrupt and add GPIO definesDuncan Laurie
The codec interrupt needs to come from codec GPIO1, so use the HOTWORD_DET GPIO as the codec IRQ and the DSP_INT as the wake.The This means codec interrupt is GPIO46 which is PIRQO and should be interrupt 30. Also add GPIO defines for the GPIOs attached to the codec itself. These are defined by index, and I used the same "jack detect" and "mic present" indices that were used in baytrail. The codec interrupt to the host is added at index 2 and the hostword detect interrupt to the host is added at index 3. These can be changed as we work through the implementation in the kernel driver. BUG=chrome-os-partner:29649 BRANCH=samus TEST=build and boot on samus Change-Id: Id9cb083ddf9df161be314da4148740ed9f4d0fe6 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 3958efb28813c664a8a4219f78bdd0fcfe75c706 Original-Change-Id: I1c1ac1b6095fab7e3f4412555db4f9a9138e528b Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220326 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9216 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02samus: Clean up touch wake sourcesDuncan Laurie
Move _PRW to the ACPI devices for the touchpad and touchscreen. Add a _DSW method, but disable it by default for now until a spurious wake issue can be resolved. BUG=chrome-os-partner:32232 BRANCH=samus TEST=build and boot on samus, ensure trackpad does not spuriously wake the system. Change-Id: I3160248ef6dfeccdec765553643d9b8de2bb2ed1 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 85d14842aefdb29c750009c0092f055587172dac Original-Change-Id: Ic4763f2cb5f3a59d04b236cee94906025661c615 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220325 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9214 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02samus: Fix and clean up GPIOs and EC info/eventsDuncan Laurie
- Define specific GPIOs in gpio.h instaed of smihandler.c - Add battery status event to SCI list - Remove old proto board version defines and SPD index usage - Do not disable cmd_pwr training now that it works on EVT board BUG=chrome-os-partner:32196,chrome-os-partner:29117 BRANCH=samus TEST=build and boot on samus Change-Id: I50f1599aa4266ed61749cc7f4229a9384b498df2 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 0e3ebcb8659c92874d3ca89fa3a6795c9b6eebfa Original-Change-Id: I53cf8d80ed7f675c10fa04e8fe8b879a4af9b21f Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220321 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9220 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02samus: Ensure PD controller is in RO mode for recoveryDuncan Laurie
In order to not break FAFT, and to have a quicker recovery mode boot, reboot the PD controller into RO image in romstage. This is done before the EC since rebooting the EC into RO will also reboot the host. BUG=chrome-os-partner:30079 BRANCH=none TEST=boot samus EVT into recovery with 'dut-control power_state:rec' and ensure that the PD controller is rebooted to RO in romstage. Change-Id: Ieb51717c17fdcbda7aa63b6a9404959e8736c08f Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 19237f6a338fa1c593867d8dfda1edcd376878af Original-Change-Id: I633f51afc382a7faab825c15618c0bc7566c4395 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218904 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9205 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02Samus: fix unused GPIO pinKenji Chen
Mark GPIO42 as unused according to Samus schematics BUG=None TEST=Make the chnage; Pass the build process; Need someone having the board perform the verification. Change-Id: Ib53a3ae062d414a2c98ec0756e759760d179e3fd Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 4e0f8f3276c575ff60fbda709de5d3cfe31a5900 Original-Change-Id: Ifd6a0d2de8af0fe3af4a14f44ce572b41b77509c Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217344 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9199 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-01mainboards: fix spd generationAaron Durbin
echo is evaluated by a shell builtin producing non-binary spd data of the form '-e -n \<byte>'. Correct this by using printf builtin which does the equivalent and is more cross platform friendly. Boards changed: gizmosphere/gizmo gizmosphere/gizmo2 google/bolt google/falco google/link google/peppy google/rambi google/samus google/slippy pcengines/apu1 Change-Id: Iefdaf59903b9682cc88c94fd991883b560616492 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9196 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-30Update hex values to CBFS binary name types in MakefilesMartin Roth
These binaries were being added to CBFS using hexadecimal values instead of the CBFS binary type names. The same value was being used in different places for different things. For example, the value 0xAB is used for SPDs, MRC & FSP binaries. This patch uses CBFS type names instead of hex values everywhere a hex value was previously used. Change-Id: Id5ac74c3095eb02a2b39d25104a25933304a8389 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/8978 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27samus: Update SPD with correct geometry and timingsDuncan Laurie
This memory is also x16 and needs slight tweak to tRFCmin in order to be functional. BUG=chrome-os-partner:31833 BRANCH=None TEST=build and boot on EVT unit with this config Original-Change-Id: I01163ee7e70f08ccad84a3da39f1aac96e4c4771 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217190 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 6c4bf71c8c8e1e46ce290441c2e21bc7b2839760) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I389936d85e61a0a939cd4485fcc0723d2a0aa4d6 Reviewed-on: http://review.coreboot.org/8972 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2015-03-27samus: Add PD MCU ACPI device and unmask host eventShawn Nematbakhsh
Samus has a PD MCU, and should handle PD MCU host events. BUG=chrome-os-partner:31361 TEST=Manual on Samus. Verify that ACPI Notify routine is called when host event is sent from EC. BRANCH=None. Original-Change-Id: Id40ebd438b3dd60cefc7650f2edc695c589343e9 Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214860 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Alec Berg <alecaberg@chromium.org> (cherry picked from commit d0752be013f66313d4218338e62372d0f5975097) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I08eb51eceeb7d2835d55e7e861126b137de72bf6 Reviewed-on: http://review.coreboot.org/8969 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27samus: Updates for EVT boardDuncan Laurie
- Remove NFC GPIOs - Change EC wake to GPIO27 - Enable wake on HOTWORD_DET_L_3V3 - Add new Hynix memory SKU BUG=chrome-os-partner:31549 BRANCH=none TEST=emerge-samus coreboot, cannot fully test until EVT Original-Change-Id: Ia25fc39f0b67c53305b3fd9150117d6a7867eb3a Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/213796 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 740ac0bb7eaa9ae35fce8a04825f9c5ecf7cab79) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I2b1c194eae2ebc53291f078c00ba04f82e10b0c1 Reviewed-on: http://review.coreboot.org/8963 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-25 05:04:13 +0000