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2019-01-11soc/mainboard: Update mainboard UART KconfigLijian Zhao
After f5ca922 (Untangle CBFS microcode updates) got merged, all mainboard using intel apollolake, cannonlake, coffeelake, glk, kabylake, skylake, icelake and whiskeylake get affected. Using INTEL_LPSS_UART_FOR_CONSOLE instead of UART_DEBUG and set default console for each platform. BUG=N/A TEST=Build and test on Sarien platform, by default we can still get console from cbmem, and enable CONSOLE_SERIAL can get logs from UART port 2. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I550a00144cff21420537bb161c64e7a132c5d2de Reviewed-on: https://review.coreboot.org/c/30853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-10sb/intel/common: Show "Add EC firmware" only for boards that need itJan Tatje
Most boards currently do not use EC firmware from SPI flash in the IFD, this hides this option by default and shows it only for boards that need it. A new config variable MAINBOARD_USES_IFD_EC_REGION is introduced to enable this option for boards that need it. The following list of boards requiring this was provided by Lijian Zhao: 1. intel/cannonlake_rvp 2. intel/coffeelake_rvp 3. intel/icelake_rvp 4. google/sarien 5. google/hatch Change-Id: I52ab977319d99a23a5e982cc01479fe801e172a7 Signed-off-by: Jan Tatje <jan@jnt.io> Reviewed-on: https://review.coreboot.org/c/30697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-01-10mb/google/sarien: Add PDR and RW_LEGACY_NVRAM to FMAPDuncan Laurie
1) Add a Platform Data Region called SI_PDR which is allocated in the flash descriptor for this platform 2) Add a DIAG_NVRAM region for use by the diagnostic payload for non-volatile storage. 3) Encapsulate both RW_LEGACY and DIAG_NVRAM in a region called RW_DIAG so it is clear they are associated. 4) Move the RW_DIAG region to the start of the RW region so that once we can re-enable a larger BIOS region this sub-region will be in the uncached area since it is not accessed on a normal boot. BUG=b:119435206 TEST=tested on Arcada board to ensure expected regions are present Change-Id: Ieb8bc4cf70d0a931e4944210112cfaf5c543f9f3 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/30755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-01-08mb/google/sarien: Set minimum assertion width valuesDuncan Laurie
Explicitly configure the minimum assertion width values to ensure that they are set as expected and are not using unknown defaults. Change-Id: I9a88e5b6002137df6e572b84d0de8a69522938f9 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/30722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-01-08mb/google/sarien: Enable recovery mode GPIODuncan Laurie
Enable the active-low recovery mode GPIO now that new boards are available which have an external pull-up instead of a pull-down so it can be asserted properly by servo. This was tested on a Sarien system by holding the recovery button on the servo board and tapping the cold reset button and ensuring that it enters recovery mode. Change-Id: I3216580bc94de71b05bf9382f15d0c4d428cb9fa Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/30721 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-01-08mb/google/sarien: Remove power button ACPI deviceDuncan Laurie
These platforms use the standard fixed function power button and do not need a second power button device declared or the kernel will end up with two devices reporting the same event. Change-Id: I6fe2b201a6a6f6307a0c4bd6a61f56cfcdd88bf4 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/30720 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-01-07mb/google/sarien: Correct I2C bus clock for touchpadLijian Zhao
Elan touchpad require connected i2c clock to be running at 400Khz, with the modification can get 404Khz speed from Arcada EVT platform. BUG=b:119628524 TEST=Build and boot up on Arcada platform, measure the i2c clock is around 400Khz. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: If717cdd6b73394125df54d90f729ffb4ef37b087 Reviewed-on: https://review.coreboot.org/c/30653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-07mb/google/sarien: Modify ELAN Touchpad i2c bus clkJohn Su
Modify ELAN touchpad bus i2c clk from 466Khz to 400Khz. BUG=b:119628524 BRANCH=master TEST=measure ELAN Touchpad CLK Change-Id: Ia8433c6ef320cea9a0145db4ba440d67ccd0f41e Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30588 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-04mb/google/sarien: Add settings for noise mitgationLijian Zhao
Enable acoustic noise mitgation for sarien platform, the slow slew rates are fast time dived by 8. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I5d38a1e03af08f106e2422a319b34c3fb54bdf28 Reviewed-on: https://review.coreboot.org/c/30448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-12-29mb/google/sarien: Adjust GPD3 pin terminationLijian Zhao
Internal pull up need to be enabled for GPD3 as power button pin for PCH according cannonlake pch EDS vol1 table 17-1. Without that pin will stay floating and hook up XDP can cause system shutdown as power buttone event will trigger. BUG=N/A TEST=Hook up XDP on sarien platform, able to boot up into OS and stay at power up state. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: Ibe21da5f4a0797a3d62b36899f023908b46c25bf Reviewed-on: https://review.coreboot.org/c/30374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-12-21mb/google/sarien: Disable pcie interface for wwanLijian Zhao
WWAN chip support 3 interfaces as pci express, USB 2.0 and USB 3.0, the usgae of Sarien choose to only use USB interface but not over pci express, so totally disable pci express root port 12. BUG=b:1246720 TEST=Boot up into OS with WWAN attached, cold boot and warm boot 10 cyles can still device can be listed under lsusb. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: Ic4da393c0c0d903848111e1c037c2730c86afa7d Reviewed-on: https://review.coreboot.org/c/30350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2018-12-19mb/google/sarien: Enable DMI/SATA power OptimizeLijian Zhao
Turn on power optimizer of PCH side DMI and SATA controller. BUG=N/A TEST=Build and boot up into sarien platoform, able to finish 100 cycles of s0ix. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I41da2b4106d683945cdc296e2a77311176144f43 Reviewed-on: https://review.coreboot.org/c/30212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-12-19mb/google/sarien: Use meaningful SATA modeLijian Zhao
Define SATA mode to AHCI mode instead of 0, make devicetree more readable. BUG=N/A Change-Id: I903545d9487c1409f9008407fe5bee6aa4959b98 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-12-19mb/google/sarien: Enable ELAN Touchpad and Disable ALPS TouchpadChris Zhou
Enable ELAN Touchpad and Disable ALPS Touchpad BUG=b:119628524 BRANCH=master TEST=ELAN Touchpad can work normally. Change-Id: I7839459a70768fa95ba4871b1915d2ea86419bbb Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2018-12-18Revert "google/sarien: Increase BIOS region to 28MB"Lijian Zhao
This reverts commit ad41f5512306d118047d2f7243678ddb32b4b06b. Reason for revert: <Issue have seen on EVT platform that vboot always fail to verify keyblock A> BUG=b:121169122 Change-Id: I2790ef3463a228008b614498009fbdc8b493cfb0 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30286 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-18mb/google/sarien/variants/arcada: Enable touchpad and touchscreenCasper Chang
Enable Elan touchpad and WACOM touchscreen BUG=b:119924134, b:120103010 BRANCH=master TEST=Verify touchpad and touchscreen on arcada work with this change. Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I3dcdb4eeeb32766e64553d9e69e6b7e2b5ba85aa Reviewed-on: https://review.coreboot.org/c/30146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-12-18src/mb/google/*/Kconfig: Consistently use $(...) for variablesJonathan Neuschäfer
Using ${...} in some places is slightly confusing. Fixes: 395cbb4f97 ("mb/*/*/Kconfig: Use CONFIG_VARIANT_DIR for devicetree") Change-Id: Id0856a10d92786a41d45ca697945699f6f4c1f4c Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/30163 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-11mb/google/sarien: Disable unused SATA portsLijian Zhao
Disable SATA port 0 and port 1 as that's not used as SATA on platform. BUG=N/A TEST=Build and boot up fine on google arcada board. Change-Id: I1b8801f7a0f9b7847b85d7c315fa0a2093b32f70 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2018-12-11mb/google/sarien: Disable PCH Gigabit LANLijian Zhao
There's no LAN connection on Arcada board, so disable PCH GBE. BUG=N/A Change-Id: I07c66df50dbe9fefd95a67b5af9e3f61ce6a18aa Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2018-12-10mb/google/sarien: Update GPIOs for next buildDuncan Laurie
Update the GPIOs for the next board build. Mostly minor changes but the polarity change on GPP_E8/RECOVERY on sarien will result in it booting to recovery every time unless using new hardware. For this reason the recovery mode GPIO that is passed to vboot is commented out for sarien. It is only used for testing and currently it is useful to have an image that works on both board versions. Change-Id: I32d84f3010cb4d3968370a03f7e191b1710a50e8 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/30062 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-10mb/google/sarien: Setup GPIOs again after FSP-SDuncan Laurie
Currently CoffeeLake FSP is incorrectly modifying GPIO pad configuration if specific UPD variables are not set as it expects. This affects the display-related SOC pads with the following UPD variables: UINT8 DdiPortBHpd; // GPP_E13 UINT8 DdiPortCHpd; // GPP_E14 UINT8 DdiPortDHpd; // GPP_E15 UINT8 DdiPortFHpd; // GPP_E16 UINT8 DdiPortBDdc; // GPP_E18/GPP_E19 UINT8 DdiPortCDdc; // GPP_E20/GPP_E21 UINT8 DdiPortDDdc; // GPP_E22/GPP_E23 UINT8 DdiPortFDdc; // GPP_H16/GPP_H17 Until FSP is fixed to not touch the pad configuration this workaround will reprogram the GPIO settings after FSP-S step so they are correct when the OS attempts to use them. This was found in CoffeLake FSP Gold release: https://github.com/IntelFsp/FSP/tree/master/CoffeeLakeFspBinPkg As well as the current top-of-tree for the FSP sources. BUG=b:120686247,chromium:913216 TEST=verify correct GPIO configuration for GPP_E group in the kernel Change-Id: I19550c4347cf65d409de6a8638619270372c4d0a Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/30113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-09mb/google/sarien: Enable LAN clock source usageLijian Zhao
FSP defined a special clock source usage 0x70 for PCH LAN device, update that to google sarien platform. BUG=b:120003760 TEST=Boot up into OS, ethernet able to be listed in ifconfig. Change-Id: I9f945be4f0ce15470ab53f44e60143f3fd0fddf8 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-12-07mb/google/sarien: Enable ISH on arcada, disable on sarienDuncan Laurie
The Intel Sensor Hub was enabled on the wrong variant so this change moves the enable from sarien to arcada. Change-Id: If933623f7dbb45c4805fb61430465236eca19ee8 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/30070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-07mb/google/sarien: Set initial I2C bus rise/fall timesDuncan Laurie
Provide rise/fall times as measured on existing boards. This will need adjusted for new boards but provides a starting point that makes I2C clocks look reasonable. Tested by measuring I2C bus speed and rise/fall times with a scope. Change-Id: Ic18010f5efc41dcee8925d696767ba2c44e3df4b Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/30069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2018-12-06mb/google/sarien/variants/sarien: Enable melf touchscreenChris Zhou
BUG=b:119799550 BRANCH=master TEST=Verify touchscreen on sarien works with this change. Change-Id: I926c988c141628ae2d98206f9eb615d06357a366 Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/29830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-12-05mb/google/sarien: Enable ISHJett Rink
Turn on the ISH in the device tree. BUG=b:120295222 Change-Id: I0ba08c245d050aebc6eb06055690c422ab9b51c6 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://review.coreboot.org/c/30034 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-05google/sarien: Increase BIOS region to 28MBLijian Zhao
Platform have a 32MB SPI chip, so we can increase the bios region from 16MB to 28MB. BUG=b:119267832 TEST=Build and boot fine on sarien platform. Change-Id: I9bc0fa0f662e5ec64e77f2005dbb2e7edb8b2524 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/29945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-12-04mb/google/sarien: Enable WWAN detection on ArcadaLijian Zhao
Set GPIO D22 low to get WWAN_PERST#_R asserted. BUG=N/A TEST=Boot up with Arcada board, check WWAN get detected as USB devices through lsusb command. Change-Id: Ie848cd19fdf3b6c4b6abeb5fa3f566e5e4e7e928 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30030 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-04mb/google/sarien: Define USB devices for ACPIDuncan Laurie
Add the USB device information for the sarien/arcada variants. This includes the ACPI _PLD group definitions for the external ports that indicate which USB2 and USB3 ports share the same physical interface. Change-Id: I0b936127954ba09c61ccb871bfc62ee7d99da263 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/30000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-04mb/google/sarien: Enable DPTFDuncan Laurie
Enable DPTF support for sarien/arcada boards. This is currently using placeholder values that are identical that will be updated after thermal tuning is done. Change-Id: I7d51c3b38068fc25927c8dafc0bd9069b29d77f5 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/29762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-04mb/google/sarien: Enable WWAN detectionAmanda Huang
Set WWAN_GPIO_PERST#(GPP_D22) to low at bootblock stage to meet the logic output for WWAN_PERST#_R to high. BUG=120004153 TEST=Boot up Sarien board, check WWAN get detected as USB devices through lsusb. Change-Id: I16f1101c64dfd4dcb5e8342fdb925951f6f2f90b Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-11-30cpu/intel/common: Use a common acpi/cpu.asl fileArthur Heymans
Change-Id: Ifa5a3a22771ff2e0efa14fb765603fd5e0440d59 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: David Guckian
2018-11-29mb/google/sarien: Add HD Audio verb tableLijian Zhao
Implement HD Audio verb table for RealTek ALC 3204/3254 codec on google sarien and arcada board. BUG=b:119058355,119054586 TEST=Confirm audio play back is working on Sarien and Arcada board. Change-Id: Icedbb510c7668d96c99c657091fc865f03bf7783 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/29484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
2018-11-23mb: Set coreboot as DSDT's manufacturer model IDElyes HAOUAS
Field 'OEMID' & "OEM Table ID" are related to DSDT table not to mainboard. So use macro to set them respectvely to "COREv4" and "COREBOOT". Change-Id: I060e07a730e721df4a86128ee89bfe168c69f31e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: David Guckian
2018-11-21ACPI: Fix DSDT's revision fieldElyes HAOUAS
DSDT revision is =1 for ACPI v1 and =2 for greater ACPI version. This will cause the AML interpreter to use 32-bit integers and math if the version is 1, and 64-bit if the version is >=2. Current spec version is 2 for ACPI 6.2-a. Change-Id: I77372882d5c77b7ed52dcdd88028403df6f6fa7f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29626 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-17mb/google/sarien: Set SMBIOS mainboard SKUDuncan Laurie
Setting sku_id() is not enough to get a value to show up in the SMBIOS tables, it also needs to be returned as a string for the table creation to consume. This change defines the smbios_mainboard_sku() function and returns a string constant of "sku#" as expected. Change-Id: I03013bab89d53d1eba969c6ffb7e95fcbb315a81 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Trent Begin <tbegin@google.com>
2018-11-16mb/*/*/Kconfig: Use CONFIG_VARIANT_DIR for devicetreePeter Lemenkov
Change-Id: Ic9620cfa1630c7c085b6c244ca80dc023a181e30 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-13mb/google/sarien: Enable EC _PTS/_WAK methodsDuncan Laurie
Enable the option to have the system level _PTS/_WAK methods call the EC provided methods when they are invoked by the OS. Verified on sarien board by inspecting dsdt.dsl: Method (_PTS, 1, NotSerialized) // _PTS: Prepare To Sleep { DBG0 = 0x96 \_SB.PCI0.LPCB.EC0.PTS (Arg0) } Method (_WAK, 1, NotSerialized) // _WAK: Wake { DBG0 = 0x97 \_SB.PCI0.LPCB.EC0.WAK (Arg0) Return (Package (0x02) { Zero, Zero }) } Change-Id: I52be1c1cd7adae9ad317a51868735eb87a410549 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-08mb/google/sarien: Set runtime IRQs to reset on PLTRSTDuncan Laurie
GPIOs that use GPI_APIC setting with DEEP can cause an IRQ storm after S3 resume. GPIOs that fire IRQs via IOAPIC need to get their logic reset over PLTRST to prevent IRQ strom after S3 resume. For sarien/arcada these are all runtime IRQs only, not wake capable. Change-Id: Iec3706a3b47b54abbacd06081910f389979c330f Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-08mb/google/sarien: Disable eSPI when ACPI is enabledDuncan Laurie
Select the option to disable eSPI when ACPI is enabled so the EC is unable to assert an SMI when booted into the OS. There is a kernel driver that implements the same mailbox interface so it cannot also be used by the SMI handler. Change-Id: I8bafc749f22aed5595e19e773762ee8b038950b9 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-07mb/google/sarien: Add sku_id functionDuncan Laurie
This change adds a sku_id() function that returns a static value to differentiate the sarien and arcada boards. Change-Id: I1fecc675573a6aece7188aae9370733068d45dbf Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29486 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-07mb/{intel/google}: Move CNVi ASL entry from static DSDT to dynamic SSDT ↵Subrata Banik
generation This changes uses drivers/intel/wifi chip for CNVi device to ensure that: 1. Correct device name shows in ACPI name space 2. Correct wake up shows in cat /proc/acpi/wakeup 3. Remove cnvi.asl from soc/intel/cannonlake Change-Id: Ic81de2dce6045ced913766790a40ed19119f5118 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/29399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-05mb/google/sarien: Enable WWAN detectionLijian Zhao
WWAN start-up control requires RESET# assert after FULL_CARD_POWER_OFF# set to high more than 10 ms, so force RESET#(GPP_D21) to low at bootblock stage to match the sequence. BUG=N/A TEST=Boot up Sarien/Arcada board, check WWAN get detected as USB devices through lsusb. Change-Id: I36eb841a2e8f2b36771d20577314a7451fbee133 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/29430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-11-02mb/google/sarien: Enable Wilco ECDuncan Laurie
The Sarien mainboard uses the newly added Wilco EC. - enable CONFIG_EC_GOOGLE_WILCO - add the device and host command ranges to the devicetree - have the mainboard SMI handlers call the EC handlers - add EC and SuperIO devices to the ACPI DSDT - call the early init hook for serial setup Change-Id: Idfc4a4af52a613de910ec313d657167918aa2619 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-11-02mb/google/sarien: Add Arcada variantDuncan Laurie
Add a variant of the Sarien board called Arcada. This is currently very similar to Sarien with differences in PCIe, USB, and GPIO usage. Change-Id: I432d2ba99558e960d4e775c809cc8bf6aa1a56bf Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29410 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-02mb/google/sarien: Add new mainboardDuncan Laurie
Sarien is a new board using Intel Whiskey Lake SOC. It also uses the newly added Wilco EC, enabled in a separate commit. Sarien is not a true reference board, it is just one variant of a very similar design. For that reason it is not considered the baseboard but rather a standalone variant. Change-Id: I2e38f617694ed2c2ef746ff8083f2bfd58cbc775 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-17 00:42:27 +0000