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path: root/src/mainboard/google/snow
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2014-05-03Move ARCH_* from board/Kconfig to cpu or soc Kconfig.Furquan Shaikh
CONFIG_ARCH is a property of the cpu or soc rather than a property of the board. Hence, move ARCH_* from every single board to respective cpu or soc Kconfigs. Also update abuild to ignore ARCH_ from mainboards. Change-Id: I6ec1206de5a20601c32d001a384a47f46e6ce479 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/5570 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-01ChromeOS: Use common fill_lb_gpio()Kyösti Mälkki
Change-Id: I2ba7a1c2b2e6ce2c00c9a2916141bed67930ba2d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5586 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-30console: Move UART port defaults to mainboardKyösti Mälkki
Correct selection of UART depends of board layout, not the CPU internals, so default setting should originate from mainboard. Change-Id: Ibf0ab0847ccce73c22704e86983dbe3d24ebc8a0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5618 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-26Rename coreboot_ram stage to ramstageFurquan Shaikh
Rename coreboot_ram stage to ramstage. This is done in order to provide consistency with other stage names (bootblock, romstage) and to allow any Makefile rule generalization, required for patches to be submitted later. Change-Id: Ib66e43b7e17b9c48b2d099670ba7e7d857673386 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/5567 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-03-04uart: Drop HAVE_UART_MEMORY_MAPPEDKyösti Mälkki
This option is used to make uart8250mem option visible in menuconfig. Showing it for these ARMs is incorrect. Change-Id: I2c28e1c3781df41c09c365355a5105c9fe4945ed Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5259 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-02-06ARMv7: Remove static CBMEM allocationKyösti Mälkki
The calculations for static allocation are no longer valid. Change-Id: I6740cdcec789abddf78485a0edaf24882ef8c2a5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4569 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-01-19board_info.txt: declare chromebooks as laptops.Vladimir Serbinenko
Change-Id: I4a3ed7e9b6aaec8aba8ffc47eafdbcca31e4c700 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4734 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2013-12-21exynos5250: Implement support to boot with USB A-A firmware uploadJulius Werner
This patch implements the basic infrastructure required to use the USB A-A firmware upload feature on Exynos5 processors with Coreboot. It will require a corresponding host-side script that activates the feature and uploads the correct image parts in the correct order to harcoded target addresses, as described in the comments of alternate_cbfs.c. Also fixes a bug in the Google Snow mainboard where it would not correctly initialize the pinmux configuration for the SPI flash bus. During a normal SPI boot the IROM would already do that for you, but when booting from USB you have to do it yourself. Change-Id: I40a39f8f5d1d70b58dbf258015c1653a27097d67 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/64875 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4456 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21snow: Set up the i2s0 pins during bootGabe Black
Change-Id: I6729a139091b40d8fd9ba2aa7a8c4e14216d95c5 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/64879 Reviewed-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: Stefan Reinauer <reinauer@google.com> Tested-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4440 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21armv7/exynos: Fix and remove memory reset workaroundsHung-Te Lin
The memory corruption problem in Exynos suspend/resume process is caused by two things together: PHY_RESET and MRS command. After stop sending MRS on resume, we can now remove the workaround of skipping PHY_RESET. Change-Id: I64acc27c1d2bb549ae6ad7d32ecda94b0355972c Reviewed-on: https://gerrit.chromium.org/gerrit/64736 Tested-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/4433 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21snow: TPS69050 -> TPS65090David Hendricks
This corrects a minor typo used for a part number. Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I8583cbfc3b4a6c3ad06419f5aab3ba7a8f685575 Reviewed-on: https://gerrit.chromium.org/gerrit/64301 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4424 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Exynos 5250: Enable dynamic CBMEMStefan Reinauer
... In order to do this, the graphics memory has to move into the resource allocator and out of CBMEM. Change-Id: I7396da4a7068404b0d2e4d308becab4dd6ea59bb Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/59326 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4390 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-12snow: Fix the edid data structure definition so depthcharge works again.Gabe Black
Some new fields were added to the edid data structure, and the edid code was changed to put estimated values into those fields which were ultimately passed into depthcharge or other payloads. On snow we do things different and just declare an edid structure statically which didn't have those members. The rows and columns of the graphics console were 0, and that confused the framebuffer driver and made it loop forever. Change-Id: I6ca3bd948482b347a6a981e83b82b10dca995e5e Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/61057 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4341 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-02Add option to disable ChromeOSKyösti Mälkki
Those building Chromebook firmware from coreboot git might be more interested in building without ChromeOS extras. Change-Id: I2f176d059fd45bf4eb02cc0f3f1dcc353095d0ce Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3977 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-09-17Fix whitespace leaked into treeKyösti Mälkki
Clean whitespace errors that have gotten past lint-stable-003-whitespace and gerrit review. Change-Id: Id76fc68e9d32d1b2b672d519b75cdc80cc4f1ad9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3920 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-09-11CBMEM ARM: Prefer get_cbmem_table() over cbmem_late_set_table()Kyösti Mälkki
Implementing get_cbmem_table() allows initializing CBMEM earlier. Change-Id: I973f3a84dd9aaa2839959df5dda22909fdb9edeb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3560 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-11CBMEM: Add cbmem_late_set_table() and drop references to high_tables_baseKyösti Mälkki
This helper function is for compatibility only for chipsets that do not implement get_top_of_ram() to support early CBMEM. Also remove references to globals high_tables_base and _size under arch/ and from two ARMv7 boards. Change-Id: I17eee30635a0368b2ada06e0698425c5ef0ecc53 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3902 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-07-10armv7/exynos: Prevent unexpected reboots in resume.Hung-Te Lin
In resume path, if memory setup takes too long without setting PS_HOLD, EC watch dog may power off or reboot the system. To prevent that, we should enable PS_HOLD in same timing as cold boot - right before starting memory setup. Change-Id: I5c294fa7ae015f8cff57b1fd81e5b80902647b15 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3718 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10Exynos5250: Initialize USB PHYStefan Reinauer
... this is needed for libpayload to talk to USB devices. Change-Id: I7eb19003c9e96efb5fa7a3f97c7b15f3ef332687 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3696 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10exynos5250: De-switch-ify the pinmux configuration code.Gabe Black
The pinmux code for the exynos5250 was all bundled into a single, large function which contained a switch statement that would set up the pins for different peripherals within the SOC. There was also a "flags" parameter, the meaning of which, if any, depended on which peripheral was being set up. There are several problems with that approach. First, the code is inefficient in both time and space. The caller knows which peripheral it wants to set up, but that information is encoded in a constant which has to be unpacked within the function before any action can be taken. If there were a function per peripheral, that information would be implicit. Also, the compiler and linker are forced to include the entire function with all its cases even if most of them are never called. If each peripheral was a function, the unused ones could be garbage collected. Second, it would be possible to try to set up a peripheral which that function doesn't know about, so there has to be additional error checking/handling. If each peripheral had a function, the fact that there was a function to call at all would imply that the call would be understood. Third, the flags parameter is fairly opaque, usually doesn't do anything, and sometimes has to have multiple values embedded in it. By having separate functions, you can have only the parameters you actually want, give them names that make sense, and pass in values directly. Fourth, having one giant function pretends to be a generic, portable API, but in reality, the only way it's useful is to call it with constants which are specific to a particular implementation of that API. It's highly unlikely that a bit of code will need to set up a peripheral but have no idea what that peripheral actually is. Call sights for the prior pinmux API have been updated. Also, pinmux initialization within the i2c driver was moved to be in the board setup code where it really probably belongs. The function block that implements the I2C controller may be shared between multiple SOCs (and in fact is), and those SOCs may have different pinmuxes (which they do). Other places this same sort of change can be made are the pinmux code for the 5420, and the clock configuration code for both the 5250 and the 5420. Change-Id: Ie9133a895e0dd861cb06a6d5f995b8770b6dc8cf Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3673 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10google/snow: Don't spew output with GPIO configStefan Reinauer
There are hundreds of GPIOs on the Exynos5250. Don't always print all of them per default. Change-Id: Ie349f2a4117883302b743027ed13cc9705b804f8 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3661 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10exynos5250: Simplify the graphics code by eliminating the unused color map.Gabe Black
The code that allocated space for the framebuffer was adding space for a vestigial color map which was never used. It was also passing around a structure which was used to calculate a single value which was already known when that structure was put together. Eliminate the extra space, and pass the single value instead of the structure. Change-Id: Ia6a41cefdf8b29fe7d68f9596a156eced6eb5df8 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3652 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10snow: Make coreboot set up pins for busses it knows are hooked up as suchGabe Black
Coreboot knows that, for the snow board, certain pins are to be connected to bus controllers in the SOC and to the wires of a bus external to the SOC. It can configure them as such and free its payload from having to know how to set everything up. Change-Id: I1bb127c810e9ee077afc4227a6f316eaa53d6498 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3650 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-07-10ARMv7: Clean up console codeStefan Reinauer
- Guard console_init() with CONFIG_EARLY_CONSOLE in bootblock - Don't initialize console twice in the bootblock - remove printk in memory init that would mess up the UART - unconditionally run console_init() in romstage, as it is also unconditionally run in the bootblock. Change-Id: I8f0d60877433162367074d0e55e01f935fd81f8e Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3647 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10pit: Create an exynos5420 directory which is nearly a copy of exynos5250.Gabe Black
This change creates an exynos5420 directory with code that will eventually implement support for the exynos5420 cpu from Samsung. Currently it's a copy of the exynos5250 directory with the name changed. There are going to be some problems where headers in src/cpu/samsung/exynos-common include headers in the exynos5250 directory directly. Change-Id: Ia8d7244310d32499238bbc171c0c668ec48178e1 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3644 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10ARMv7: De-uboot-ify Exynos5250 GPIO codeStefan Reinauer
The Exynos GPIO code has three different APIs that, unfortunately, were widely used throughout the code base. This patch is cleaning up the mess. Change-Id: I09ccc7819fb892dbace9693c786dacc62f3f8eac Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3643 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10ARMv7: De-uboot-ify Exynos5250 codeStefan Reinauer
When starting the Exynos5250 port, a lot of unneeded u-boot code was imported. This is an attempt to get rid of a lot of unneeded code before the port is used as a basis for further ARM ports. There is a lot more that can be done, including cleaning up the 5250's Kconfig file. Change-Id: I2d88676c436eea4b21bcb62f40018af9fabb3016 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3642 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10samsung/exynos5250: unify codeStefan Reinauer
It turns out that the exynos5-common code previously imported from u-boot is not common code at all but very specific to the 5250 and not compatible with the 5450. Hence, unify the directories exynos5250 and exynos5-common. We will try to factor out common code while progressing with the 5450 port. Change-Id: Iab595e66fcd01eda8365c96fb8bef896f7602f03 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3641 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10Wield battle axe at ARM portStefan Reinauer
This patch unfortunately incorporates a number of changes, all of which are making future ARM ports easier. - drop cruft that came in with u-boot - move serial console from mainboard Kconfig to Exynos Kconfig - factor out non-board specific wakeup code - move generic bootblock code from mainboard to Exynos - actually call arch_cpu_init() - remove dead code - fix up copyright messages - remove snow_ prefix from a lot of code to reduce the noise when creating a new mainboard based on that code. Change-Id: Ic05326edf5a7e1a691c5ff841a604cb9e351b562 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3640 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10Rename hardwaremain() to main()Stefan Reinauer
... and drop the wrapper on ARMv7 Change-Id: If3ffe953cee9e61d4dcbb38f4e5e2ca74b628ccc Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3639 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10ARMv7: normalize ramstage code flowStefan Reinauer
In ram stage, all code flow should be tied to the resource allocator. Stuff that has to happen before everything else goes into the mainboard enable function in mainboard.c. This patch empties the main() wrapper around hardwaremain.c, allowing to get rid of this special case in the ARM port. Change-Id: Ide91a23f1043b64acf64471f180a2297f0f40d97 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3638 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10Provide support for setting up the framebuffer from EDIDRonald G. Minnich
Add three functions to edid.c: void set_vbe_mode_info_valid(struct edid *edid, uintptr_t fb_addr) takes an edid and uintptr_t, and fills in a static lb_framebuffer struct as well as setting the static vbe_valid to 1 unless some problem is found in the edid. The intent here is that this could be called from the native graphics setup code on both ARM and x86. int vbe_mode_info_valid(void) returns value of the static vbe_valid. void fill_lb_framebuffer(struct lb_framebuffer *framebuffer) copies the static edid_fb to lb_framebuffer. There is now a common vbe.h in src/include, removed the two special ones. In general, graphics in coreboot is a mess, but graphics is always a mess. We don't have a clean way to try two different ways to turn on a device and use the one that works. One battle at a time. Overall, things are much better. The best part: this code would also work for ARM, which also uses EDID. Change-Id: Id23eb61498b331d44ab064b8fb4cb10f07cff7f3 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3636 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-03Move select MMCONF_SUPPORT under northbridgeKyösti Mälkki
Move/remove MMCONF_SUPPORT reference under mainboard Kconfig, as that feature originates from northbridge and cannot be disabled for a single mainboard. Change-Id: I6d6861079876ddddaff90b10f18edb6936e93bd0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3589 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-26snow: Add a name to the serial console UART choice block.Gabe Black
This allows other boards to have the same choice block without confusing kconfig. Change-Id: Iea5a7f2d1c263aa7992f504b832ca9c862833c3f Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3293 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-05-08hardwaremain: drop boot_complete parameterStefan Reinauer
it has been unused since 9 years or so, hence drop it. Change-Id: I0706feb7b3f2ada8ecb92176a94f6a8df53eaaa1 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3212 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-05-06exynos5250/snow: deprecate time.hDavid Hendricks
This re-introduces 2fde966 (http://review.coreboot.org/#/c/3177/) which was reverted due to unsatisfied dependencies. time.h We Hardly Knew Ye. This deprecates time.h which is currently only used by Exynos5250 and Snow. The original idea was to try and unify some of the various timer interfaces and has been supplanted by the monotonic timer API. timer_us() is now obsolete. timer_start() is now mct_start() and is exposed in exynos5250/clk.h. Change-Id: I8e60105629d9da68ed622e89209b3ef6c8e2445b Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3201 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-04Revert "exynos5250/snow: deprecate time.h"David Hendricks
This reverts commit 2fde9668b47e74d1bfad2f1688a4481e6b966d04 Somehow this got merged before its dependencies. 3190 must be merged first, followed by 3176. However 3190 will fail while this patch is in. So the situation can't correct itself. Reverting this until the other two go in. Change-Id: I176f37c12711849c96f1889eacad38c00a8142c4 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3195 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-05-03exynos5250/snow: deprecate time.hDavid Hendricks
time.h We Hardly Knew Ye. This deprecates time.h which is currently only used by Exynos5250 and Snow. The original idea was to try and unify some of the various timer interfaces and has been supplanted by the monotonic timer API. timer_us() is now obsolete. timer_start() is now mct_start() and is exposed in exynos5250/clk.h. Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I14ebf75649d101491252c9aafea12f73ccf446b5 Reviewed-on: http://review.coreboot.org/3177 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-01Google/Snow: Revise bootblock initialization.Hung-Te Lin
It's fine to always start timer even in suspend/resume mode, so we can move the timer_start() back to the very beginning of boot procedure. That provides more precise boot time information. With that timer change, the wake up state test procedure can be simplified. Verified by building and booting firmware image on Google/Snow successfully, and then suspend-resume without problem (suspend_stress_test). Change-Id: I0d739650dbff4eb3a75acbbf1e4356f2569b487d Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/3151 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-01Google/Snow: Remove duplicated SPI1 initialization in bootblock.Hung-Te Lin
The firmware media source (SPI1) is already initialized by Exynos iROM. There is no need to do it again. Verified by building and booting Google/Snow successfully. Change-Id: I89390506aa825397c0d7e52ad7503f1cb808f7db Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/3147 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-30Google/Snow: Remove unnecessary serial console init code.Hung-Te Lin
The "console_init" does initialize UART driver (which will setup peripheral and pinmux) and print starting message. Duplicated initialization can be removed. Also, console_init (from console.c) is always linked to bootblock (and will do nothing if CONFIG_EARLY_CONSOLE is not defined) so it's safe to remove #ifdef. Verified by building and booting on Google/Snow, with and without CONFIG_EARLY_CONSOLE. Change-Id: I0c6b4d4eb1a4e81af0f65bcb032978dfb945c63d Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/3150 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-30Google/Snow: Temporary fix for resume failure.Hung-Te Lin
The DDR3 memory initialization (with "mem_reset" set on normal boot) will cause resume to be unstable, especially when X is running. System may show X screen for few seconds, then crash randomly and unable to recover - although text console may still work for a while. Probably caused by corrupted memory pages. 'mem_reset' (which refers to RESET# in DDR3 spec) should be enabled according to DDR3 spec. But it seems that on Exynos 5, memory can be initialized without setting mem_reset for both normal boot and resume - at least no known failure cases are found yet. So this can be a temporary workaround. Verified by booting a Google/Snow device with X Window and ChromeOS, entering browser session with fancy web pages, closing LID to suspend for 5 seconds, then re-opening to resume. Suspend/resume worked as expected. Also tried the "suspend_stress_test" with X running and finished 100 iterations of suspend/resume test without failure. Change-Id: I7185b362ce8b545fe77b35a552245736c89d465e Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/3148 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-29Google/Snow: Enable suspend/resume.Hung-Te Lin
Add the suspend/resume feature into bootblock and romstage. Note, resuming with X and touchpad driver may be still unstable. Verified by building and booting successfully on Google/Snow, and then executing the "suspend_stress_test" in text mode ("stop ui; suspend_stress_test") in Chromium OS, passed at least 20 iterations. Change-Id: I65681c42eeef2736e55bb906595f42a5b1dfdf11 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/3102 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-04-26google/snow: Revise romstage initialization code.Hung-Te Lin
Move board setup procedure to snow_setup_* functions, and Snow board-specific (wakeup) code to snow_* for better function names and comments. Verified by successfully building and booting on Google/Snow. Change-Id: I2942d75064135093eeb1c1da188a005fd255111d Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/3130 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-04-25google/snow: Add "wakeup" module for suspend/resume.Hung-Te Lin
The "wakeup" procedure will be shared by bootblock and romstage for different types of resume processes. Note, this commit does not include changes in romstage/bootblock to enable suspend/resume feature. Simply adding functions to handle suspend/resume. Verified by successfully building and booting Google/Snow firmware image. Change-Id: I17a256afb99f2f8b5e0eac3393cdf6959b239341 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/3129 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-25arm/exynos: Allow DRAM controller to be initialized without clearing RAM ↵Hung-Te Lin
content. To support suspend/resume, PHY control must be reset only on normal boot path. So add a new param "mem_reset" to specify that. Verified to boot successfully on Google/Snow. Change-Id: Id49bc6c6239cf71a67ba091092dd3ebf18e83e33 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/3128 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-23GOOGLE/SNOW: get graphics workingRonald G. Minnich
This adds support for display bring-up on Snow. It includes framebuffer initialization and LCD enable functions. Change-Id: I16e711c97e9d02c916824f621e2313297448732b Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3116 Tested-by: build bot (Jenkins)
2013-04-19google/snow: disable unused USB3.0 PLL to save powerDavid Hendricks
This PLL is unused and can be disabled to save about 250mW. Change-Id: I1be37304d6ea5ff78696e05ad1023ce3c57f636c Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3109 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-19google/snow: Minor clean-ups for display setup code in ramstageDavid Hendricks
This just cleans up a few areas: - Removed an unnecessary delay from exynos_dp_bridge_setup() - The delay at the end of exynos_dp_bridge_init() is necessary, so removed the comment suggesting that it might not be. - Simplified exynos_dp_hotplug Change-Id: I44150f5ef3958e333985440c1022b4f1544a93aa Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3113 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-19google/snow: enable clock gating to save powerDavid Hendricks
This enables clock gating to save power on unused IPs. Change-Id: I9ab2a2535ebb91bb4110390a6f055a67146bdbf9 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3110 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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