| Age | Commit message (Expand) | Author |
|---|---|---|
| 2015-09-24 | coreboot: move TS_END_ROMSTAGE to one spot | Aaron Durbin |
| 2015-09-23 | google: veyron: CBFS_SIZE to match the available size for Coreboot in ChromeOS | Paul Kocialkowski |
| 2015-09-08 | rk3288: Allow board-specific APLL (CPU clock) settings | David Hendricks |
| 2015-09-08 | veyron: Unify identical mainboards | Julius Werner |
| 2015-03-24 | veyron: Rename "veyron" board to "veyron_pinky" | Julius Werner |
| 2015-03-24 | rk3288: update romstage & mainboard | huang lin |
| 2015-03-24 | rk3288: add ddr driver | Jinkun Hong |
| 2015-03-24 | add make_idb.py & update bootblock | huang lin |
| 2015-03-20 | romstages: use common run_ramstage() | Aaron Durbin |
| 2015-03-16 | coreboot: rk3288: Add a stub implementation of the rk3288 SOC | jinkun.hong |
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index : coreboot | |
| Some coreboot project code with my work | vimacs |
| summaryrefslogtreecommitdiff |