coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-10-08	mb/google/volteer: disable TBT if no USB4 hardware available	Nick Vaccaro
2020-10-05	mb/google/hatch,dedede,volteer: enable CHROMEOS_DRAM_PART_NUMBER_IN_CBI	Nick Vaccaro
2020-10-05	mb, soc: change mainboard_get_dram_part_num() prototype	Nick Vaccaro
2020-09-22	mb/google: Drop unneeded empty lines	Elyes HAOUAS
2020-08-06	mb/google/volteer: add support for ddr4 memory	Nick Vaccaro
2020-07-26	src: Remove extra lines in license header	Elyes HAOUAS
2020-06-14	mb/google/volteer: Disable HDA PCI device when AUDIO=NONE	Duncan Laurie
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-04-28	mb/google/volteer: implement mainboard_get_dram_part_num()	Nick Vaccaro
2020-04-02	soc/intel/tigerlake: Reorganize memory initialization support	Furquan Shaikh
2020-04-01	soc/intel/tigerlake: Remove Jasper Lake SoC references	Aamir Bohra
2020-03-18	mainboard/google: Remove copyright notices	Patrick Georgi
2020-02-11	mb/google/volteer: use new Tiger Lake memory config	Nick Vaccaro