summaryrefslogtreecommitdiff
path: root/src/mainboard/google/volteer
AgeCommit message (Collapse)Author
2020-06-24mb/google/volteer/malefor: Update overridetree.cbWilliam Wei
1) Based on malefor schematics, disable unused I2C port, USB port, TBT PCIe 2) Add audio device to the tree BUG=b:150653745, b:154973095 TEST=FW_NAME=malefor emerge-volteer coreboot chromeos-bootimage Boot to kernel and check the devices' function worked properly. Signed-off-by: William Wei <wenxu.wei@bitland.corp-partner.google.com> Change-Id: I9ce465705e8b8f67ddbc9e4eb06c5a8bfac65fcb Reviewed-on: https://review.coreboot.org/c/coreboot/+/42246 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-24volteer: Create volteer2 variantNick Vaccaro
Create the volteer2 variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.1.1). Modified to alphabetize and update to duplicate latest volteer changes currently in the review and merge pipeline. Added the following missing files from the variants/volteer2/ folder: - gpio.c - include/variant/acpi/dptf.asl - acpi/mipi_camera.asl - Makefile.inc - memory/dram_id.generated.txt - memory/Makefile.inc - memory/mem_list_variant.txt - overridetree.cb BUG=b:159135047 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_VOLTEER2 Change-Id: I987c72b83dc993af248a753a2caa56be0f26c1ad Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42605 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-24volteer: Create delbin variantZhuohao Lee
Create the delbin variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.1.1). BUG=b:158797761 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_DELBIN Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Change-Id: Icf5fc6b9cc6a7c47e52103b2d396bcddb26adf50 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-22mb/google/volteer/variants/terrador: Enable Cmd MirrorDavid Wu
Enable CmdMirror for Terrador to achieve optimum routing from SoC to DRAMs BUG=b:156435028 BRANCH=none TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I0db9fff0dddf35c99a6cb2a90d40886ed8e18686 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-22mb/google/volteer/variants/volteer: clean up gpio.cNick Vaccaro
Remove an unneccessary comment and group the variant_early_gpio_table together based on GPIO group. Changed static variable name gpio_table to override_gpio_table to be more descriptive. BUG=none TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer to kernel. Change-Id: Iabe810df1e5a3df35e3543ab81b9fdb6f76c223a Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42577 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22mb/google/volteer: move volteer devices to overridetree.cbNick Vaccaro
Move the following volteer-specific devices from baseboard's devicetree.cb into volteer's overridetree.cb file: - Goodix Touchscreen - ELAN Touchscreen - ELAN Touchpad - SAR0 Proximity Sensor Adjust the other variant's overridetree.cb files to correspond to the changes made to the baseboard's devicetree.cb in this change. BUG=b:159241303, b:154646959 TEST='emerge-volteer coreboot chromeos-bootimage', flash and boot volteer to kernel and verify that the trackpad works. Change-Id: I30f8266ec87a7cde293c84d3e687d133207b8d59 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-22mb/google/volteer: update fw_config definitionNick Vaccaro
Update fw_config definition in devicetree.cb to match current definition for volteer. BUG=b:159157584 TEST=none Change-Id: I761893818231880d86fd13cfa61319157d06a7d5 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42331 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22mb/google/volteer: Disable D3Cold for TCSS along with pass through modeJohn Zhao
The pass through mode (SW CM) RTD3 is not supported until QS platform. D3Cold is needed to be disabled along with upstream TBT firmware signed_TGL_HR_4C_A0_rev6_pre4_SW_CM_PM_support_ENG_VER_perst_check_fix. This temporary patch will need to be reverted once PM RTD3 support is validated on QS platform. BUG=b:159050315 TEST=Verfiy PM S0ix along with upstream TBT firmware. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I98ed991e4185abf1f3168e33b099e0e97c9075f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42504 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Divya Sasidharan <divya.s.sasidharan@intel.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22mb/google/volteer: Override power limits with SKU-specific limitsTim Wawrzynczak
Using guidance from Intel, a new set of power limits (PL1, PL2 & PL4) are available for TGL-U. They are dependent upon the SKU of the CPU that the mainboard is running on. Volteer is updated here to use these new limits. To accomplish this, the SoC chip config's power_limits_config member was expanded to an array, which can be indexed by POWER_LIMITS_*_CORE macros. Just before power limits are applied, the correct set of them is chosen from the array based on System Agent PCI ID. Therefore, a TGL board should have two sets of power limits available in the devicetree. BUG=b:152639350 TEST=On a Volteer SKU4 (4-core), verified the following console output: CPU PL1 = 15 Watts CPU PL2 = 60 Watts CPU PL4 = 105 Watts Change-Id: I18a66fc3aacbb3ab594b2e3d6e2a4ad84c10d8f0 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-06-22mb/google/volteer: Change VCM and EEPROM configs for ov8856Daniel Kang
TGL RVP and Volteer use ov8856 camera module from different vendors. TGL RVP from Foxlink and Volteer from Sunny. ov8856 sensor is identical for the two modules but VCM and EEPROM are different. Originally, Volteer ACPI was set to align with Sunny module, GT9679. But it turned out GT9679 is compatible with Foxlink's DW9768. So Volteer camera ACPI configuration doesn't need to keep GT9679. BUG=b:158188369 BRANCH=none TEST=Build and boot volteer proto 2 board. Start a camera app and check user-facing camera functionalities. Signed-off-by: Daniel Kang <daniel.h.kang@intel.com> Change-Id: I792608f86a59b16545dfa4edf6508de7a444bb26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Daniel H Kang <daniel.h.kang@intel.corp-partner.google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-06-19tigerlake: add unique acpi device ids for dptfSumeet R Pawnikar
Add unique new acpi device ids for dptf for Tiger Lake soc based platforms and update volteer speficic dsdt.asl file accordingly. The Linux kernel driver expects these new acpi device ids for dptf functionalities. BUG=None BRANCH=None TEST=Build and boot on volteer system Change-Id: I7dbb812c0fc0f5084c98cf2752ce7ddce8e4d50e Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-19Kconfig: Escape variable to accommodate new Kconfig versionsPatrick Georgi
Kconfig 4.17 started using the $(..) syntax for environment variable expansion while we want to keep expansion to the build system. Older Kconfig versions (like ours) simply drop the escapes, not changing the behavior. While we could let Kconfig expand some of the variables, that only splits the handling in two places, making debugging harder and potentially messing with reproducible builds (e.g. when paths end up in configs), so escape them all. Change-Id: Ibc4087fdd76089352bd8dd0edb1351ec79ea4faa Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-06-18mb/google/volteer/variants/terrador: Disable EC SW syncDavid Wu
It is the reference board of TGL-Y platform, we want to disable EC SW sync for Proto stage, it would be re-enabled before EVT stage. BUG=b:156435028 TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ie7999e24e9c173d4870b35ce1728f3dcc8dcac29 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42090 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17mb/google/volteer: remove unused GPP_H23Nick Vaccaro
BUG=b:157567939 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer to kernel. Change-Id: I3046cf3a359e833a5d204f78ab84312e8665061f Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42411 Reviewed-by: Jes Klinke <jbk@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17mb/volteer: Set IomTypeCPortPadCfg default to 0x09000000Brandon Breitenstein
Temporary workaround for S0ix issues related to FSP's handling of 0 value. When IomTypeCPortPadCfg is 0 FSP completely skips any flow related to this value which seems to be causing issues with s0ix. This is still being debugged and a final solution will be made when available BUG=b:159151238 TEST=flash image with workaround to volteer and verify that s0ix cycles correctly. Change-Id: Id79dd1c49958389cdb666b3760abd821bc1973a8 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42268 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-14mb/google/volteer: Disable HDA PCI device when AUDIO=NONEDuncan Laurie
If there is no installed audio daughter board on volteer then the HDA driver in the kernel will crash on resume. In order to prevent this disable the PCI device when AUDIO=NONE probe match is true. BUG=b:147462631 TEST=boot on volteer and ensure that the PCI device at 0:1f.3 is gone Change-Id: I4a436e1b76418030bf635427e490b54a713fdd33 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-14mb/google/volteer/var/terrador: Update dq/dqs mappingsDavid Wu
Update dq/dqs mappings based on terrador schematics. BUG=b:156435028,b:151978872 BRANCH=none TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I97697a3dd9b88eaffe6e2b1be7bd346979cbc956 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-14mb/google/volteer: Enable thermal sensor 4 in DPTF for volteerDeepika Punyamurtula
Enables the fourth thermal sensor for fan in DPTF for volteer BRANCH=None BUG=b:149722146 TEST= On volteer system check `cat /sys/class/thermal/thermal_zone5/type` for TSR3 Signed-off-by: Deepika Punyamurtula <deepika.punyamurtula@intel.com> Change-Id: Ie11496828133aa71f1017f759516e2e5d3dff2d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-06-12mb/google/volteer/var/voxel: Add memory parts and generate DRAM IDsFurquan Shaikh
This change adds memory parts used by variant voxel to mem_list_variant.txt and generates DRAM IDs allocated to these parts. This variant is not yet supported by coreboot but DRAM IDs need to be generated for it. In the coming days, variant voxel will be added to coreboot. BUG=b:157732528 Change-Id: I8780beec987deb8fed11bb8f84275dcba4768514 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-06-12mb/google/volteer: Customize PCH VR settings for better Sx power savingsVenkata Krishna Nimmagadda
For Volteer mainboard, this patch set optimized values for PCH external VR settings and ext rail voltage/current, to achieve better power savings in sleep states. v1p05 and vnn power rails can be used as an alternative source by-passing vccin_aux during Sx. This by-pass feature, enables us to shutdown vccin_aux rail which is higher voltage rail compared to v1p05 and vnn. These both rails were disabled by default in FSP. Changes in this patch are: 1. v1p05 and vnn rails are enabled and enabled supported voltage types in S0i1, S0i2, S0i3, S3, S4, S5 states. They were disabled by default. 2. Icc Max for v1p05 changed to 500 mA from default 100 mA. 3. vnn rail's voltage is changed to 5 V from default 4.2 V. BUG=None BRANCH=None TEST="Build and boot volteer and check VR settings with Intel ITP-XDP debugger and verify approx 250 mW power savings in Sx" Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com> Change-Id: Ib46423872c956af9aaa92902fce552d5447237c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42223 Reviewed-by: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-11mb/google/volteer: Update DPTF TSR2 sensor ID for volteerDeepika Punyamurtula
Update DPTF_TSR2_SENSOR_ID to 2. Fixes the issue where TSR1 and TSR2 have the same DPTF_TSR#_SENSOR_ID value causing them to report the same temperature under /sys/class/thermal and also swap TSR0 and TSR1 in DTRT to match physical sensor in volteer schematics BRANCH=None BUG=b:149722146 TEST=On volteer system check TSR1 and TSR2 temperatures, should report different values `cat /sys/class/thermal/thermal_zone[3,4]/temp` Also verify other TSRs using `cat /sys/class/thermal/thermal_zone*/temp` and `ectool tempsinfo all ; ectool temps all` Signed-off-by: Deepika Punyamurtula <deepika.punyamurtula@intel.com> Change-Id: Idc5f35e4faf59b0ee726eb32a08eab4654fb342d Reviewed-on: https://review.coreboot.org/c/coreboot/+/42232 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-09mb/google/volteer: move volteer-specific GPIOs to variant gpio.cNick Vaccaro
- Move the GPIOs that are likely to be volteer-specific (mostly peripherals) to reside in variants/volteer/gpio.c so that variants don't have to override too many GPIO settings. - Modify malefor's gpio.c to adjust for the changes to baseboard's gpio.c. - Remove unused GPP_C3 (USB4_SMB_SCL) and GPP_C4 (USB4_SMB_SCA) settings. - Remove unused GPP_D9, GPP_D10, GPP_D11, and GPP_D12 settings. - Remove unused GPP_E8 (SLP_S0IX), COEX, WWAN, and SNDW related settings for malefor. - Remove unused GPP_R4 (HDA_RST_L) setting. BUG=b:157597158 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer SKU4 to kernel. Change-Id: Ib2f384f539d55a3a8d4a7608336ef22aca3d8c4f Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41797 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-06-06mb/google/volteer: Drop spd/ folders from variants/Furquan Shaikh
Now that volteer is moved to using the auto-generated SPDs, we no longer need the spd/ folder under each variant. Hence, this change drops the spd/ folders and the SPD files within them. BUG=b:156126658 Change-Id: Icb36adeb11fd68a84df5b225db32fb8d840a530f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41619 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06mb/google/volteer: Switch to using auto-generated SPDsFurquan Shaikh
This change switches volteer and family to using auto-generated SPDs obtained using gen_spd.go and gen_part_id.go. BUG=b:147321551,b:155423877 Change-Id: I9ed48f0b51714b072a0459d0b70b5417a49db54f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-06-06mb/google/volteer/var/volteer: Use auto-generated Makefile.inc using ↵Furquan Shaikh
gen_part_id.go This change adds mem_list_variant.txt that contains the list of memory parts used by volteer and Makefile.inc generated by gen_part_id.go using mem_list_variant.txt. In the final change of the series, all volteer variants will be switched from using the current SPDs to new auto-generated SPDs. Differences in auto-generated SPD from current SPD are as follows: Part: K4U6E3S4AA-MGCL Byte# Current New Explanation 6 0x95 0x94 Signal loading is not used by MRC. Set bits 1:0 to 00. 16 0x48 0x00 Signal loading is not used by MRC. Set to 0x00. 19 0x0F 0xFF As per JEDEC spec, tckMax should be 100ns. So, value should be 0xff as per datasheet. 21,22 0x55,0x00 0x54,0x05 As per datasheet, part supports CAS latencies 20,24,28,32,36. So value should be 0x54, 0x05. 24 0x8C 0x87 taa is .468ns * CAS-36 which results in byte 24 being 0x87 as per datasheet. 123 0x00 0xE5 Fine offset for taa. Expected value is 0xE5 as per datasheet. 124 0x7F 0x00 Fine offset for tckMax. Expected value is 0x00 as per datasheet. 125 0xE1 0xE0 Fine offset for tckMin. As per datasheet tckMin is 0.468ns. So, this comes out to be 0xE0. Part: K4UBE3D4AA-MGCL Byte# Current New Explanation 6 0xB5 0xB4 Signal loading is not used by MRC. Set bits 1:0 to 00. 16 0x48 0x00 Signal loading is not used by MRC. Set to 0x00. 19 0x0F 0xFF As per JEDEC spec, tckMax should be 100ns. So, value should be 0xff as per datasheet. 123 0x00 0xE5 Fine offset for taa. Expected value is 0xE5 as per datasheet. Part: H9HCNNNBKMMLXR-NEE Byte# Current New Explanation 6 0x95 0x94 Signal loading is not used by MRC. Set bits 1:0 to 00. 16 0x48 0x00 Signal loading is not used by MRC. Set to 0x00. 19 0x0F 0xFF As per JEDEC spec, tckMax should be 100ns. So, value should be 0xff as per datasheet. 21,22 0x55,0x00 0x54,0x05 As per datasheet, part supports CAS latencies 20,24,28,32,36. So value should be 0x54, 0x05. 24 0x8C 0x87 taa is .468ns * CAS-36 which results in byte 24 being 0x87 as per datasheet. 123 0x00 0xE5 Fine offset for taa. Expected value is 0xE5 as per datasheet. 124 0x7F 0x00 Fine offset for tckMax. Expected value is 0x00 as per datasheet. 125 0xE1 0xE0 Fine offset for tckMin. tckMin is calculated as (1/4267)*2 which comes out to be 0.46871. Some datasheets round this down to 0.468 and others round it up to 0.469. JEDEC spec uses 0.468. As per that, this value comes out to be 0xE0. Part: H9HCNNNFAMMLXR-NEE Byte# Current New Explanation 4 0x15 0x16 As per datasheet, density is 16Gb per logical channel. So value should be 0x16. 6 0xF9 0xB8 This device has 4 logical dies instead of 8. Also, signal loading is not used by MRC. 16 0x48 0x00 Signal loading is not used by MRC. Set to 0x00. 20,21, 0x92,0x55, 0x12,0x29, As per datasheet, part supports CAS 22 0x00 0x15 latencies 6,10,16,22,26,32,36,40. So value should be 0x12,0x29,0x15. 24 0x8C 0x96 taa is .468ns * CAS-40 which results in byte 24 being 0x96 as per datasheet. 29,30 0xE0,0x0B 0xC0,0x08 As per datasheet, this corresponds to 280ns in MTB units which is 0x08C0. 31,32 0xF0,0x05 0x60,0x04 As per datasheet, this corresponds to 140ns in MTB units which is 0x04C0. 123 0x00 0xE2 Fine offset for taa. Expected value is 0xE2 as per datasheet. 124 0x7F 0x00 Fine offset for tckMax. Expected value is 0x00 as per datasheet. 125 0xE1 0xE0 Fine offset for tckMin. tckMin is calculated as (1/4267)*2 which comes out to be 0.46871. Some datasheets round this down to 0.468 and others round it up to 0.469. JEDEC spec uses 0.468. As per that, this value comes out to be 0xE0. Part: MT53E1G32D2NP-046 WT:A Byte# Current New Explanation 4 0x15 0x16 As per datasheet, density is 16Gb per logical channel. So value should be 0x16. 5 0x21 0x29 As per datasheet, this part has 17row address bits and 10column address bits. This results in 0x29. 6 0xB5 0x94 This device has 2 logical dies. Also, MRC does not use signal loading. 16 0x48 0x00 Signal loading is not used by MRC. Set to 0x00. 12 0x0A 0x02 As per datasheet, this is 1rank and 16-bit wide channel. So, value should be 0x02. 21,22 0x55,0x00 0x54,0x05 As per datasheet, part supports CAS latencies 20,24,28,32,36. So value should be 0x54, 0x05. 24 0x8C 0x87 taa is .468ns * CAS-36 which results in byte 24 being 0x87 as per datasheet. 29,30 0xC0,0x08 0xE0,0x0B As per datasheet, this corresponds to 380ns in MTB units which is 0x0BE0. 31,32 0x60,0x04 0xF0,0x05 As per datasheet, this corresponds to 190ns in MTB units which is 0x05F0. 123 0x00 0xE5 Fine offset for taa. Expected value is 0xE5 as per datasheet. 124 0x7F 0x00 Fine offset for tckMax. Expected value is 0x00 as per datasheet. 125 0xE1 0xE0 Fine offset for tckMin. As per datasheet tckMin is 0.468ns. So, this comes out to be 0xE0. BUG=b:147321551,b:155423877 Change-Id: I3998b2cd91020130bacf371fce9b0d307304acbe Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-06-06mb/google/volteer/var/halvor: Use auto-generated Makefile.inc using ↵Furquan Shaikh
gen_part_id.go This change adds mem_list_variant.txt that contains the list of memory parts used by halvor and Makefile.inc generated by gen_part_id.go using mem_list_variant.txt. In the final change of the series, all volteer variants will be switched from using the current SPDs to new auto-generated SPDs. Differences in auto-generated SPD from current SPD are as follows: Part: H9HKNNNCRMBVAR-NEH Byte# Current New Explanation 4 0x16 0x15 As per datasheet, density is 8Gb per logical channel. So value should be 0x15. 6 0xB9 0x94 Signal loading is not used by MRC. Set bits 1:0 to 00. 2 channels 2 dies. Hence, 0x94 19 0x0F 0xFF As per JEDEC spec, tckMax should be 100ns. So, value should be 0xff as per datasheet. 29,30 0xE0,0x0B 0xC0,0x08 As per datasheet, this corresponds to 280ns in MTB units which is 0x08C0. 31,32 0xF0,0x05 0x60,0x04 As per datasheet, this corresponds to 140ns in MTB units which is 0x0460. 125 0xE1 0xE0 Fine offset for tckMin. tckMin is calculated as (1/4267)*2 which comes out to be 0.46871. Some datasheets round this down to 0.468 and others round it up to 0.469. JEDEC spec uses 0.468. As per that, this value comes out to be 0xE0. Part: MT53E1G64D4SQ-046 WT:A Byte# Current New Explanation 5 0x21 0x29 As per datasheet, this part has 17row address bits and 10column address bits. This results in 0x29. 6 0xB9 0x94 Signal loading is not used by MRC. Set bits 1:0 to 00. 2 channels, 2 dies. Hence, 0x94. 19 0x0F 0xFF As per JEDEC spec, tckMax should be 100ns. So, value should be 0xff as per datasheet. 125 0xE1 0xE0 Fine offset for tckMin. As per datasheet tckMin is 0.468ns. So, this comes out to be 0xE0. BUG=b:147321551,b:155423877 Change-Id: I28b065a00380516d8686279a92ef68b9f17e2f65 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41616 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06mb/google/volteer/var/malefor: Use auto-generated Makefile.inc using ↵Furquan Shaikh
gen_part_id.go This change adds mem_list_variant.txt that contains the list of memory parts used by malefor and Makefile.inc generated by gen_part_id.go using mem_list_variant.txt. In the final change of the series, all volteer variants will be switched from using the current SPDs to new auto-generated SPDs. Differences in auto-generated SPD from current SPD are as follows: Part: K4U6E3S4AA-MGCL Byte# Current New Explanation 6 0x95 0x94 Signal loading is not used by MRC. Bits 1:0 set to 0. 16 0x48 0x00 Signal loading is not used by MRC. Set to 0x00. 19 0x0F 0xFF As per JEDEC spec, tckMax should be 100ns. So, value should be 0xff as per datasheet. 21,22 0x55,0x00 0x54,0x05 As per datasheet, part supports CAS latencies 20,24,28,32,36. So value should be 0x54, 0x05. 24 0x8C 0x87 taa is .468ns * CAS-36 which results in byte 24 being 0x87 as per datasheet. 123 0x00 0xE5 Fine offset for taa. Expected value is 0xE5 as per datasheet. 124 0x7F 0x00 Fine offset for tckMax. Expected value is 0x00 as per datasheet. 125 0xE1 0xE0 Fine offset for tckMin. As per datasheet tckMin is 0.468ns. So, this comes out to be 0xE0. BUG=b:155239397,b:147321551 Change-Id: I8b8bdc55314f538aff4dd1944a0b745357744d8c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41615 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06mb/google/volteer/var/ripto: Use auto-generated Makefile.inc using ↵Furquan Shaikh
gen_part_id.go This change adds mem_list_variant.txt that contains the list of memory parts used by ripto and Makefile.inc generated by gen_part_id.go using mem_list_variant.txt. In the final change of the series, all volteer variants will be switched from using the current SPDs to new auto-generated SPDs. Differences in auto-generated SPD from current SPD are as follows: Part: K4U6E3S4AA-MGCL Byte# Current New Explanation 6 0x95 0x94 Signal loading is not used by MRC. Bits 1:0 set to 0. 16 0x48 0x00 Signal loading is not used by MRC. Set to 0x00. 19 0x0F 0xFF As per JEDEC spec, tckMax should be 100ns. So, value should be 0xff as per datasheet. 21,22 0x55,0x00 0x54,0x05 As per datasheet, part supports CAS latencies 20,24,28,32,36. So value should be 0x54, 0x05. 24 0x8C 0x87 taa is .468ns * CAS-36 which results in byte 24 being 0x87 as per datasheet. 123 0x00 0xE5 Fine offset for taa. Expected value is 0xE5 as per datasheet. 124 0x7F 0x00 Fine offset for tckMax. Expected value is 0x00 as per datasheet. 125 0xE1 0xE0 Fine offset for tckMin. As per datasheet tckMin is 0.468ns. So, this comes out to be 0xE0. BUG=b:155239397,b:147321551 Change-Id: Ibb06443a5c7fd80915f66b806cdd7c3ae1275b05 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41614 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-04mb/google/volteer: Create voxel variantDavid Wu
Create the voxel variant of the volteer reference board BUG=b:157879197 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_VOXEL Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I8ba5412be211730db84675927c500238cb20ff3d Reviewed-on: https://review.coreboot.org/c/coreboot/+/41968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-06-03mb/google/volteer/halvor: initialize gpio setting and update overridetree.cbFrank Wu
Based on schematic and gpio table of halvor, generate gpio setting and overridetree.cb for halvor. BUG=b:153680359 TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage Verify that the image-halvor.bin is generated successfully. Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Ic6bd018551be58945742d1a6e7f7c5560f218e40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-02mb/google/volteer/ripto: Add audio devices to the treeDuncan Laurie
The ripto board is still being used for testing so make sure it supports the same audio config as volteer. BUG=b:147462631 TEST=build ripto variant Change-Id: Iabeb73307418dc16b12fa60ad26923cd9f6e1f3a Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
2020-06-02mb/google/volteer: Add firmware configuration probing for audioDuncan Laurie
For all of the audio devices in devicetree.cb add the probe matches that will determine if the device should be enabled or not based on the selected audio daughter board type. AUDIO=MAX98357_ALC5682I_I2S: enable max98357 and alc5628, disable others AUDIO=MAX98373_ALC5682I_I2S: enable max98373 and alc5682, disable others AUDIO=MAX98373_ALC5682_SNDW: enable soundwire devices, disable others BUG=b:147462631 TEST=test different device present in ACPI based on fw_config value: > AUDIO=NONE ectool cbi set 6 0x00000000 4 2 > AUDIO=MAX98357_ALC5682I_I2S ectool cbi set 6 0x00000100 4 2 > AUDIO=MAX98373_ALC5682I_I2S ectool cbi set 6 0x00000200 4 2 > AUDIO=MAX98373_ALC5682_SNDW ectool cbi set 6 0x00000300 4 2 Change-Id: I5492e8cddcff3ba01023b0daef02be3508d347b0 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41216 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02mb/google/volteer: Add firmware configuration tableDuncan Laurie
Add the current firmware configuration table for the volteer mainboard and define some actions based on probe results for audio: - When I2S options are selected disable the SoundWire GPIOs. - When SoundWire is enabled disable the I2S GPIOs. - When no audio is enabled disable all the GPIOs. BUG=b:147462631 TEST=Test that GPIOs are configured as expected based on the current value of the fw_config field in cbi. Change-Id: I179f8b6436be83a2b37911777764bd26a0d404b7 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41215 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02mb/google/volteer: Reorganize audio codecsDuncan Laurie
- Move all audio devices from baseboard to the volteer variant. - Add max98373 devices and enable the driver - Disable everything in FSP and let coreboot configure GPIOs. BUG=b:147462631 TEST=this change makes all audio devices show up in ACPI, so this was tested by ensuring that all audio devices are present in ACPI. Change-Id: Ic654ea52a549053622603aa8c81fb37577d4e011 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-02mb/google/volteer: Enable TCSS DMA0 for VolteerJohn Zhao
This explicitly enables TCSS DMA0 controller and disables TBT PCIe2 and PCIE3 since they are unused on volteer. BUG=:b:146624360 TEST=Built and booted on Volteer. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I05cc9e3964d8037d433fca443be6e8d5b444bbce Reviewed-on: https://review.coreboot.org/c/coreboot/+/41387 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28mb/google/volteer: Add PMC.MUX.CONx devices to devicetree for VolteerTim Wawrzynczak
Volteer's MUX connections are known, and can now be described in ACPI tables. Port 1 has the only oddity, with SBU lines staying fixed in the CC1 orientation. TEST=Dump SSDT tables on Volteer, and confirm (coalesced for brevity): Scope (\_SB.PCI0.PMC) { Device (MUX) { Name (_HID, "INTC105C") Device (CON0) { Name (_ADR, 0) Name (_DSD, Package() { Package () { "usb2-port-number", 9 }, Package () { "usb3-port-number", 1 }, }) } Device (CON1) { Name (_ADR, 1) Name (_DSD, Package() { Package () { "usb2-port-number", 4 }, Package () { "usb3-port-number", 2 }, Package () { "sbu-orientation", "normal" }, ... } } } Change-Id: Id361b2df07e87ad72b6a59a686977b3f424e8ecf Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-05-28Revert "Revert "mb/google/volteer: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ↵Furquan Shaikh
ports"" This reverts commit 1726fa1f0ce474cde32e8b32be34a212aff3ffba. Reason for revert: Resource allocator is split into old(v3) and new(v4). So, this change to enable hotplug resource allocator for volteer can land back. BUG=b:149186922 Change-Id: Ib6a4df610b045fbc885c70bff3698a032b79f770 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41468 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-28mb/google/volteer: Create terrador variantDavid Wu
Create the terrador variant of the volteer reference board BUG=b:156435028 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_TERRADOR Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I088861d1f8b7b4ee8de1e5ab6c7d3109ffd0531b Reviewed-on: https://review.coreboot.org/c/coreboot/+/41718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-05-28mb/google/volteer: Select SX9310 driver in KconfigDuncan Laurie
There are SX9310 devices present in devicetree.cb but the driver is not enabled so it is not getting used. Change-Id: I625233013a2e14eaf758e56027774fbf5df3bc83 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41700 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-26mb/google/volteer: fix some white space nitsNick Vaccaro
Convert spaces to tabs in volteer variant makefiles, and remove empty comment lines from file headers. BUG=none TEST="emerge-volteer coreboot chromeos-bootimage", flash and verify volteer boots to kernel. Change-Id: I6c818c3adcc55ce89707efff6dd9a6bce512daa5 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41587 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-26soc/intel/tigerlake: Remove MIPI clock setting from devicetreeSrinidhi N Kaushik
In Tiger Lake we have support for enabling MIPI clocks at runtime in ACPI. Hence remove setting pch_islclk from devcietree and chip.h. Also update functions which reference pch_isclk. BUG=b:148884060 Branch=None Test=build and boot volteer and verify camera functionality Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I6b3399172c43b4afa4267873ddd8ccf8d417ca16 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41570 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-26mb/google/volteer: Enable D3HotEnable and D3ColdEnable for VolteerJohn Zhao
This explicitly enables both of TCSS D3HotEnable and D3ColdEnable from Volteer devicetree.cb setting. BUG=:b:146624360 TEST=Built and booted on Volteer. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I1a168ad87169c0f6633704c55c9293aa25710188 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-05-26mb/google/volteer: Enable ELAN trackpad wake suspend functionWilliam Wei
BUG=b:156990317 TEST=emerge-volteer coreboot chromeos-bootimage Boot to kernel and check the ELAN trackpad can wake up unit from suspend. Signed-off-by: William Wei <wenxu.wei@bitland.corp-partner.google.com> Change-Id: If4bea8a9742f7533be2e51b855cc39ca77d73608 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-22mb/google/volteer: Add SoundWire codecs to volteer variantDuncan Laurie
Enable drivers for SoundWire codecs and define the topology in the devicetree for the volteer variant with the SoundWire daughter board connected. +------------------+ +-------------------+ | | | Headphone Codec | | Intel Tigerlake | +--->| Realtek ALC5682 | | SoundWire | | | ID 1 | | Controller | | +-------------------+ | | | | Link 0 +----+ +-------------------+ | | | Left Speaker Amp | | Link 1 +----+--->| Maxim MAX98373 | | | | | ID 3 | | Link 2 | | +-------------------+ | | | | Link 3 | | +-------------------+ | | | | Right Speaker Amp | +------------------+ +--->| Maxim MAX98373 | | ID 7 | +-------------------+ This was tested by booting the firmware and dumping the SSDT table to ensure that all SoundWire ACPI devices are created as expected with the properties that are defined in coreboot under \_SB.PCI0: HDAS - Intel Tigerlake HDA PCI device HDAS.SNDW - Intel Tigerlake SoundWire Controller HDAS.SNDW.SW01 - Realtek ALC5682 - Headphone Codec HDAS.SNDW.SW13 - Maxim MAX98373 - Left Speaker Amp HDAS.SNDW.SW17 - Maxim MAX98373 - Right Speaker Amp BUG=b:146482091 Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I7782059807416369e0e1ba0d4d7c79dcab0fcbc5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40894 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-22mb/google/volteer: Add overridetree.cb for volteer variantDuncan Laurie
Instead of only using the baseboard devicetree add a placeholder overridetree for volteer and refer to it in Kconfig. This will allow us to add the volteer specific devices here instead of at the baseboard level. BUG=b:146482091 Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I7788a5473fc2275a9791fb27e0e4018a0efcd0f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40893 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-21mb/google/volteer: set DRAM Max Cycle Time to 15Nick Vaccaro
The DRAM Max Cycle Time (tCKmax) for Samsung's K4UBE3D4AA-MGCL DRAM part should be set to 0xF. BUG=b:157178553, b:156555863 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot a SKU4 volteer to the kernel and run "memtester 6G 100" and verify it completes successfully without error and does not crash. Change-Id: Id95b19fe261e3f57a52a43055acab99af66b14ab Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41634 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-21mb/google/volteer: fix error in generic SPDNick Vaccaro
The SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex SPD contained an incorrect SDRAM Max Cycle Time (0 instead of 0x0f). After fixing that error, I noticed that two generic SPDs could be collapsed into one, so I removed one of the duplicate generic SPDs (SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_16Row_DDP_4267.spd.hex), and changed Makefile to collapse volteer's DRAM ID 2 into ID 0. BUG=b:156126658, b:156058720 TEST=Flash and boot a ripto to kernel. Also verified that ripto can boot successfully to the kernel at 4267 MT/sec with FSP built in debug mode with RMT enabled. Change-Id: Ib52bf674ebf91854d3d078015aa640aa7ee98a6f Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41345 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-20tigerlake: enable DPTF functionality for volteerSumeet R Pawnikar
Enable DPTF functionality for volteer platform BRANCH=None BUG=b:149722146 TEST=Built and tested on volteer system Change-Id: I385fb409ccd291d97369295ff99f21c9430880f9 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41427 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-20soc/intel/tigerlake: Move PMC PCI resources under PMC deviceTim Wawrzynczak
Historically in coreboot, the PMC's fixed PCI resources were described by the System Agent (the MMIO resource), and eSPI/LPC (the I/O resource). This patch moves both of those to a new Intel SoC-specific function, soc_pmc_read_resources(). On TGL, this new function takes care of providing the MMIO and I/O resources for the PMC. BUG=b:156388055 TEST=verified on volteer that the resource allocator is aware of and does not touch these two resources: ("PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1") Also verify that the MEM resource is described in the coreboot table: ("BIOS-e820: [mem 0x00000000fe000000-0x00000000fe00ffff] reserved") Verified the memory range is also untouchable from Linux: ("system 00:00: [mem 0xfe000000-0xffffffff] could not be reserved") Change-Id: Ia7c6ae849aefaf549fb682416a87320907fb3fe3 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41385 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-20mb/google/volteer: Fix camera dsdt config for ov2740Daniel Kang
Link frequency and a format was not correct for volteer proto 2 ov2740 user-facing camera. The link frequency is calculated in the following way. (max frame width * max frame height * max fps * data format in bps / number of lanes / data rate) + max 35% of overhead For ov2740, (1920 * 1080 * 60 * 10 / 2 / 2) = 311Mhz. 360Mhz after adding 18% of overhead. BUG=b:148428976 BRANCH=none TEST=Build and boot volteer proto 2 board. Start a camera app and check user-facing camera functionalities. Signed-off-by: Daniel Kang <daniel.h.kang@intel.com> Change-Id: I3b51826e123dec394c1b4eb9a1c5b64b8b11459e Reviewed-on: https://review.coreboot.org/c/coreboot/+/41157 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Dossym Nurmukhanov <dossym@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-18 13:22:28 +0000