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3.6 schematic will separate TS power from eDP PP3300 to GPIO
for power control and correct GPIO assignment from GPIO_90 to
GPIO_32 instead.
BUG=b:161579679
BRANCH=zork
TEST=emerge-zork coreboot
Change-Id: Ieef67e1d04201c5d9e1dc625c519e6d0307c55f0
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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GPIO_144 is REPORT_EN pin for the touchscreen controller where 1 means
enable operation and 0 means stop operation. Override tree exposes
this pin as stop GPIO. Thus, it needs to be configured as active low
i.e. 0 = active (stop), 1 = inactive (enable report).
Change-Id: I349123655260349b78d2f75f846da0ce1dc966fc
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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v3.6+ of reference schematics have moved to using active low polarity
for touchscreen GPIO. This change sets the default polarity in
override tree accordingly to active low. To support boards from older
builds, variant_touchscreen_update() already updates the polarity to
active high.
BUG=b:161937506
Change-Id: I370bdb27ea5d0601612d13b515113a6048018964
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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TS:
ELAN 5015M
G2 GTCH7503 HID TS
TP:
ELAN i2c-hid touchpad
BUG=b:161579679
BRANCH=master
TEST=1. emerge-zork coreboot chromeos-bootimage
2. power on proto board successfully
3. TP/TS are functional
Change-Id: I54aa16d433b6d71a39cca2ddd026a33e4741320f
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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BUG=b:164757545
BRANCH=master
TEST=1. emerge-zork coreboot chromeos-bootimage
2. power on proto board successfully
3. measure i2c freq by scope is close to 400kHz
Change-Id: Icb27ff8a4960caaebc542ee4e507f1611da5a77e
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Create the dirinboz variant of the dalboz reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.1.1).
BUG=b:161579679
BRANCH=master
TEST=util/abuild/abuild -p none -t google/zork -x -a
make sure the build includes GOOGLE_DIRINBOZ
Change-Id: I33c03080ffbe0bca61acf4144417b9f5fff6389f
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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