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2020-08-06mb/google/zork: Configure GPIO_89 as PAD_NCFurquan Shaikh
GPIO_89 was marked as EN_DEV_BEEP_L in pre-v3.6 schematics, but it was never really used on any of the zork variants. Starting with v3.6, GPIO_89 is left unused in schematics. This change configures GPIO_89 as PAD_NC in baseboard GPIO table. Since EN_DEV_BEEP_L still needs to be driven high to allow speakers to work, GPIO_89 is configured as PAD_GPO driven high on pre-v3.6 schematics. BUG=b:62108046 Change-Id: I026cd6cb598667ce6e115c3ec9357a6a56051d39 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44190 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-06mb/google/zork: Add touchscreen power controlFurquan Shaikh
This change adds support for touchscreen power control using: * GPIO_90 for trembyle based boards * GPIO_32 for dalboz based boards By default, baseboard tables configure these GPIOs as PAD_GPO driven low and override trees expose these pads as enable_gpio to be used by ACPI power resource. In order to support pre-v3.6 boards, override tables configure these pads as PAD_NC and drop the enable_gpio setting from device tree based on board version. BUG=b:161935640, b:162747210 Change-Id: Iba5e36b65b44ea11613b4d5fc8f13ce6433f83ab Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44193 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-06mb/google/zork: Switch USI_RESET to active low polarity for v3.6+Furquan Shaikh
v3.6 of reference schematics have switched the polarity of reset signal to touchscreen controller from active high to active low. This change updates the default configuration in baseboard gpio tables to set the reset GPIO to output low and override tables in variants to set the reset GPIO to output high. Additionally, devicetree by default exposes ACTIVE_LOW configuration for reset GPIO. In order to support pre-v3.6 boards, reset GPIO is updated to ACTIVE_HIGH based on board version. BUG=b:161937506 Change-Id: I092f274d8eb1920a1cd6d3eccbe8f26b0b28928a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-06mb/google/zork: Use dev_nested_path for dmic gpio updateJosie Nordrum
Create function update_dmic_gpio to update DMIC GPIO for ACP machine and use find_dev_nested_path function for consistency. BUG=None BRANCH=None TEST=None Change-Id: I96cf207f24c6117d98ff2bf7e6e5cd282489e805 Signed-off-by: Josie Nordrum <josienordrum@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44158 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-06mb/google/zork: Make SW changes for HP_INT_ODL in schematic v3.6Josie Nordrum
HP_INT_ODL is no longer connected to CODEC_GPI in schematic version 3.6. Split variant_audio_update into update_dmic_gpio and update_hp_int_odl. Changed GPIO_29 from PAD_NC to PAD_GPI in Trembyle. Changed GPIO_84 from PAD_NC to PAD_GPI for Dalboz. Changed HP_INT_ODL to appropriate pin in both boards devicetree.cb. BUG=b:161938476 BRANCH=None TEST=None Cq-Depend: chromium:2335424 Change-Id: I05ffb063ab99823d07be6eaa911efbde3cc4ff55 Signed-off-by: Josie Nordrum <josienordrum@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44157 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-06mb/google/zork: Add kconfigs to check schematic version 3.6Josie Nordrum
Added VARIANT_SUPPORTS_PRE_V3_6_SCHEMATICS and VARIANT_MIN_BOARD_ID_V3_6_SCHEMATICS. Added helper functions to check if variant uses v3.6 and if variant uses CODEC GPI. BUG=b:161938476 BRANCH=None TEST=None Change-Id: If86e1ea3c02db354c7b410f1bbc1daacb483cc51 Signed-off-by: Josie Nordrum <josienordrum@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44156 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-05mb/google/vilboz: update telemetry settings for vilbozPeichao Wang
update telemetry value for SDLE test result. BUG=b:160698427 BRANCH=None TEST=emerge-zork coreboot Change-Id: Icce57f9be2732ff79f336daa6c447a30247366cf Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-05mb/google/zork/ezkinil: Fix ELAN touchscreen ACPI nodeLucas Chen
a. USI_REPORT_EN is no longer set to high in coreboot. Instead GPIO_144 is exposed as stop_gpio in ACPI to allow OS to control this pad as required. b. Add Delay after stop_gpio Low - 300ms BUG=b:162263398 Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Change-Id: I3d4dcb6e5cae5d9515abfd415315ec4114ca80b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44107 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-05mb/google/zork: update DRAM SPD table for dirinbozKevin Chiu
DRAM support list 0x00 HYNIX HMA851S6CJR6N-VK 0x01 HYNIX H5ANAG6NCMR-VKC 0x02 Samsung K4A8G165WC-BCTD 0x03 Samsung K4AAG165WB-MCTD 0x04 Samsung K4A8G165WC-BCWE 0x05 HYNIX H5AN8G6NDJR-XNC 0x06 HYNIX H5ANAG6NCMR-XNC 0x07 Micron MT40A512M16TB-062E:J 0x08 Micron MT40A1G16KD-062E:E 0x09 Samsung K4AAG165WA-BCTD 0x0A Samsung K4AAG165WA-BCWE BUG=b:161579679 BRANCH=master TEST=build Change-Id: Ib9fa5ae98568d659326d431a4006174a343fa299 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-04mb/google/zork/var/vilboz: Enable support for garaged stylusFurquan Shaikh
This change adds support for pen insert/eject operations in S0 and wake on pen eject from S3 for vilboz. BUG=b:157628650 Change-Id: I7ba0881b67dfb67c032667d591f7d1806a50af22 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-03mb/google/zork: Pass oscout system clk to rt5682Akshu Agrawal
In kernel clk for AMD SoCs we expose a generic clk by the name oscclk1. This oscclk1 is a fixed 48Mhz frequency clk in RV. In Zork oscout system clock is linked to rt5682 mclk. Setting mclk-name to oscclk1 tells rt5682 driver its mclk is oscclk1. Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> BUG=b:158906189 TEST=rt5682 driver get the correct clk and tested audio playback Change-Id: Ic565e8e0573e085e5759b2d3688cc0a4533b67fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/44010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-03mb/google/zork: Add Samsung K4AAG165WA-BCTD SPDKevin Chiu
For dirinboz DRAMID 0x9: K4AAG165WA-BCTD BUG=b:161579679 BRANCH=master TEST=build Change-Id: I28c0d23f96c5b9c975ffead3a1cac66cbda8c293 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-07-30mb/amd,google/mandolin,zork: Set EFS SPI platform configMatt Papageorge
Set platform defaults for SPI settings in Kconfig for EFS. BUG=b:158755102 TEST=Build and boot test on Tremblye and Morphius. Verify values in output image in a hex editor. Measure 1st x86 timestamp, perf improves by over a second. Change-Id: I765dada14700f4800263d2d3844af07fad0e5b71 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43303 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-30mb/google/zork: remove indirection for dxio lane configurationAaron Durbin
There was a mix of open coding DXIO logical lane numbers and clkreq pins. And there are separate macros depending on the baseboard as well as processor type. Remove the indirection and supply the values directly in the descriptors. BUG=b:162423378 Change-Id: I779cb0a514e3b668265e6039d6e7e7bd0f3d49ed Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-07-30mb/google/zork/var/ezkinil: Configure boot media for new SKUsLucas Chen
Configure the correct eMMC present flag for Ezkinil new added sku_id. 0x5A020015 NVME present 0x5A020016 eMMC present 0x5A020017 eMMC present BUG=b:159761042 TEST:none Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Change-Id: I1b89cc4568283d5dbebf0ab7ac578368d3a3637e Reviewed-on: https://review.coreboot.org/c/coreboot/+/43753 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-30mb/google/zork: add USB over-current pin mapping to devicetreeFelix Held
BUG=b:162010077 Change-Id: Iba3e3ec62cdfd818077017abd28fa754c2ae7797 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-29mb/google/zork: update stapm parameter for berknipKevin Chiu
sustained_power_limit = 12w fast_ppt_limit = 24w slow_ppt_limit = 20w BUG=b:162377903 BRANCH=master TEST=emerge-zork coreboot chromeos-bootimage Change-Id: I9baf9990e26edbbadfba85bc16b380c46684033d Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-28mb/google/zork: Add Bluetooth reset gpios to devicetreeRob Barnes
Add bluetooth reset gpio 143 to dalboz baseboard devicetree Add bluetooth reset gpio 14 to trembyle baseboard devicetree Remove bluetooth reset_gpio when not supported on a specific board variant. BUG=b:157580724 TEST=Boot Ezkinil with Realtek 8822CE, observe log [ 12.240720] Bluetooth: af_bluetooth.c:bt_init() HCI device and connection manager initialized [ 12.249272] Bluetooth: hci_sock.c:hci_sock_init() HCI socket layer initialized [ 12.256520] Bluetooth: l2cap_sock.c:l2cap_init_sockets() L2CAP socket layer initialized [ 12.264575] Bluetooth: sco.c:sco_init() SCO socket layer initialized [ 12.273700] usb 3-2: GPIO lookup for consumer reset [ 12.273702] usb 3-2: using ACPI for GPIO lookup [ 12.273705] acpi device:18: GPIO: looking up reset-gpios [ 12.273707] acpi device:18: GPIO: looking up reset-gpio [ 12.273711] acpi device:18: GPIO: _DSD returned device:18 0 0 0 [ 12.273737] gpio gpiochip0: Persistence not supported for GPIO 14 [ 12.273960] usbcore: registered new interface driver btusb Change-Id: I14e3ef099d5b8f48c915b41284039b3508dec975 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-26mb/google/vilboz: Tune I2C bus 3 clockpeichao.wang
Tune I2C bus3 frequency and insure it meets I2C spec. BUG=b:161650117 TEST=flash coreboot to the DUT and actual measured I2C bus3 make sure it meet Spec. Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: Ifa9f0bce723f55a12fd2313788c995f8326e3e7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/43661 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26mb/google/zork: remove ACPI_FADT_RESET_REGISTER from fadt_flagsFelix Held
This applies what commit 79572e4f32f844f60338d1aafdba6b94f4111a5c does to the devicetree settings of the zork devices. Change-Id: Ife94818d771f137e56c51ad1598148f60fcf5345 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43820 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26amd/picasso: rework USB2 PHY tune parameter handlingFelix Held
BUG=b:161923068 Change-Id: I67f23c0602e345fbd806e661a4462cf07f93ef64 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43783 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25soc/amd/picasso: don't apply unconfigured USB2 PHY tune parametersFelix Held
Since FSP pre-populates the UPD struct with the non-zero default values, coreboot shouldn't set them to zero in the case that they aren't configured in the board's devicetree. Since all parameters being zero is a valid case, this patch adds another devicetree option that applying the devicetree settings for the USB2 PHY tuning depends on being set. BUG=b:161923068 Change-Id: I66e5811ce64298b0644d2881420634a8ce1379d7 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43781 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23mb/google/zork: Don't expose reset GPIO for touchscreen to OSRaul E Rangel
The Raydium ACPI entry currently provides a reset GPIO and an _ON/_OFF method to the kernel. These are contradictory. The ownership of the GPIO should be mutually exclusive between either the OS or the FW. Since we have two methods exposed this causes the OS to reset the TS twice. Once using the _ON method, and once using the GPIO. Additionally the _ON method is waiting for 20ms after reset while the OS driver uses a 50ms delay. The Raydium TS datasheet specifies 20ms for FW ready time, so the OS driver is adding additional padding. The reference design has a 32ms rise time on the reset line. So without this patch, the OS tries to reset the TS using the _ON method and it waits for 20ms. This is not enough time for the reset line to reach high, let alone account for the FW ready time. The OS driver then tries to reset the device by toggling the GPIO. It waits 50ms which is still 2ms less than required. This CL removes the GPIO from being exported in the _CRS so the OS driver won't try and reset the device. It also increases the reset delay by 32ms to account for the rise time. This isn't a complete fix. I think that the slow rise time is causing some kind of metastability in the TS reset hardware. Using a script to bind and unbind the TS driver, the TS device becomes unresponsive after ~200 iterations. The only way to reset the device is to power cycle. The TS power is also not currently controlled by the power resource. This means that we have no guarantee over when the reset line is toggled. This will lead to issues while spending and resuming. BUG=b:160854397 TEST=Boot trembyle and make sure TS works. Suspend/Resume trembyle 300+ times. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I23131be5d7109eed660a8bd6e2c156c015aa3c4e Reviewed-on: https://review.coreboot.org/c/coreboot/+/43467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-23mb/google/zork/variants/dalboz: Use HS200 for eMMCEric Peers
Earlier versions of Dalboz did not correctly handle HS400. One fix was to add stitching vias, but these boards did not have them. b/156539551 Another possible fix is to add tuning parameters including drive strength, but that is still a WIP. b/158959725 This should correct OS load failures in the meantime by running the bus slower. BUG=b:158845662 TEST=build, flash, boot sku 0x5a80000c to OS BRANCH=None Signed-off-by: Eric Peers <epeers@google.com> Change-Id: Ia3e7a641bde04c5a7be29bf91c38dd8c110ed17a Reviewed-on: https://review.coreboot.org/c/coreboot/+/43572 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23zork: Create dirinboz variantKevin Chiu
Create the dirinboz variant of the dalboz reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.1.1). BUG=b:161579679 BRANCH=master TEST=util/abuild/abuild -p none -t google/zork -x -a make sure the build includes GOOGLE_DIRINBOZ Change-Id: I33c03080ffbe0bca61acf4144417b9f5fff6389f Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-07-23mb/google/zork: Fix Goodix touchscreen ACPI nodeFurquan Shaikh
This change does the following: a. USI_REPORT_EN is no longer set to high in coreboot. Instead GPIO_144 is exposed as stop_gpio in ACPI to allow OS to control this pad as required. b. Appropriate delays are added for power-down sequencing: - Delay after REPORT_EN is disabled - 1ms - Delay after RESET is asserted - 1ms BUG=b:159501288 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: If4d12fa0d4f4e5123d8fdccdabda996dcafa4523 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-23mb/google/zork/var/morphius: Change hid and desc for Goodix touchscreenFurquan Shaikh
Morphius uses Goodix touchscreen and not G2 touchscreen. This change updates hid and desc properties in devicetree accordingly. BUG=b:159501288 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I2527fa5409bb127ac225c6fb2a5f1bc24895f6cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/43700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-23mb/google/zork: Drop TODO for GPIO_91Furquan Shaikh
GPIO_91 is added to ACPI using the device tree entry for codec. So, this change drops the TODO from GPIO table. Change-Id: I9c2e91465ab554126531f8512028360ae5fb316d Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-23mb/google/zork: Configure all pads in ramstage for dalboz referenceFurquan Shaikh
This change configures all missing pads in ramstage for dalboz reference. This ensures that the state of all pads is set correctly for the payload/OS. Also, all the pads for the platform are configured in baseboard gpio table in ramstage to ensure that variants can override any pads if required. BUG=b:154351731 Change-Id: Ia30da908d3827177a7b3594ffba38bff81018ab9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-23mb/google/zork: Configure all pads in ramstage for trembyle referenceFurquan Shaikh
This change configures all missing pads in ramstage for trembyle reference. This ensures that the state of all pads is set correctly for the payload/OS. Also, all the pads for the platform are configured in baseboard gpio table in ramstage to ensure that variants can override any pads if required. BUG=b:154351731 Change-Id: Idd827b6a4f995546493596f22249f8699bdf526b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-23mb/google/zork: Remove unnecessary PULL_UP from early_gpio_tableFurquan Shaikh
This change drops PULL_UP configured on pads in early_gpio table since these pads have external pulls. BUG=b:154351731 Change-Id: Id270e7b4f83dfa942655f513776a3b1c15c9678d Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-23amd/picasso: rename PCIe descriptor to DXIO descriptorFelix Held
Most of the DXIO descriptors are used to configure PCIe engines and lanes, but on Picasso system some of the DXIO lanes can also be configured as SATA or XGBE ports. Change-Id: I28da1b21cf0de1813d87a6873b8d4ef3c1e0e9dd Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43675 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23vc/amd/fsp/picasso: add logical to lane number in port descriptor structFelix Held
The lane numbers in the PCIe/DXIO descriptor are the logical and not the physical ones, so add logical to the corresponding field names of the fsp_pcie_descriptor struct. Change-Id: I7037fed225119218e87593932815aff815e83ff8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-22mb/google/zork: Modify Woomax variantKane Chen
Update Woomax configuration including GPIO, memory SPD table, I2C devices and USB type C. BUG=b:158343602 BRANCH=None TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I55ba995d9438551d45cb9e17f92b5089ccf4a5fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/43497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-21mb/googlz/zork: Drop unnecessary PULL_UPs in variant overridesFurquan Shaikh
This change drops the pulls configured on override GPIOs as they already have external pull-ups. Also, pads which are unused are configured as PAD_NC. BUG=b:154351731 Change-Id: I8da5d51af25bbe2694c21ecb0868c9cc387243cb Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-07-20mb/google/zork: Delete sleep.aslRaul E Rangel
These methods are empty and the kernel treats these as optional. BUG=b:153001807, b:154756391 TEST=Suspend and resume trembyle Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I5f2b375c1186951f95b7ac44dc7158a0299013a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43465 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20mb/google/zork: Drop unnecessary PULL_UPs for dalboz referenceFurquan Shaikh
This change drops internal pulls for dalboz reference configured on pads which already have external pull-ups in hardware. GPIO_0(PWR_BTN_L): Pulled up to PP3300_A GPIO_2(WAKE_L): Pulled up to PP3300_A GPIO_10: Unused. Changed to PAD_NC. GPIO_11(EC_IN_RW_OD): Pulled up to PP3300_A GPIO_12(USI_INT_ODL): Pulled up to PP3300_A GPIO_16(USB_OC0_L): Pulled up to PP3300_A GPIO_17(USB_OC1_L): Pulled up to PP3300_A GPIO_21(EMMC_CMD): Pulled up to PP1800_S0 GPIO_22(EC_FCH_SCI_ODL): Pulled up to PP3300_A GPIO_31(EC_AP_INT_ODL): Pulled up to PP1800_A GPIO_32: Unused. Changed to PAD_NC. GPIO_113(I2C2_SCL): Pulled up to PP3300_S0 GPIO_114(I2C2_SDA): Pulled up to PP3300_S0 GPIO_129(KBRST_L): Pulled up to PP1800_S0 GPIO_92(CLK_REQ0_L): Pulled up to PP3300_S0 GPIO_115(CLK_REQ1_L): Pulled up to PP3300_S0 GPIO_116(CLK_REQ2_L): Pulled up to PP3300_S0 BUG=b:154351731 Change-Id: I62e9dbac7a55efa1e055983a7c126168ee516151 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-20mb/google/zork: Drop unnecessary PULL_UPs for trembyle referenceFurquan Shaikh
This change drops internal pulls for trembyle reference configured on pads which already have external pull-ups in hardware. GPIO_0(PWR_BTN_L): Pulled up to PP3300_A GPIO_2(WAKE_L): Pulled up to PP3300_A GPIO_10: Unused. Changed to PAD_NC. GPIO_12(USI_INT_ODL): Pulled up to PP3300_A GPIO_16(USB_OC0_L): Pulled up to PP3300_A GPIO_17(USB_OC1_L): Pulled up to PP3300_A GPIO_21(EMMC_CMD): Pulled up to PP3300_A GPIO_22(EC_FCH_SCI_ODL): Pulled up to PP3300_A GPIO_31(EC_AP_INT_ODL): Pulled up to PP1800_A GPIO_90: Unused. Changed to PAD_NC. GPIO_113(I2C2_SCL): Pulled up to PP3300_S0 GPIO_114(I2C2_SDA): Pulled up to PP3300_S0 GPIO_129(KBRST_L): Pulled up to PP1800_S0 GPIO_130(EC_IN_RW_OD): Pulled up to PP3300_S0 GPIO_92(CLK_REQ0_L): Pulled up to PP3300_S0 GPIO_115(CLK_REQ1_L): Pulled up to PP3300_S0 GPIO_132(CLK_REQ4_L): Pulled up to PP3300_S0 BUG=b:154351731 Change-Id: Id84b801e019eede7ef543c24aac968f3ef99b3fd Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43526 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17mb/google/zork/var/vilboz: Use AMDI1015 HID for I2S machine deviceFurquan Shaikh
Vilboz requires a different HID than rest of the zork variants. Hence, this change sets the HID to AMDI1015 for I2S machine device in vilboz overridetree.cb. BUG=b:157708581 Change-Id: Ibae343f21cf8f0c782dc8a461f69172bf0da7eba Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43545 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17mb/google/zork: Switch to using newly added i2s_machine_dev driverFurquan Shaikh
This change switches zork devices to use the newly added i2s_machine_dev driver in devicetree rather than passing dmic_select_gpio in SoC config. BUG=b:157708581 Change-Id: I76c633694cbfb454c081ab2a4af4765bfbbae16b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-17mb/google/zork: Drop mainboard.aslFurquan Shaikh
This change drops mainboard.asl from zork because none of the objects defined in it are used. BUG=b:153879530 Change-Id: If5440bcbce39b4461b44acaec69561663b1ea329 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43519 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17soc/amd/picasso: Move PMOD global variable to globalnvs.aslFurquan Shaikh
Global variable `PMOD` that stores the interrupt mode used by OS is required by all mainboards. This change moves the variable definition to globalnvs.asl under picasso. Additionally, ACPI spec says that BIOS should assume interrupt mode as PIC until _PIC() method is called by OS. Thus, this change also updates the default value of PMOD as 0 i.e. PIC mode. BUG=b:153879530 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I731c03d965882281a7a23f55894451210ba72274 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43514 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17mb/google/zork: correct wake gpe value for gpio 9Aaron Durbin
GPIO_9 is associated with gevent 22. Correct all the misconfigurations and use macros for clarity as to what bit offset is being used instead of open coding things. BUG=b:161205804 Change-Id: Ic4cfd62763d72d12a55f89585f24e07df6af0f4f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43516 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17mb/google/zork: Enable ACP_PME_EN and ACP_I2S_WAKE_ENFurquan Shaikh
This change enables ACP_PME_EN and ACP_I2S_WAKE_EN for dalboz and trembyle boards using devicetree settings. BUG=b:161328042,b:146317284 Change-Id: Ie367a9ba878a1892177df874bbcb8005efeb0880 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43496 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16soc/amd/picasso: remove unused fadt_pm_profile devicetree settingFelix Held
commit 56da63c3dc3f50cfac541c779b608e1bae9e635c removed overriding that field in the FADT. Change-Id: I0c8ff9ab125129dc856949c47a3a0c14e4109c73 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43417 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16soc/amd/picasso/acpi,mb/{zork,mandolin}: Stop clearing PciExpWakeStatusRaul E Rangel
The kernel already clears this: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/master:src/third_party/kernel/v5.4/drivers/acpi/acpica/hwregs.c;l=390 No reason to have the firmware do it as well. BUG=b:153001807, b:154756391 TEST=Build Trembyle, boot, suspend, and resume and didn't see any ACPI errors. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia5c79fb95dc885eaef8abc4257b6ba18c1ef1b66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-16soc/amd/picasso,mb/{zork,mandolin}: Remove invalid UPWS variableRaul E Rangel
PMx0EE is not defined in the Picasso PPR. BUG=b:153001807, b:154756391 TEST=None Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I98caf0cd2d0bdcf19de2b945dcf74f5cf7354769 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-16mb/google/zork: Move variant_pcie_gpio_configure() to bootblockFurquan Shaikh
On zork, bootblock is part of RW firmware in non-recovery mode, so PCIe GPIOs can be configured early on in bootblock rather than waiting until romstage. This change moves the call to variant_pcie_gpio_configure() to happen in bootblock and drops romstage.c file. BUG=b:154351731 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ic515304f35fe5623d58d6000efcb11fb9039e137 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43476 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16mb/google/zork: Drop variant_romstage_gpio_table()Furquan Shaikh
gpio_set_stage_rom table is now configuring only PCIe related GPIOs in romstage. This change moves the configuration of PCIe related GPIOs to variant_pcie_gpio_configure() to keep all the configuration for WiFi and non-WiFi PCIe pads in one place. It also drops the function variant_romstage_gpio_table() as it is unused. BUG=b:154351731 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ib1c41ba141dce6b52b6e0a250a3aa07c296068aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/43475 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16mb/google/zork: Drop redundant romstage GPIO tableFurquan Shaikh
Now that the power and reset GPIO configuration for non-PCIe devices is dropped from romstage GPIO table, the tables for pre-v3 and v3 version of schematics are exactly same. So, this change drops the duplicate table and also removes the check for v3 schematics when configuring the pads in romstage. BUG=b:154351731 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I67ca9f587c3f47912393ebaf38badcc9d76cc393 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-07 04:51:06 +0000