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2018-11-05mainboard: Remove unneeded include <console/console.h>Elyes HAOUAS
Change-Id: Ib3aafcc586b1631a75f214cfd19706108ad8ca93 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29285 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-02google/kukui: Add board id supportTristan Shieh
Get board id from AUXIN4 and RAM code from AUXIN3. BUG=b:80501386 BRANCH=none TEST=AUXIN4 is 0.074v and AUXIN3 is 0.212v on P0. AUXIN4 is 0.212v and AUXIN3 is 0.212v on P1. Change-Id: I50533e851d2fae66ae8c5e4e1aa36708d9058e94 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/29062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-11-02mb/google/sarien: Enable Wilco ECDuncan Laurie
The Sarien mainboard uses the newly added Wilco EC. - enable CONFIG_EC_GOOGLE_WILCO - add the device and host command ranges to the devicetree - have the mainboard SMI handlers call the EC handlers - add EC and SuperIO devices to the ACPI DSDT - call the early init hook for serial setup Change-Id: Idfc4a4af52a613de910ec313d657167918aa2619 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-11-02mb/google/sarien: Add Arcada variantDuncan Laurie
Add a variant of the Sarien board called Arcada. This is currently very similar to Sarien with differences in PCIe, USB, and GPIO usage. Change-Id: I432d2ba99558e960d4e775c809cc8bf6aa1a56bf Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29410 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-02mb/google/sarien: Add new mainboardDuncan Laurie
Sarien is a new board using Intel Whiskey Lake SOC. It also uses the newly added Wilco EC, enabled in a separate commit. Sarien is not a true reference board, it is just one variant of a very similar design. For that reason it is not considered the baseboard but rather a standalone variant. Change-Id: I2e38f617694ed2c2ef746ff8083f2bfd58cbc775 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-02mb/google/poppy/variants/nami: Enable radium touchscreen supportRen Kuo
Enable the radium touchscreen support BUG=b:117960394 BRANCH=master TEST= 1. emerge-nami coreboot chromeos-bootimage 2. boot up on ekko DUT to check touchscreen device by evtest /dev/input/event3: Raydium Touchscreen Change-Id: I16167d5d3ce6eac9d64832b52bb1945999a63a90 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29365 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-01sb/intel/common: Create a common implementation of `acpi_fill_madt()`Tristan Corrick
The function `acpi_fill_madt()` is identical among all the Lynx Point boards and sb/intel/bd82x6x, so share a common function between them. Earlier Intel platforms have similar implementations of this function. The common implementation might only need minor alterations to support them. Tested on an ASRock H81M-HDS and Google Peppy (variant of Slippy). No issues arose from this patch. Change-Id: Ife9e3917febf43d8a92cac66b502e2dee8527556 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/29388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-01sb/intel/lynxpoint: Add a common platform.asl fileTristan Corrick
The platform.asl file is copied from sb/intel/bd82x6x, and also matches the contents deleted from each mainboard's platform.asl. Tested on an ASRock H81M-HDS and a Google Peppy board (variant of Slippy). No issues arose from this patch. Change-Id: I539e401ce9af83070f69147526ca3b1c122f042c Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/29386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-01sb/intel/lynxpoint: Automatically generate the ACPI PCI routing tableTristan Corrick
This patch is based on a8a9f34e9b7b ("sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tables") Tested on an ASRock H81M-HDS. The generated _PRT object looks correct, and the system doesn't show any issue when running. The following assignments occur: ACPI_PIRQ_GEN: PCI: 00:02.0: pin=0 pirq=0 ACPI_PIRQ_GEN: PCI: 00:03.0: pin=0 pirq=0 ACPI_PIRQ_GEN: PCI: 00:14.0: pin=0 pirq=0 ACPI_PIRQ_GEN: PCI: 00:16.0: pin=0 pirq=0 ACPI_PIRQ_GEN: PCI: 00:1a.0: pin=0 pirq=0 ACPI_PIRQ_GEN: PCI: 00:1b.0: pin=0 pirq=6 ACPI_PIRQ_GEN: PCI: 00:1c.0: pin=0 pirq=0 ACPI_PIRQ_GEN: PCI: 00:1c.1: pin=1 pirq=1 ACPI_PIRQ_GEN: PCI: 00:1c.2: pin=2 pirq=2 ACPI_PIRQ_GEN: PCI: 00:1c.3: pin=3 pirq=3 ACPI_PIRQ_GEN: PCI: 00:1d.0: pin=0 pirq=7 ACPI_PIRQ_GEN: PCI: 00:1f.2: pin=1 pirq=3 ACPI_PIRQ_GEN: PCI: 00:1f.3: pin=2 pirq=2 Also tested on a Google Peppy board. The following assignments occur: ACPI_PIRQ_GEN: PCI: 00:02.0: pin=0 pirq=0 ACPI_PIRQ_GEN: PCI: 00:03.0: pin=0 pirq=0 ACPI_PIRQ_GEN: PCI: 00:14.0: pin=0 pirq=2 ACPI_PIRQ_GEN: PCI: 00:1b.0: pin=0 pirq=6 ACPI_PIRQ_GEN: PCI: 00:1c.0: pin=0 pirq=0 ACPI_PIRQ_GEN: PCI: 00:1d.0: pin=0 pirq=3 ACPI_PIRQ_GEN: PCI: 00:1f.2: pin=0 pirq=6 ACPI_PIRQ_GEN: PCI: 00:1f.3: pin=1 pirq=2 ACPI_PIRQ_GEN: PCI: 00:1f.6: pin=2 pirq=1 A diff of the _PRT object for the Google Peppy board is below. The code used in the diff has been modified for clarity, but the semantics remain the same. To summarise the diff: * The disabled PCIe root ports are no longer included. * The LPC controller is no longer included, as it has no interrupt pin. The pins for the remaining LPC devices are each one less. Perhaps the original _PRT object was incorrect? * The SDIO device is no longer included, as it is disabled. * The Serial IO devices are no longer included, but that is due to a separate issue I am having with this system (the devices don't show up under Linux regardless of this patch). In short: their omission is not a fault of this patch. --- pre/_PRT +++ post/_PRT @@ -1,301 +1,157 @@ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table { If (PICM) { - Return (Package (0x12) + Return (Package (0x09) { Package (0x04) { 0x0002FFFF, Zero, Zero, 0x10 }, Package (0x04) { 0x0003FFFF, Zero, Zero, 0x10 }, Package (0x04) { 0x0014FFFF, Zero, Zero, 0x12 }, Package (0x04) { 0x001BFFFF, Zero, Zero, 0x16 }, Package (0x04) { 0x001CFFFF, Zero, Zero, 0x10 }, - Package (0x04) - { - 0x001CFFFF, - One, - Zero, - 0x11 - }, - - Package (0x04) - { - 0x001CFFFF, - 0x02, - Zero, - 0x12 - }, - - Package (0x04) - { - 0x001CFFFF, - 0x03, - Zero, - 0x13 - }, - Package (0x04) { 0x001DFFFF, Zero, Zero, 0x13 }, Package (0x04) { 0x001FFFFF, Zero, Zero, 0x16 }, Package (0x04) { 0x001FFFFF, One, Zero, 0x12 }, Package (0x04) { 0x001FFFFF, 0x02, Zero, 0x11 - }, - - Package (0x04) - { - 0x001FFFFF, - 0x03, - Zero, - 0x10 - }, - - Package (0x04) - { - 0x0015FFFF, - Zero, - Zero, - 0x14 - }, - - Package (0x04) - { - 0x0015FFFF, - One, - Zero, - 0x15 - }, - - Package (0x04) - { - 0x0015FFFF, - 0x02, - Zero, - 0x15 - }, - - Package (0x04) - { - 0x0015FFFF, - 0x03, - Zero, - 0x15 - }, - - Package (0x04) - { - 0x0017FFFF, - Zero, - Zero, - 0x17 } }) } Else { - Return (Package (0x12) + Return (Package (0x09) { Package (0x04) { 0x0002FFFF, Zero, ^LPCB.LNKA, Zero }, Package (0x04) { 0x0003FFFF, Zero, ^LPCB.LNKA, Zero }, Package (0x04) { 0x0014FFFF, Zero, ^LPCB.LNKC, Zero }, Package (0x04) { 0x001BFFFF, Zero, ^LPCB.LNKG, Zero }, Package (0x04) { 0x001CFFFF, Zero, ^LPCB.LNKA, Zero }, - Package (0x04) - { - 0x001CFFFF, - One, - ^LPCB.LNKB, - Zero - }, - - Package (0x04) - { - 0x001CFFFF, - 0x02, - ^LPCB.LNKC, - Zero - }, - - Package (0x04) - { - 0x001CFFFF, - 0x03, - ^LPCB.LNKD, - Zero - }, - Package (0x04) { 0x001DFFFF, Zero, ^LPCB.LNKD, Zero }, Package (0x04) { 0x001FFFFF, Zero, ^LPCB.LNKG, Zero }, Package (0x04) { 0x001FFFFF, One, ^LPCB.LNKC, Zero }, Package (0x04) { 0x001FFFFF, 0x02, ^LPCB.LNKB, Zero - }, - - Package (0x04) - { - 0x001FFFFF, - 0x03, - ^LPCB.LNKA, - Zero - }, - - Package (0x04) - { - 0x0015FFFF, - Zero, - ^LPCB.LNKE, - Zero - }, - - Package (0x04) - { - 0x0015FFFF, - One, - ^LPCB.LNKF, - Zero - }, - - Package (0x04) - { - 0x0015FFFF, - 0x02, - ^LPCB.LNKF, - Zero - }, - - Package (0x04) - { - 0x0015FFFF, - 0x03, - ^LPCB.LNKF, - Zero - }, - - Package (0x04) - { - 0x0017FFFF, - Zero, - ^LPCB.LNKH, - Zero } }) } } Change-Id: Id3f067cbf7c7d649fbbf774648d8ff928cb752a4 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/29381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-01mb/google/fizz/variants/karma: Rename kalista to karmaDavid Wu
Change the variant name from kalista to karma. According to the CL:1298319, the baseboard name is kalista and the board name is karma. BUG=none BRANCH=master TEST=emerge-kalista coreboot chromeos-bootimage Change-Id: Idea295cc14249721a6dc0fc4e2ef6470d43e16eb Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29314 Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-01src: Add missing include <stdint.h>Elyes HAOUAS
Change-Id: Idf10a09745756887a517da4c26db7a90a1bf9543 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-10-31Veyron: add Hynix H9CCNNNBKTMLBR-NTD ddr with RAMID '00Z1'Loop_Wu
Confirm with RK, H9CCNNNBKTMLBR-NTD uses this sdram config. sdram-lpddr3-hynix-4GB.inc BUG=b:117967129 BRANCH=master TEST=None Change-Id: I98afc33fd2cb61343be0dcdc007add75bee9c2af Signed-off-by: Loop_Wu <Loop_Wu@asus.com> Reviewed-on: https://review.coreboot.org/29366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-10-31mb/google/poppy/variants/nami: Perform PL2 setting for syndraJohn Su
According to syndra thermal table, PL2 need to check cpu id. Set up syndra PL2 value. 1. KBL_U PL2 is 25w. 2. KBL_R PL2 is 29w. Refer to b:116836990#comment10. BUG=b:116836990 TEST=The thermal team verify OK Change-Id: I766a886121a089683565608252b4c176c70e88a3 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Shelley Chen <shchen@google.com>
2018-10-30mb/google/kahlee: Disable IOMMUMartin Roth
Unfortunately Stoney has an issue where enabling the IOMMU causes a 10%-50% decrease in the integrated graphics performance. It is also disabled by default on other stoney platforms. BUG=b:118612241 TEST=Verify that IOMMU is disabled. Change-Id: Ia396c7227cb21461ec8afbdf746721d4fb28083d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/29342 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-30src: Add missing include <stdint.h>Elyes HAOUAS
Change-Id: I6a9d71e69ed9230b92f0f330875515a5df29fc06 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29312 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-29mb/google/poppy/variants/nami: Add field to identify single channel DDRShelley Chen
Variants of Nami need to accommodate single channel DDR. Will use GPP_D10 on nami for identification. GPP_D10 will return 1 when device is using single channel DDR and 0 when using dual channel DDR. BUG=b:117194353 BRANCH=None TEST=dmidecode | grep Channel and make sure that the correct number of channels gets returned. Change-Id: If86ab2c5404c4e818ce496ea935227ab5e51730a Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/29233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-25mb/google/kahlee/irq_tables.c: Prefer using '"%s...", __func__'Richard Spiegel
In function write_pirq_routing_table(), the function name is used in a print string. Use __func__ instead. BUG=b:117642170 TEST=Build grunt. Change-Id: Ibf8673c5b2cda1105aae1edb46f6589d55208c50 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-10-25mb/google/fizz/variants/kalista: Add variant for kalistaDavid Wu
Add a new variant of fizz for the kalista board. Key differences from baseboard include: - GPIO changes - devicetree.cb changes BUG=b:117066935 BRANCH=master TEST=Build (as initial setup) Change-Id: I808c5e0883049575cbedd181c249a78a833fa96a Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29205 Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-25mb/google/fizz: Enable use of override devicetreeFurquan Shaikh
This change enables override device tree for Fizz to allow variants to provide their own overrides and also moves I2C5 realtek node to fizz/overridetree.cb since it doesn't apply to some variants being added for Fizz. Change-Id: Ia1a069fc539b51a22882ef94b55baf5bf7cd302f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/29242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2018-10-25google/kukui: Support recovery modeTristan Shieh
Get recovery mode switch from EC and pass it to payload. BUG=b:80501386 BRANCH=none Test: Boots correctly on Kukui. Change-Id: Ib92afca885e5a97ec4646f55f2279ef56a61af5a Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/29190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2018-10-24mb/google/kahlee: Enable 2T mode for liarachris wang
Liara auto restart issue is caused by memory access error and consequent kernel panic. To solve this issue, revert the CL:1243666 (Disable NbP-state on Liara) and use 2T mode instead. BUG=b:116082728 TEST=verify the 2T mode is enabled/boot into ChromeOS and no auto restart/run memtester passed 10 cycle. Change-Id: I3a96276d88ffb70530d72b15c07b59a01cc6209a Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-24mb/google/octopus/variants/fleex: Update DPTF parametersJohn Su
1. Update PSV values for cpu and sensers. 2. Change PL1 min value from 3w to 4.5w. 3. Change TSR2 TRT source from charger to CPU. Refer to 112448519#comment31. BUG=b:112448519 TEST=Build coreboot for Octopus board Change-Id: I7c7df0f54374fdaa4cf57d5c255d841d7db38cfc Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-10-24mb/google/poppy/var/nocturne: Use CRFP as device name for FP deviceFurquan Shaikh
This change uses CRFP ACPI name for FP device since user space utilities expect this name for triggering different actions. BUG=b:112974410 BRANCH=nocturne Change-Id: I63309227c916b43917e529c223cf738fc3baa209 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/29231 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-24mainboard/google/poppy/variants/rammus: Enable touchscreenkane_chen
On rammus, set GPIO GPP_C22 to 1 for touchscreen power on. And add touchscreen device "PNP0C50" to I2C0. According to touchscreen spec, device power on initialization takes 105 ms, so set "generic.enable_delay_ms" to 120. We found there is i2c error log pop up when we set delay time to be 110ms or 105ms. If we set delay time to be 120ms. System will not pop up i2c error log. BUG=b:115944726 BRANCH=master TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, and make sure touchscreen works. Change-Id: Ibce552d04991e85c99ae3a0a92455fc747d9fced Signed-off-by: YanRu Chen <kane_chen@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-24mb/google/octopus: Use DIMM_INFO_PART_NUMBER_SIZE for part_num_storeFurquan Shaikh
This change uses DIMM_INFO_PART_NUMBER_SIZE to decide the size of part_num_store that holds the number of DRAM part. It ensures that host advertises the supported size to read part number from the EC. BUG=b:115697578 Change-Id: I8439a301fc037b0acdc8b1226ad04d2f363838ef Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/29241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
2018-10-23mb/google/poppy: add the smi_events backZhuohao Lee
Before entering the OS, the AP relies on the smi handler to shutdown the system when the lid closes. Without the smi_events setting, the AP will not receive the smi handler. As a result, the AP won't shutdown and will always keep in S0. This problem is caused by the https://review.coreboot.org/c/coreboot/+/28983 and this patch adds the smi_events back to support the smi handler for the lid close. BRANCH=master BUG=b:115572596 TEST=test_that -b ${BOARD} ${IP} firmware_ECLidShutdown Change-Id: Id82311a8ccd109f9c26516f59a45bdf34da98529 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/29191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-10-23src: Remove unneeded whitespaceElyes HAOUAS
Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-10-23mb/kahlee mb/gardenia: Remove smbus.asl includeRichard Spiegel
The file soc/amd/stoneyridge/acpi/smbus.asl has 0 bytes (no content). Remove the include of this file. BUG=b:117814641 TEST=Build grunt and gardenia. Change-Id: I0c48167195a9708afc255490bb1996b6dfc7bdfb Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29178 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-23mb/google/octopus: Use a single GPIO for trackpad wake and IRQFurquan Shaikh
This change uses the newly added macros for configuring the same GPI pad(GPIO_135) for IRQ (normal interrupt operations) and wake (interrupt for waking from S3/S0ix) for the trackpad device. The other pad GPIO_142 is now configured as not connected. BUG=b:117553222 TEST=Verified that yorp and bobba wake from S3 and S0ix using trackpad. Change-Id: I2b704f1be493141629c647b79723b0025b0f7dd6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/29189 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-22mb/google/poppy/var/nocturne: Change IMX319 sensor link freqLijian Zhao
Change link frequency of IMX319 from 360Mhz to 482.4 Mhz to match the changes from kernel driver. IMX319 has two PLLs and it can be configured either single or dual. Previous driver implemente dual PLL mode, however image sensor vendor prefer single PLL mode and calculate the pixel rate became easier. So the kernel driver changed to use single pll, coreboot change will match that. Bug=b:116082248 Change-Id: Iac9a72253e0529bf2c0785fb701b7bc251bcbab5 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28736 Reviewed-by: Tomasz Figa <tfiga@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-22mainboard/: Select MISSING_BOARD_RESET appropriatelyNico Huber
We didn't have a hard_reset() implementation for these boards. So select the board_reset() stub for them. Change-Id: I77651e3844632fb1a347008c96e53d23cc5a2646 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29170 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-22soc/rockchip/rk3399: Convert to `board_reset()`Nico Huber
Change-Id: Id07e1c7fbd35393ffafda53fc7a15ec0e157d075 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-10-22reset: Convert individual boards to `board_reset()`Nico Huber
Change-Id: I6182da172ae2f4107a9b5d8190e4b3b10ed2f0b9 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-10-19mb/google/octopus: Preserve MRC training data across firmware updateFurquan Shaikh
This change udpates FMAP to wrap MRC training data in RW_PRESERVE section so that we don't lose the data when performing full firmware updates on octopus. BUG=b:117882029 TEST=Verified that chromeos-firmwareupdate doing full firmware update preserves training data on octopus. Change-Id: I5adb9bfa926327057b003360150685a8b4778c8c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/29183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-19mb/google/fizz: Provide nhlt variant APIDavid Wu
Move current NHLT configuration implementation to baseboard so that variants can leverage it or provide their own configuration. BUG=b:117066935 BRANCH=Fizz TEST=emerge-fizz coreboot Change-Id: I30d93babb6fc09e8642b3740f1f7638fa33f0ade Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28965 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-19mb/google/fizz: Provide cros_gpio variant APIDavid Wu
Add support for ChromeOS GPIO ACPI table information by providing weak implementation from the baseboard. BUG=b:117066935 BRANCH=Fizz TEST=emerge-fizz coreboot Change-Id: I2fa52c005cacdbcc322d107a3ac92d22df3f3697 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-19mb/google/fizz: Add variant API for gpioDavid Wu
Provide API for gpio table functionality. Default weak implementations are provided from the baseboard. BUG=b:117066935 BRANCH=Fizz TEST=emerge-fizz coreboot Change-Id: Iaafa8d6932bc0a37826175b15816f1b9a4f4c314 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-19mb/google/fizz: Provide baseboard and variant conceptsDavid Wu
In order to be able to share code across different fizz variants, provide the concept of baseboard and variants. New directory layout: variants/baseboard - code variants/baseboard/include/baseboard - headers variants/fizz - code variants/fizz/include/variant - headers New boards would then add themselves under their board name within "variants" directory. This is purely an organizational change. BUG=b:117066935 BRANCH=Fizz TEST=emerge-fizz coreboot CQ-DEPEND=CL:1273514 Change-Id: I28cc41681e7af88ddeba2e847dc0a4686606feb2 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-19google/grunt: Remove unused MRC regions from FMAPRaul E Rangel
I didn't change the offsets of all the other regions because I didn't want to cause all dogfood devices to lose their corp enrollment. BUG=b:117797131, b:117798830 BRANCH=none TEST=Ran autotest and made sure the tests were skipped /tmp/test_that_results_2OZ90v/results-1-firmware_CorruptRecoveryCache [ PASSED ] /tmp/test_that_results_2OZ90v/results-1-firmware_CorruptRecoveryCache TEST_NA: No RECOVERY_MRC_CACHE was found on DUT. /tmp/test_that_results_2OZ90v/results-1-firmware_CorruptRecoveryCache/firmware_CorruptRecoveryCache.normal [ PASSED ] /tmp/test_that_results_2OZ90v/results-1-firmware_CorruptRecoveryCache/firmware_CorruptRecoveryCache.normal TEST_NA: No RECOVERY_MRC_CACHE was found on DUT. Change-Id: I5cdbf4139dde80fe6e9d0045139a97841b03bc42 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/29171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-10-18src/mainboard: Remove unneeded whitespaceElyes HAOUAS
Change-Id: Ibf23f49e7864c611a3cb32a91891b6023a692e1d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28979 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-10-18mb/google/glados/variants/sentry: Remove unnneded whitespaceElyes HAOUAS
Change-Id: Ibc928dc66e00dbb40d25420fd92f6c5f8049dec1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28703 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-18src/{sb/intel,mb/google/auron}: Don't use device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: I564319506870f75eab58cce535d4e3535a64a993 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-10-18mb: Fix non-local header treated as localElyes HAOUAS
Change-Id: Ib39305effdb00e032ca07e6d0e0d84cdf3dcf916 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-17google/kukui: Configure USBTristan Shieh
Set up USB host controller. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Iec98f3dc1bbf3dda3d28dbefad15339d48608c7e Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/28788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2018-10-17mb/*/*: Clean up FADT checksum assignmentJonathan Neuschäfer
The assignment of header->checksum was in some cases done twice, or unnecessarily split into two lines. Change-Id: Ib0c0890d7589e6a24b11e9bda10e6969c7d73c56 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-10-17mb/google/poppy/variants/nocturne: Disable pull-down of GPP_E9/E10Roy Mingi Park
While these pins were set to a pull-down 20KOhm, NPCX EC consumes ~2.1mW higher power. Becasue there was leakage current on both GPIO67 and GPIO70 from NPCX EC. With the external pull-up 10KOhm for USB_OC0#/USB2_OC1#, this wasn't enough to prevent leakage current. BUG=b:117139495 TEST=Check nxpc EC power to see power improvement Change-Id: I685d876461c263f07ca4c8f8046635cb7087279c Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com> Reviewed-on: https://review.coreboot.org/29007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-17mb/google/poppy/variants/nocturne: Tune DPTF settings for CPUSumeet R Pawnikar
Update CPU passive temperature threshold value from 70C to 80C, to avoid early throttling for spiky workloads. Also, change CPU throttling interval from 1 sec to 5 sec for CPU temperature. BUG=b:116400298 BRANCH=None TEST=Manual performance testing on nocturne. Change-Id: Ic5031a4aa16f750237565f4e4928e78834b1d686 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/29044 Reviewed-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-15mb/google/poppy/variants/nami: Disable rear camera/DMIC for SyndraAmanda Huang
Since there are two cameras on Nami and only one camera on Syndra. We need to disable rear camera/DMIC on all Syndra sku. BUG=b:112876867 Change-Id: I92fb43ec84387c268ffdb6d0d34a5e5b13bcf50a Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-15vc/google/chromeos/ec: remove EC hibernate in cr50 update pathAaron Durbin
More platforms are not able to hibernate under certain circumstances, such as when AC is plugged. This original path was conservatively put in to prevent potential damage when cr50-update-caused asynchronous resets occur. Julius' compelling argument that async resets from recovery mode requests should have enough coverage of the design over the course of project development. Remove the hibernate path and assume all is well going forward. Change-Id: I37121e75ff4e6abcb41d8534a1eccf0788ce2ea2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/29076 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-12amd/stoneyridge: Rename GppClkCntrl fieldsMarshall Dawson
Make the field names of the MISCx00 GPPClkCntrl more manageable by shortening their names. Make the definitions look more like the rest of the header file. Change-Id: I515cd664808e38851a7dbdba899df4fb9bbbcde6 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/29014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-18 13:27:29 +0000