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2019-04-20mb/google/arcada: Set psys_pmax to 140WNathan_chen
arcada is designed to operate at max power of 140 Watt. Hence set psys_max to 140W. BUG=b:124792558 TEST=Build and boot arcada. Change-Id: I280dfb81b3e25c7619a68db487e2b18867f52fda Signed-off-by: nathan chen <nathan_chen@wistron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32335 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-04-19src/mb/Kconfig: Fix PCI subsystem IDsElyes HAOUAS
References to MAINBOARD_PCI_SUBSYSTEM_{DEVICE_ID,VENDOR_ID} were removed in commits dbd3132 sb/intel/{i82801g/i/j,bd82x6x}: Make use of generic set_subsystem() 00bb441 sb/intel/lynxpoint: Remove PCI bridge function Change-Id: I72bba8406eea4a264e36cc9bcf467cf5cfbed379 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32107 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-19kohaku: mb/hatch/gpio: Scrub Kohaku GPIOs.Tim Wawrzynczak
Ensure Kohaku GPIO pins are configured correctly w/r/t Hatch. Implement the base/override model for GPIOs (regular and early). The 'hatch' baseboard contains the base GPIOs, and variants can override individual pads. BUG=b:129707481 BRANCH=none TEST=Compiles for all variants. Change-Id: Ie5c83a0538d367ea11e9499f21cea41891d7a78e Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-19mb/google/sarien: Update SMBIOS type17Lijian Zhao
Match SMBIOS type 17 device locator with motherboard silk screen,using "DIMM-A" and "DIMM-B" instead of "Channel-0-DIMM-0" and "Chaneel-1-DIMM-0". TEST=Boot up with sarien platform and run dmidecode to check SMBIOS type 17 have expected output. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: Ie2125c0381bd24d96f725f68cde93a53da8c94c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-04-19mb/google/sarien: Update GPIO GPP_C23 settingLijian Zhao
GPIO pin GPP_C23 is used as level trigger but not edge trigger, also it is not inverted, correct it here. According to board schematic, GPP_C23 connected with 3.3v pull up, so the pin is low active. BUG=b:128554235 TEST=Boot up arcada platform with stylus keep on touching the screen, the touch screen is still functional once in OS stage. Without change, touch screen is not functional at same scenario. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I2bee664198057e3997dda181a16b9a0388067036 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32347 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-18mb/google/sarien: Enable board_id featureDuncan Laurie
Enable the Kconfig option to automatically read the board ID and populate it into the SMBIOS tables. BUG=b:123261132 TEST=verify current board id from the OS: cat /sys/class/dmi/id/board_version rev1 Change-Id: Id41631bfaa627ca9d5034e2ebe93f8ace2ffdad8 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32277 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-18mb/google/octopus: Set default configuration to low for gpio_178Wisley Chen
Set default configuration to low for gpio_178, and can remove the override setting for bobba/bloog/fleex/meep/phaser. For ampton, Change-Id I64a67f73564188ad0548a1a770169ef2bca47453 ( mb/google/ampton: Fix polarity of EN_PP3300_WLAN_L signal.) modified the pin setting. TEST=verified that boot into OS on meep board. suspend/resume, reboot, and no failure found. Change-Id: I7668ff4817edfca5c6cea63db779fcea21c7af92 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32247 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-17google/kukui: Get write protection status from WP GPIOHung-Te Lin
Write protection (get_write_protect_state) was hard-coded to 0 and should be fixed to read from correct GPIO (PERIPHERAL_EN0 from schematics). BUG=b:130681408 TEST=make -j; boots on Kukui Rev2. BRANCH=None Change-Id: I75b98b1d587abe5e8cdf3df28ea661bc1ffa19f9 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: You-Cheng Syu <youcheng@google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Joel Kitching <kitching@google.com>
2019-04-16soc/intel/cannonlake: Configure Vmx support using KconfigRonak Kanabar
Change VmxEnable UPD values based on Kconfig ENABLE_VMX and remove it from Devicetree and chip.h Remove Vmx dependency on Vt-d Change-Id: I4180c2270038a28befd6ed53c9485905025a15ba Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32117 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-15google/kukui: Include LCD module identifier (LCM ID) into SKU IDHung-Te Lin
Kukui is using MIPI display panel and needs some identifier to tell payloads which LCD module is installed, and to select right kernel device tree. Following Scarlet, the decision is to embed LCD module ID as part of SKU ID. The LCM ID is using a different voltage mapping table from the rest. Considering the complexity in computation of SKU ID, it is better to move the cache logic from get_index to caller. Also revise the mapping table since ADC on 8183 only supports 12 levels. BUG=b:129299873 TEST=make -j; boots on Kukui Rev2 unit. Change-Id: Ib0c00bc8ce3c71c445c5c4561403ce8ef4dd5844 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32263 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-15mb/google/hatch: Update sleep signal assertion widthsRizwan Qureshi
Based on the power rail discharge times measured on hatch, update the assertions widths that have to be programmed in SoC. BUG=b:129328209 TEST=warm/cold reboot and S3 are working fine on hatch. Change-Id: I3c6dce0a942e6dcd9e55ef5e58a7e9e8d2b0a1e3 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32266 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-15mb/google/octopus: Add custom SAR values for Laserpeichao.wang
Laser would prefer to use different SAR values. Since Laser sku id is 5. BUG=b:130381493 BRANCH=octopus TEST=build Change-Id: I5cce38a191edfb235e274db3c788c58b65e0ebe1 Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32296 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-13mb/google/hatch: Restore Goodix Touch ScreenEric Lai
Restore Goodix devicetree config because of the missing Goodix config when moving from baseboard devicetree to board level overridetree. And move PENH from I2C#2 to I2C#1. BUG=b:124460799 BRANCH=None TEST=local build and tested with Goodix touch screen Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ic028c5d7b687a069d7f0510897bea91dca58e91f Reviewed-on: https://review.coreboot.org/c/coreboot/+/32265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-12mb/google/hatch: Use GPIO IRQ for sx9310 deviceFurquan Shaikh
This change uses GPIO IRQ instead of IOAPIC for GPP_A0 pad which is the interrupt line for sx9310. This is required because IRQ# used by GPP_A0 is allocated for PIRQ which does not allow IRQ# sharing. Additionally, this change also configures GPP_A6 for GPIO IRQ. GPP_A6 is currently unused in the devicetree. BUG=b:129794308 TEST=Verified that there are no interrupt storms on GPP_A0. Change-Id: Ibb510a647391c0d9cb854d23656bb4b1cb7756ab Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-04-12mb/google/hatch: Configure reset config to PLTRST for IOAPIC padsFurquan Shaikh
This change configures reset config for all pads routed to IOAPIC as PLTRST. This is required to ensure that the internal logic of the GPIO gets reset any time the platform enters S3 or powers off and avoids any interrupt storms on boot-up. BUG=b:129933011 TEST=Verified that there are no interrupt storms on boot-up from S5. Change-Id: Ib790280c9f1410fa18746d4d7d2a5027afd7585b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-04-12mb/google/hatch: Skip UART0 config in FSPFurquan Shaikh
UART0 is already configured in coreboot, so this change sets SerialIo config for UART0 to PchSerialIoSkipInit to skip initialization in FSP. BUG=b:130325418 Change-Id: Ifc88f4fa11bff2144417d5194776c15f9f7b60ac Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Shelley Chen <shchen@google.com>
2019-04-11google/kukui: Add variant 'Krane'Hung-Te Lin
Add the new configuration 'Krane' that will need at least its own EC. There's currently no difference in coreboot side. BUG=b:130011505 TEST=make menuconfig; make -j # select board=Krane BRANCH=None Change-Id: Ibb2ec42b08f9a51b22c22f3fe99b203f5eb31627 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: You-Cheng Syu <youcheng@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-11mb/google/sarien: Reserve gpio pins for D3 cold controlEric Lai
Based on HW change, reserve gpio pins for D3 cold control. A13,A15 for Card reader H13 for M.2 SSD BUG=b:123263562 TEST=N/A Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ib4245be8d77c015e56df7b1d53ef82722c51d656 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-04-11mb/google/sarien: Change GPIOs to avoid leakage during S0iXRoy Mingi Park
Three GPIOs are not being used and this change will save 2-3mW power during S0iX and this power saving is only for Arcada BUG=b:129990365 TEST= Measure total platform power during S0iX from Arcada Change-Id: Ie0208bd6c7affb2e87fd76005b727ea7effdf434 Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-04-11mb/google/ampton: Fix polarity of EN_PP3300_WLAN_L signal.Tim Wawrzynczak
WiFi enable signal was configured and driven as active-high, but the signal is |To start the server in this Emacs process, stop the existing actually active-low BUG=b:130196983 BRANCH=none TEST=Verified WiFi still works after boot, and also after a suspend/resume cycle. Device powers down correctly using "poweroff". Change-Id: I64a67f73564188ad0548a1a770169ef2bca47453 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32255 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-11chromeos: clean up "recovery" and "write protect" GPIOsJoel Kitching
The "write protect" GPIO's cached value is never actually read after entering depthcharge. Ensure the value from get_write_protect_state() is being transferred accurately, so that we may read this GPIO value in depthcharge without resampling. The cached value of the "recovery" GPIO is read only on certain boards which have a physical recovery switch. Correct some of the values sent to boards which presumably never read the previously incorrect value. Most of these inaccuracies are from non-inverted values on ACTIVE_LOW GPIOs. BUG=b:124141368, b:124192753, chromium:950273 TEST=make clean && make test-abuild BRANCH=none Change-Id: Ic17a98768703d7098480a9233b752fe5b201bd51 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-11google/kukui: Use internal CR50_IRQ pull-upYou-Cheng Syu
For Kukui CR50_IRQ pin, we're going to replace external pull-up with internal pull-up. This change won't break older boards, so we can just always do that when setting up GPIOs. BUG=b:124821269 BRANCH=none TEST=Waveform looks correct. Change-Id: Ib1a90dce583a6aa0cec8ac8ba96d1362f50c16a8 Signed-off-by: You-Cheng Syu <youcheng@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-04-11mb/google/octopus: Disable WLAN prior the entry of S5Kane Chen
ODM reported issues that some systems can't be shutdown to S5 very occasionally. ODM found issue is gone if they remove the WLAN card. So, this change to disable WLAN before system enters S5. This change is validated by ODM and it does help issue. BUG=b:129377927 Change-Id: Ib8e81022b8c9b63bc75e5cc14121233222da7595 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32246 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Chen Wisley <wisley.chen@quantatw.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-09google/kukui: Configure AP_IN_SLEEP_L correctlyYou-Cheng Syu
This pin should be set to its alternative function SRCLKENA0 instead of GPIO, so that SPM (a power management component of MT8183) can control it. BUG=b:113367227 BRANCH=none TEST=1. Boot. Run 'powerinfo' in EC console and see power state in S0. 2. Run 'powerd_dbus_suspend --wakeup_timeout=10', and then run 'powerinfo' in EC console and see power state in S3. 3. Wait until AP resume. 4. Run 'powerinfo' in EC console and see power state back to S0. Change-Id: I0a7e34f95381dec17eb6d166d6552c12e021bd9a Signed-off-by: You-Cheng Syu <youcheng@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32120 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-09mb/google/hatch: Support 16MiB fmapPhilip Chen
Add a fmd file for 16MiB fmap, so that we can support both 16MiB / 32MiB SPI flash ROM chips. BUG=b:129464811 TEST=build hatch firmware image with 16MiB fmap and verify fmap is updated by 'fuility dump_fmap' Change-Id: Ifc0103c7fd0d99439f40a31d23422401a6dce826 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-09mb/google/hatch: Add ACPI support for BT reset functionalityTim Wawrzynczak
Expose the Bluetooth BT_DISABLE_L signal in Hatch's devicetree, on both USB2 port 5 and 10. BUG=b:123293169 BRANCH=none TEST=compiles, verified kernel is able to find the reset-gpio Change-Id: I6e4d9786e44f12da71533b6740fdd390f3a57e40 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32216 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-08mb/mainboard/google/sarien/variants: Set correct tcc_offset valueSumeet Pawnikar
Set new tcc_offset value to 10 degree C. This configures the Thermal Control Circuit (TCC) activation value to 90 degree C. It prevents any abrupt thermal shutdown while running heavy workload. This helps to take early thermal throttling action when CPU temperature goes above 90 degree C. Change-Id: Ica77264782b4a3f3e72e73e1b8cb8b2e464fb033 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-08mb/google/sarien: Add support for melfas touch panelEric Lai
Add a support melfas touch panel with i2c address:0x34. BUG=b:122019253 TEST=tested with new melfas touch panel and worked Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I27f5c47517d093c819cbbbcdafd85d74145887e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32169 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-06src: Use include <delay.h> when appropriateElyes HAOUAS
Change-Id: I23bc0191ca8fcd88364e5c08be7c90195019e399 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: David Guckian
2019-04-06{mb,soc/intel/skylake}: remove unused InternalGfxMaxim Polyakov
The InternalGfx option in devicetree.cb is not used to enable iGPU. The patch removes this option from chip.h and mb/*/devicetree.cb files for all boards with skl/kbl processor. Change-Id: I41ecca3fdfb1d4b20ee634a13263ff481dcf440e Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-04-04mb/google/hatch: Move I2C/SPI options to override treeFurquan Shaikh
This change moves the I2C/SPI devices and configs which do not apply to all variants to override tree. Currently, there are just two variants. However, as we prepare to add more variants, these devices need to be moved out of the base devicetree. BUG=b:129728235 TEST=Verified that I2C/SPI devices are present in static.c for hatch and hatch_whl. Change-Id: I9426f6bf5f8514de5f1889e22e57105749fd92de Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32138 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-04mb/google/hatch: Change the DEVSLP reset config to PLTRSTRizwan Qureshi
In S3 the PCH is driving the DEVSLP signal low, assuming that the SATA device is already powered off. However on hatch the SATA power is still enabled. And, since DEVSLP is low, this causes the SATA device to not enter low power state. The fix here is to set the pad config to be reset on PLTRST assertion which will cause the pin to be high impedance state and will be pulled up by the SATA device. BUG=b:126611255 BRANCH=None TEST=Make sure that S3 and S0ix is working fine on hatch. And also make sure that DEVSLP is pulled high in S3. Change-Id: Ifb6a71a72244522c8dd8d48e9b9f8dc6feef8981 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-04mb/google/fizz/variants/karma: Clear GPP_B4 when entering S5David Wu
Set GPP_B4 to low in S5 to meet touch panel power sequence BUG=b:124197348 BRANCH=master TEST=Verify GPP_B4 is low. Change-Id: I65deb33a45fdc0c0ce64deaa29c2790029dc1d12 Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-04mb/google/hatch: Add Kohaku boardShelley Chen
Adding Kohaku as a variant of hatch. BUG=b:129706980 BRANCH=NONE TEST=./util/abuild/abuild -p none -t google/hatch -x -a make sure HATCH_KOHAKU is built as well. Change-Id: I5b451f421f6d353005e6b73eac180dcec2e8b0c0 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-04mb/google/hatch: Create kohaku variantShelley Chen
Creating Kohaku hatch variant. Currently taking a copy of the hatch variant. Kohaku-specific changes to come in future CLs. BUG=b:129706980 BRANCH=NONE TEST=NONE Change-Id: Ib4b8c2c8332910d992549e3aae8e6aff5234698b Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32160 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-04vboot: remove Kconfig option VBOOT_PHYSICAL_REC_SWITCHJoel Kitching
This option is duplicated in depthcharge: https://crrev.com/c/1545144 BUG=b:124141368, b:124192753, chromium:943150 TEST=make clean && make test-abuild CQ-DEPEND=CL:1545144 BRANCH=none Change-Id: I48e20ad21cdcb948a23387d3e5fcf142723b0c82 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-04-03mb/google/hatch: Enable Goodix Touch ScreenEric Lai
Enable Goodix touch screen. Follow GT7375P_Datasheet_Rev.0.1 BUG=b:124460799 BRANCH=None TEST=local build and tested with Goodix touch screen Change-Id: Ib204e6b77b87ba6c775cf38e572476dd9eb37d1d Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32134 Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-03mb/google/sarien/variants/sarien: Update thermal configuration for DPTFJohn Su
Follow thermal table for second tunning. BUG=b:129509918 TEST=Built and tested on sarien system Change-Id: I64844b84891dc3ab7abe9378cdca5dcf57b3e433 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2019-04-02mb/google/poppy/variants/nami: update sku_ids for PantheonFrank Wu
The sku ids are updated for Pantheon. Sync'ing the sku_ids list in the master sku sheet for Pantheon. BUG=b:121207221 BRANCH=firmware-nami-10775.B TEST=emerge-nami coreboot chromeos-bootimage Change-Id: Ibf683ca8219b2980ea9d9c40b06db264d58440b0 Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
2019-04-02mb/google/hatch: Change GPIO_E1 settingJohn Su
For HW require to change GPIO_E1. Change GOIO_E1 setting from NF2(SATAGP1) to NF1(SATAPCIE1). BUG=b:123730924 TEST=flash BIOS and make sure hatch boots up properly Change-Id: I0f5569e13b17a2dc713be5031a63436e8f31f911 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32099 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-02mb/google/hatch: Re-configure GPP_A12 as GPO before entering sleepKrishna Prasad Bhat
GPP_A12 has a Native3 (SX_EXIT_HOLDOFF#) mode, which allows to delay resuming to S0. If this pad is not locked and platform was not initially designed for this functionality, malware could reconfigure this pads setting under OS (switch to Native3), which would make platform not able to resume until G3 is applied. To prevent misuse of this pad, re-configure this pad before entering S3 and S5 to guarantee that the pad configuration is correct. BUG=b:128686027 Change-Id: I1e7979baa491acf2c56d223afb4618f0f6429e37 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-01assert: Make dead_code() work at link-time instead of compile-timeJulius Werner
The dead_code() macro can be used to ensure that a certain code path is compile-time eliminated (e.g. if you want to make sure it's never executed for certain Kconfig combinations). Unfortunately, the current implementation via __attribute__((error)) hits only at the GCC level. This can catch code that can be compile-time eliminated based on state within the same file, but it cannot be used in cases where a certain library function is built but then garbage collected at link time. This patch improves the macro by relying solely on the linker finding an undefined reference. Unfortunately this makes the error message a little less expressive (can no longer pass a custom string), but it is still readable and one can add code comments next to the assertion to elaborate further if necessary Change-Id: I63399dc484e2150d8c027bc0256d9285e471f7cc Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32113 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-01mb/google/sarien: Enable Bluetooth RF killLijian Zhao
Add bluetooth Rfkill function to recover the Bluetooth controller in cases where itself has entered a bad state and needs to be recovered. Bug=b:129375810 TEST=Boot up into OS and dump SSDT table, check there's _DSD entry under Bluetooth devices with GPIO in. Also confirm bluetooth itself is functional. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I79a310a55d94d7d20d1705afc11fe47cbb81abc1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-04-01mb/google/hatch: Unlock GPIO padsKrishna Prasad Bhat
GPP_A12 is being used as FPMCU_RST in hatch. This GPIO is being padlocked in FSP and cannot used in kernel. Hence unlock the GPIO pads to export this pin in kernel to be used as FPMCU_RST. BUG=b:128686027 BRANCH=None TEST=Read Pad Configuration Lock (PADCFGLOCK_GPP_A_0) register. localhost /sys/class/gpio # iotools mmio_read32 0xfd6e0080 0x00000000 localhost /sys/class/gpio # echo 212 > export Change-Id: Ie0439956e6c8e386435e535665ccaf2ab82adeb0 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32126 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-29src: Use include <reset.h> when appropriateElyes HAOUAS
Change-Id: I3b852cae4ef84d257bf1e5486447583bdd16b441 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-29mb/google/arcada: Make bluetooth reset_gpio active lowMike Hsieh
Follow b:129375810 to set bluetooth reset_gpio as ACPI_GPIO_OUTPUT_ACTIVE_LOW BUG=b:129375810 TEST=Verified BT function on Arcada DVT1 system. Signed-off-by: Mike Hsieh <mike_hsieh@wistron.corp-partner.google.com> Change-Id: I816eb2a76f642a2bb1702f38138bce7916334011 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-03-29mb/google/arcada: Make touchscreen IRQ level triggeredMike Hsieh
Touchscreen lost function after boot with stylus touching the screen BUG=b:128554235 Signed-off-by: Mike Hsieh <mike_hsieh@wistron.corp-partner.google.com> Change-Id: I692fc6f245b7fade67862da4986a83d11a2cd51f Reviewed-on: https://review.coreboot.org/c/coreboot/+/32100 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-29mb/google/hatch: Deassert EN_PP3300_WWAN during sleepMaulik V Vaghela
Deassert EN_PP3300_WWAN to turn the WWAN module completely off when entering S5. This is the same fix in commit eeb475c5c for coral board. BUG=none BRANCH=none TEST=On hatch, Perform a quick system power cycle, verify that the modem is powered cycle and the SIM with PIN lock enabled requests unlocking. Change-Id: I3ec8ccb7618189b9e8586f5571a68d3309597ee7 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-28mb/google/sarien: Call EC romstage init functionDuncan Laurie
When in romstage call into the EC init function so it can send a progress code to the EC before memory training starts. BUG=b:127875364 TEST=boot with FSP debug and ensure EC does not try to turn off the system while it is still booting. Change-Id: I5d99fb16bae250a82b652c530c13977e74c3378b Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-03-28Mistral: Enable USB in romstageNitheesh Sekar
Enable USB support for mistral in romstage. TEST=build & run Change-Id: I5c2bbe16aa3601e014a2b77d192565402ed23794 Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-18 22:38:38 +0000