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2020-09-16zork/var/ezkinil: Fix Touchscreen doesn't work on v3.6x rework boardLucas Chen
The gpio90 EN_PWR_TOUCHSCREEN had been set to PAD_GPO(GPIO_90, LOW), but addtional PAD_NC(GPIO_90) cause enable fail. remove it for issue fixed. BRANCH=zork BUG=b:168580357 TEST=Check Touchscreen function work Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Change-Id: Id94dd63ba51759cebaf17779a5e659dbe0f1807f Reviewed-on: https://review.coreboot.org/c/coreboot/+/45415 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-16trogdor: invoke new watchdog function before qclib runsRavi Kumar Bokka
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Change-Id: Ia76323c749a9ba71cc752a91c968aeacc11e0093 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45212 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-15mb/google/dedede/var/magolor: Add touch screen devicesRen Kuo
add the magolor touch screen ctrl devices: 1)elan 6915 2)elan 5012 3)raydium RM32680 BUG=b:166711761 BRANCH=None TEST=build firmware and verify the touch functions on DUT Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Change-Id: Icd2963317e858f7d35c937e45cd6f3e556bbb953 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45227 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Henry Sun <henrysun@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-15mb/google/zork: Fix FPMCU_INT_L configurationFurquan Shaikh
Fingerprint interrupt (FPMCU_INT_L) is level triggered and not edge triggered. Also, we are using GEVENT for wake from fingerprint and not the GPIO IRQ wake. Thus, the irq property exposed in ACPI tables does not need to be set to indicate wake for the IRQ. This change updates GPIO table to configure the pad as level triggered and drops the wake attribute for irq_gpio in overridetree. BUG=b:165612778 BRANCH=zork TEST=Verified that fingerprint still works in S0 and to wake device from S3. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I9007e5b0882ac1a6770db52d651218998f6d750d Reviewed-on: https://review.coreboot.org/c/coreboot/+/45307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-09-14soc/amd/picasso: Move sd_emmc_config into emmc_config structRaul E Rangel
I plan on adding another eMMC parameter. This refactor keeps the config contained in a single struct. BUG=b:159823235 TEST=Build test Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4b57d651ab44d6c1cad661d620bffd4207dfebd4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-09-14mb/google/delbin: Configure DP_HPD as PAD_NC and disable DdiPortHpdRavi Sarawadi
GPP_A19(DP_HPD1) and GPP_A20(DP_HPD2) were configured native function (NF1) without internal pull-down which wrongly presents HPD interrupts. DP_HPD had been removed for EVT design as those events are through eSPI. This change configures GPP_A19 and GPP_A20 to be no connection and disables DdiPort1Hpd and DdiPort2Hpd. BUG=b:162566436 TEST=Booted to kernel and verified no kernel HPD pins assertion message on Delbin board. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: Ifdef8ee438276678258b75d2fb70c6dfc7ee0a33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-09-14mb/google/octopus/variants/fleex: Add G2Touch touchscreen supportJohn Su
BUG=b:167297664 BRANCH=octopus TEST=build fleex, and check touchscreen can work Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I910681c258ff5487830e795a8bd08c66be69b1d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44980 Reviewed-by: Justin TerAvest <teravest@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Henry Sun <henrysun@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14mb/google/dedede/var/boten: Add audio configurationKarthikeyan Ramasubramanian
Add configuration for ALC5682 headphone jack and ALC1015 speaker amplifier. Also turn on the HDA PCI device. BUG=b:161667665 TEST=Build the boten board and verified the audio functionality. Change-Id: I835db854543e6282c102c86a7073b432fd89d0a5 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44920 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14mb/google/volteer: Fix GPP_E12 definitionCaveh Jalali
GPP_E12 should not be defined in the baseboard as its use is determined by the variant. For legacy reasons, we still have GPP_E12 defined in early_gpio but should not. Malefor and volteer* have the same GPP_E12 definition, but that is a misconfiguration. I think that was a copy-paste that slipped through the reviews. BUG=b:157597158 TEST=volteer2 boots to the OS Change-Id: Ic3ef864827aa94b0b96e335565119f3d5d008837 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-09-14mb/google/volteer/var/voxel: Update DPTF parameters and TCC offsetDavid Wu
1. Set tcc offset to 5 degree celsius 2. Apply the DPTF parameters received from the thermal team. BUG=b:167523658 TEST=build and verify by thermal team Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I01a6fc5bd959798c8dd423df3907c69c883733e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-14mb/google/volteer: Refactor baseboard devicetreeTim Wawrzynczak
Clean up the DPTF section of the baseboard devicetree; this makes overrides simpler, as not necessarily all of the fields need to be overridden. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Iad46fd02f7602c9419d7c3674b0d2b6f5add9a93 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-14mb/google/dedede/variants/drawcia: Increase PL2 value from 15W to 20WSumeet R Pawnikar
Jasper Lake SoC supports PL2 (Power Limit2) as 20W. Increase PL2 value from 15W to 20W. BRANCH=None BUG=b:166656373 TEST=Built and tested on drawlat system Change-Id: I82d6792907bb1c88cc9dd57d1eaeda8421c12fb2 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45162 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14mb/google/volteer: Add error handlingJohn Zhao
Coverity detects missing error handling after calling function tlcl_lib_init. This change checks the function tlcl_lib_init return value and handles error properly. Found-by: Coverity CID 1432491 TEST=None Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ife38b1450451cb25e5479760d640375db153e499 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-14mb/google/volteer: Enable EC software syncDavid Wu
Enable EC software sync for terrador and todor BUG=None TEST=emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I8c463eadd19d99dc04923f7400560cf7ba4b8101 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-09-13soc/amd/picasso/chip: fix typo in acp_pme_enableFelix Held
That devicetree setting is about the Audio Co-Processor and not ACPI. BRANCH=zork Change-Id: I7f376371ee094392d4434340c77f0fc8d0d8e4e1 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-09-11strongbad / coachz : Add Initial SupportBob Moragues
BUG=b:162409909 BUG=b:164196066 BRANCH=NONE TEST=Verify build of strongbad target Signed-off-by: Bob Moragues <moragues@chromium.org> Change-Id: If83bd2c8f25fdd3c9625f40121e55c3c922a66fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/45276 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-11mb/google/dedede/var/drawcia: Remove debug statement with NULL pointerKarthikeyan Ramasubramanian
The debug statement to print WiFi SAR file can potentially have a NULL pointer. Also the debug statement does not add much value. Hence remove the debug statement. BUG=b:165613510 TEST=Build and boot the drawcia board to OS. Change-Id: I710240f5e965f523fb8ac55a67880e1cbf9abd48 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-11mb/google/dedede/var/drawcia: Add Wifi SAR for drawciaWisley Chen
drawman/drawlat/drawcia share the same coreboot, and only drawcia is convertible. Use tablet mode of fw config to decide to load custom wifi sar or not. BUG=b:165613510 TEST=enable CHROMEOS_WIFI_SAR in config of coreboot, emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage. Change-Id: Ibcd498021e63d0a172c71c3d94b60b3a25973467 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-09-11mb/google/dedede: Enable FW_CONFIGWisley Chen
Enable FW_CONFIG and add tablet mode field in devicetree BUG=b:165613510 TEST=emerge-dedede coreboot Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Change-Id: I55e4c0d0b4aa2337c01773006d0b485fdcd91654 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-09-11mb/google/dedede: Add option to enable WiFi SAR configsWisley Chen
BUG=b:165613510 TEST=emerge-dedede coreboot Change-Id: Ic575889fd9b726a710abff78e1ecc8427b668d5d Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-09-11mb/google/zork: Add woomax memory ID 0Rob Barnes
Woomax needs memory ID 0 to map to MT40A512M16TB-062E:J. BUG=b:165611555 TEST=None Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: Ibbcef6be382bd6649c93cfe92427f124dd137112 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45264 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-11mb/google/volteer/variants/volteer2: route GPP_F14 via APICAlex Levin
GPP_F14 should be configured to be routed via APIC and not SCI. BUG=b:162528549 TEST=verified on a volteer2 Signed-off-by: Alex Levin <levinale@google.com> Change-Id: I7f2c7af230dd75b3cb3806e2b186725d49da9e68 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45279 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-10trogdor: Strappings_update_final3.1_second_thisistherealone.patchJulius Werner
Apparently what I thought was lazor-rev2 is actually lazor-rev3 and nobody is really sure what lazor-rev4 is going to be at this point or how we proceed from there. What seems to be somewhat agreed upon is that for now all Lazor revisions use the "old" GPIO mapping and it's not very clear if that's ever going to change for Lazor, so let's take the revision restriction out from Lazor for now. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I4939ccfd8464da6e72b5e01a58489b8c80f5b4df Reviewed-on: https://review.coreboot.org/c/coreboot/+/45225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Philip Chen <philipchen@google.com>
2020-09-10soc/amd/picasso: Move APCB generation out of picassoRob Barnes
Move APCB generation out of the picasso makefile and into the mainboard makefile. APCB generation tends to be mainboard specific and does not belong in the soc makefile. BUG=b:168099242 TEST=Build mandolin and check for APCB in coreboot binary Build and boot ezkinil Change-Id: Ib85ad94e515f2ffad58aafe06c1f1d4043e9303c Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45222 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-10mb/google/asurada: Add config for hayatoYu-Ping Wu
BUG=b:163789704 TEST=emerge-asurada coreboot BRANCH=none Change-Id: I1a5928fb81356aaf040534e1675933a504aa9f95 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45163 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-10sc7180: Add display hardware pipe line initializationVinod Polimera
Add sc7180 display hardware pipeline programming support and invoke the display initialization from soc_init. Changes in V1: - added display init required check. - added edid read function using i2c communication. - added sn65dsi86 bridge driver to init bridge. - moved display initialization to mainboard file. Changes in V2: - moved diplay init sequence to mainboard file - moved edid read function to bridge driver. - calculated timing paramters using edid parameters. - removed command mode config code. - moved bridge driver to drivers/ti. - seperated out bridge and soc code with mainboard file as interface. Changes in V3: - add GPIO selection at runtime based on boardid. - add vbif register struct overlay. Changes in V4: - update gpio config for lazor board. Change-Id: I7d5e3f1781c48759553243abeb3d694f76cd008e Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-10sc7180: Add support for sn65dsi86 bridgeVinod Polimera
Add sn65dsi86 bridge driver to enable the eDP bridge. Datasheet used : https://www.ti.com/lit/ds/sllseh2b/sllseh2b.pdf Changes in V1: - fix the dp lanes using mask - separate out the refclk and hpd config to init function Change-Id: I36a68f3241f0ba316c261a73c2f6d30fe6c3ccdc Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-09sc7180: GPIO: Add I2S configuration for google/trogdorvsujithk
Configure GPIO pins as I2S mode for audio speaker. The audio speaker does not work on Trogdor revision 1, as the layout was changed. Developer/Reviewer reference, be aware of this issue: https://partnerissuetracker.corp.google.com/issues/146533652 Change-Id: Ia4bbfea591a3231640b53e64f0e4e9d43c4437a3 Signed-off-by: vsujithk <vsujithk@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-09mb/google/volteer/var/trondo: Add memory parts and generate DRAM IDsDavid Wu
Add memory parts and generate DRAM IDs for trondo. BUG=None TEST=FW_NAME=trondo emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I2e89ecaf73a30595ed48ac9ce94ccbd4bb7ed3c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45164 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-09mb/google/volteer/variants/eldrid: add memory.c for ddr4 supportnick_xr_chen
Add new memory.c to support DDR4 memory types. Use the new meminit_ddr() and variant_memory_sku() for eldrid variant code on memory.c The initial settings override the baseboard from volteer and fine tune gpio.c and overridetree.cb on eldrid's configuration. BUG=b:161772961 TEST='emerge-volteer coreboot chromeos-bootimage' and verify that Eldrid can boots. NOTE that tests the ddr4 side of the implementation. Change-Id: I2c7b30093a8d85bac5aba5b83768af5eb36c4f70 Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-09-09util/spd_tools: Support comments in mem_parts_usedRob Barnes
Allow comments prefixed with '#' in mem_parts_used csv file. BUG=None TEST=Run gen_part_id with mem_parts_used file containing comments Change-Id: Ia9e274d45aa06dea7a3a5f8cd1c8ee2b23398876 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-09apollolake: Define MAX_CPUS at SoC scopeAngel Pons
The three Intel Apollo Lake boards (apl_rvp, leafhill and minnow3) do not define MAX_CPUS, which would then default to 1. Since this is most likely an oversight, use the same value as other Apollo Lake boards. To ensure this does not happen again, factor out MAX_CPUS to SoC scope. Change-Id: I5ed98a6b592c8010b59eca7ff773ae1ccc4cd7b1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45144 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-09apollolake: Limit MAX_CPUS to 4Angel Pons
APL does not support Hyper-Threading, and has at most four CPU cores. Change-Id: Ib2ffadc0c31cdd96bec8eed5364c984acb2e1250 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45143 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-09geminilake: Factor out MAX_CPUS valueAngel Pons
Both Gemini Lake boards in the tree use the same value. Change-Id: Ib6bd05206026736fd7e3d44b49e4d8ba217c2708 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-09soc/intel/apollolake: Rename `SOC_INTEL_GLK` symbolAngel Pons
For consistency with other platforms, use `SOC_INTEL_GEMINILAKE`. Change-Id: I06310e5a9bca6c9504f19a6c2fe9b26626f290d4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-09mb/google/puff: Increase DPTF parameters for faffyDavid Wu
Update critical and passive policy for TSR0. BUG=b:167477885 BRANCH=puff TEST=build and verify by thermal team Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I244e1b5cacabf5b73c47b4039ae150cd17fcd0fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/45169 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-08src/mb/google/hatch: remove "sushi" variant.Paul Fagerburg
Sushi is not a real product, just a test of the new_variant program. The effort to keep it up-to-date with the rest of Hatch is no longer worth it. Remove the variant. BUG=b:168030592 TEST=build bot is successful, hatch-cq builds successfully Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Change-Id: I2b0036f3cbdea4bfaed1274ab87a20d24c75de57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-08mb/google/dedede: Fix the SPD pathKarthikeyan Ramasubramanian
CB:44774 introduced the non-existent SPD path. This is preventing the device from booting up. BUG=b:168053219 TEST=Build and boot drawcia board to OS. Change-Id: I70ca5f4cf2c8e2e88ea5b1514b656caafb732743 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-08mb/google/dedede/var/drawcia: Configure I2C high and low timeKarthikeyan Ramasubramanian
Configure the I2C bus high and low time for all enabled I2C buses. BUG=b:162232776 TEST=Measured the I2C bus frequency as 389 KHz, high time as 870 ns and low time as 1580 ns. Change-Id: I67d2725a7fc8d83e3fa8a56cfa86540c4e6f0971 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45084 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-08mb/google/dedede/var/waddledee: Configure I2C high and low timeKarthikeyan Ramasubramanian
Configure the I2C bus high and low time for all enabled I2C buses. BUG=b:163743035 TEST=Measured the I2C bus frequency as 384 KHz, high time as 924 ns and low time as 1680 ns. Change-Id: I60a5f6814fb9818c724f6b6fe465ea49d0de0f97 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45083 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-08nb/intel/sandybridge: Use an enum for `gpu_panel_port_select`Angel Pons
All boards currently have backlight on either LVDS or eDP. Change-Id: I878bc7f1ff75a2b82b9556e855aff1d4d03e0268 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-08nb/intel/haswell: Drop `gpu_panel_port_select`Angel Pons
The corresponding bits in PP_ON_DELAYS are reserved MBZ. Change-Id: Icd2554c928a5908dfb354b81d3e6c5b5f242f1d1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-08soc/intel/broadwell: Drop `gpu_panel_port_select`Angel Pons
The corresponding bits in PP_ON_DELAYS are reserved MBZ. Change-Id: I9789a7d50c4bce2ccad0bf476f877db25e3ff82e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-08mb/google/volteer: config QS silicon devices for CSE LITEMark Hsieh
Configure eldrid to use CSE Lite. BUG=b:158140797 TEST=cd to volteer's asset_generation folder, execute "./gen_all_variant_images.sh" and verify that all variant images are produced. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I357abdac4102f358d3aa1cb50f600312039ef140 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-09-08mainboard/google/volteer: Disable S0i3.4 if cr50 firmware is too oldJes Klinke
For Volteer (and future Tiger Lake boards) we can enable mode S0i3.4 only if we know that the Cr50 is generating 100us interrupt pulses. We have to do so, because the SoC is not guaranteed to detect pulses shorter than 100us in S0i3.4 substate. A new Kconfig setting CR50_USE_LONG_INTERRUPT_PULSES controls new code running in verstage, which will program a new Cr50 register, provided that Cr50 firmware is new enough to support the register. This CL adds code to detect the case when Cr50 is unable to generate longer pulses, and in that case explicitly disable the S0i3.4 substate as well as setting gpio_pm_override to all zeroes. This will increase power usage slightly, but guarantee that the GPIO block in the SoC does not switch to a slower sampling clock. In practice, this case will only be encountered in the factory, before the Cr50 chip is updated to a new RW image. (Prior to this change, the gpio_pm_override was hardcoded to zero for Volteer, but the S0i3.4 substate was not disabled. According to my conversations with Intel engineers, that was not enough to guarantee detection pulses shorter than 100us. But it is entirely possible that we have just been "lucky" that the SoC has not gone into low power mode during the boot process, where most of the cr50 communication happens.) TEST=util/abuild/abuild -t GOOGLE_VOLTEER -c max -x BUG=b:154333137 Change-Id: Idef1fffd410a345678da4b3c8aea46ac74a01470 Signed-off-by: Jes Bodi Klinke <jbk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-08mb/google/kukui: Add LPDDR4X Samsung K4UBE3D4AA-MGCR 4GB supportKevin Chiu
Support 4GB Samsung K4UBE3D4AA-MGCR discrete DDR bootup. BUG=b:162379736 BRANCH=kukui TEST=emerge-jacuzzi coreboot Change-Id: I2f4f084ece067e9884c23004506b450a281a77a6 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45101 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-08hatch: Create dooly variantTony Huang
Create the dooly variant of the puff reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.1.2). BUG=b:155261464 BRANCH=puff TEST=util/abuild/abuild -p none -t google/hatch -x -a make sure the build includes GOOGLE_DOOLY Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Change-Id: I8e714cc9bf4a49266da77db88f8c4a3ca45878d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45026 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sam McNally <sammc@google.com>
2020-09-07mb/google/zork: update TS power control for dirinbozKevin Chiu
3.6 schematic will separate TS power from eDP PP3300 to GPIO for power control and correct GPIO assignment from GPIO_90 to GPIO_32 instead. BUG=b:161579679 BRANCH=zork TEST=emerge-zork coreboot Change-Id: Ieef67e1d04201c5d9e1dc625c519e6d0307c55f0 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-06mb: remove duplicated Make code for spd.bin generationMichael Niewöhner
Drop duplicated code for spd.bin generation that is provided globally in lib/Makefile.inc. For all affected boards it has been verified that the output binary functionally matches the original one. The changed execution order of Make instructions influenced the cbfs file order. Hence, the rom images can't be compared directly. Thus, the output files of the two timeless abuild runs have been compared. Further, it was verified that the final files in cbfs stay identical, by comparing the extracted cbfs of each board. The boards (possibly) needing modification could be found with something like this (with false positives, though): find src/mainboard -name Makefile.inc | \ xargs egrep 'SPD_BIN|SPD_DEPS' | cut -d: -f1 | sort -u Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: Icd3ac0fd6c901228554115c6350d88bb49874587 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-06mb/*: devicetree: drop now unneeded USBx_PORT_EMPTYMichael Niewöhner
Setting USBx_PORT_EMPTY is not a requirement anymore, since unset devicetree settings default to 0 and the OC pin now only gets set when the USB port is enabled (see CB:45112). Thus, drop the setting from all devicetrees. Change-Id: I899349c49fa7de1c1acdca24994ebe65c01d80c6 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-05 06:19:55 +0000