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2016-02-12link: Support native raminitVladimir Serbinenko
Change-Id: I95173c06d334a340fa2157511a1d69f38877b264 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13665 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-02-12chromebooks: Define GBB hardware IDsPatrick Georgi
This makes the test IDs the default, taken from depthcharge master (board/*/fmap.dts, hwid property). Change-Id: I25793962ac16f451f204dbba6ede6a64c847cfd5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13634 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-02-12butterfly: Make configurable MRC vs non-MRC.Vladimir Serbinenko
Change-Id: I7b1e046d5895750d350dfa851a6f51c3a3a1613f Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13659 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2016-02-12stout: Support native raminitVladimir Serbinenko
Change-Id: If64607d40a64ada8cfe4c3ad054be9d6571fc221 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13660 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-02-12Make MRC vs native a config rather than making a separate chipset for it.Vladimir Serbinenko
Tested by making lenovo x230 configurable despite pretty MRC bugs. Change-Id: Ia2a123f24334f5cd5f42473b7ce7f3d77c0e65b7 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13658 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-12mainboards: Drop remaining references to vboot indexesPatrick Georgi
Those aren't used anymore. Change-Id: If7baf2d03c47bcc6f69d63a349bbf9d5e749aeac Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13685 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-12Fix butterfly usb map.Vladimir Serbinenko
This was copied from mrc structure despite them having fields in different order. Change-Id: If10ffa3316c5fdc538a6fabf2409512bc8c3e676 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13661 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-02-12Move gpio.h to gpio.c on sandy and ivy.Vladimir Serbinenko
Change-Id: Ic9d8c2a4e5125eca20eb692ac7ed070fda6cbe32 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13657 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-12Merge sandy/ivybridge romstage flow for MRC and non-MRC.Vladimir Serbinenko
Change-Id: I11e09804ed1d8a7ae8b8d4502bd18f6be933f9fa Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13656 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-10google/veyron_speedy: remove extraneous filePatrick Georgi
veyron_speedy was deduplicated as sub-board into google/veyron, so the addition of chromeos.fmd (identical btw) wasn't useful. Change-Id: Ic4eb6f5fefb0812cae1b9c0475e3a296d7fa65b6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13646 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-09stout: Add native gfx initVladimir Serbinenko
Tested during FOSDEM. Change-Id: Id095364d6e4735256e54a68ea9ae677355dd386a Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13532 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09ivy: Add a possiblity for mainboard early init.Vladimir Serbinenko
This is needed for stout EC init. Change-Id: I5c73499c17763229840152a473a2d820802ee2f6 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13535 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09chromebooks: Configure Chrome EC board namesPatrick Georgi
For devices with Chrome EC, state the "board" name(s), so they're built as part of the image. A number of EC boards aren't supported in the Chrome EC master branch, they're brought along but commented out, waiting for a port to master in the Chrome EC code base. Change-Id: Ic6ab821de55cf9b4e8b48fe5ebc603adeb8bb28b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13548 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-09google/lars: Set I2C[4] port voltage to 1.8vdavid
As the audio card needs 1.8V I2C operation. This patch adds entry into devicetree.cb to set I2C port 4 operate at 1.8V. TEST=Built & booted lars board. Verified that I2C port 4 is operating at 1.8V level Change-Id: Ia77841a26d024785d53251ca4b17afcf77f36a5b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e431e7acd85f6d7bf9d47f54ed41c48b8276071c Original-Change-Id: Iccc85a5e3bbf2b5362665036e1294a6635e38fbe Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/321000 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/13627 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09skylake mainboards: Enable backing up VBNV from CMOS to flashDuncan Laurie
Enable the option to back up Vboot non-volatile data from CMOS to flash as these boards have the necessary nvram fmap region and are using vboot2 which does not backup to the TPM. BUG=chrome-os-partner:47915 BRANCH=glados TEST=manually tested on chell Change-Id: I7bfe88f2cb7826f3315987aaf56f77df708896ce Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 35df03c5ef24406129cba920ee9af6d55458cd45 Original-Change-Id: Ia7c014fe2768c55941a65ec5605ef4fbc986151c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/324123 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13601 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09google/veyron_rialto: Remove developer mode switchAlexandru M Stan
The developer mode gpio switch on rialto is always hardcoded (through a resistor) as developer mode. We need to ignore it to allow transitions to verified mode with the virtual developer mode stuff. TEST=We can now exit dev mode on rialto Change-Id: I94a949f0973132de5fd008224af79cf612151193 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e78bb8f81eaa9c082e47ad818b64843c2565d00b Original-Change-Id: If11d752d58a5f26fc270ef01b529dad18b4cce46 Original-Signed-off-by: Alexandru M Stan <amstan@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/325861 Original-Commit-Ready: Alexandru Stan <amstan@chromium.org> Original-Tested-by: Alexandru Stan <amstan@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13626 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-04skylake boards: disable ACPI PM TimerArchana Patni
These devicetree patches set the ACPI PM Disabled variable to 1. This will disable the ACPI PM timer and remove from FADT table. BRANCH=none BUG=chrome-os-partner:48646 TEST=Build for skylake board with the PmTimerDisabled policy in devicetree set to 1. iotools mmio_read32 0xfe0000fc should return 0x2. cat /sys/devices/system/clocksource/clocksource0/available_clocksource should list only "tsc hpet". acpi_pm should be removed from this list. Change-Id: Ia66f37e13f0f2f527651418b8b5c337b56c25c7f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: db3e8130495038850c7034b89701b4a5fcf88dce Original-Change-Id: Ib1b876cfa361b8cbdde2f9e212e3da4fd724e498 Original-Signed-off-by: Archana Patni <archana.patni@intel.com> Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319362 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13589 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04google/lars: perform early init for CAR *stageAaron Durbin
In order to support both separate verstage and a verified boot after romstage one needs to ensure the proper GPIO and EC configuration been complete. Therefore, move that logic to car_mainboard_post_console_init() in car.c file which gets called in the early flow of a CAR stage (either verstage or romstage). BUG=chrome-os-partner:44827 BRANCH=glados TEST=None Change-Id: I331f25ad4764cab972af7198f6154f604d2dbeae Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2c1cb04645cbf34696e6adf48acec9d396e87ca9 Original-Change-Id: I8d14ea16b2d07bbf04c5c33e4205a85d9f21847b Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/324075 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/13585 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04google/glados: perform early init for CAR *stageAaron Durbin
In order to support both separate verstage and a verified boot after romstage one needs to ensure the proper GPIO and EC configuration been complete. Therefore, move that logic to car_mainboard_post_console_init() in car.c file which gets called in the early flow of a CAR stage (either verstage or romstage). BUG=chrome-os-partner:44827 BRANCH=glados TEST=Built glados w/ separate verstage and booted. Change-Id: I626a500c183d21f94d976e24f09af15a242fba9c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b564514a8b93f53a919fcdac3589e30dbac82124 Original-Change-Id: Icc989ec5700b3f1a144a6b41198b7dd2c2aac6f7 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/324073 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/13583 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04google/chell: perform early init for CAR *stageAaron Durbin
In order to support both separate verstage and a verified boot after romstage one needs to ensure the proper GPIO and EC configuration been complete. Therefore, move that logic to car_mainboard_post_console_init() in car.c file which gets called in the early flow of a CAR stage (either verstage or romstage). BUG=chrome-os-partner:44827 BRANCH=glados TEST=Built chell w/ separate verstage and booted. Change-Id: Ic728c2904006376fdc2b27b512f72173a2260be3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 42d190af8996fea894305ebe686afbfda5f2b8a5 Original-Change-Id: I95aeb97737d0ddfa6c53269c9d14db16ed5e47cc Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/324072 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/13582 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-02Kconfig: indent with tabs, not spaces.Martin Roth
Change-Id: I8996f8ab739a07014a4189738b5624485d752d9d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13540 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-31stout: Fix VGA PCIIDs.Vladimir Serbinenko
Change-Id: I7dcde170d0f59ea9886342c0d2c09b70b9d0d84d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13537 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-01-29google/peppy/Kconfig: Move select MAINBOARD_DO_NATIVE_VGA_INITJean Lucas
Move the default select of "Use native graphics initialization" for Peppy to the ChromeOS section as SeaBIOS (default payload) requires a vBIOS and takes twice as long to load with this option enabled. For the same reasons, this option shouldn't be enabled by default (def_bool y). Change-Id: I1f2163e0a1e4bf8e5041dad150bdf7de804fb4db Signed-off-by: Jean Lucas <jean@4ray.co> Reviewed-on: https://review.coreboot.org/13493 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-29src/: Chmod 644 all .c, .h, .asl, .inc, .cb, .hex, & Kconfig filesMartin Roth
Some trivial cleanup. Change-Id: I866efc4939b5e036ef02d1acb7b8bb8335671914 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13427 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-28soc/braswell: Fix for auto wake from S5Hannah Williams
Disabling S5 wake from touch panel and trackpad TEST=Build and boot the platform. TEST=Poweroff platform -> enter PG3 -> remove AC -> close Lid Plug AC in -> EC boots up and AP will shutdown the platform and open Lid -> platform boots to OS. Change-Id: I7b661a9f1327b97d904bac40e78612648f353e39 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/288970 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Divagar Mohandass <divagar.mohandass@intel.com> Original-Tested-by: Divagar Mohandass <divagar.mohandass@intel.com> Reviewed-on: https://review.coreboot.org/13425 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28soc/braswell: Fix issues found during static code analysisRavi Sarawadi
TEST=Build, boot to OS Original-Reviewed-on: https://chromium-review.googlesource.com/299483 Original-Reviewed-by: Aaron Durbin <adurbin@google.com> Change-Id: I738003b8dfff6a5255085d39e378e18d6ad36bcf Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/12738 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28Braswell: Separate L1 Sub State init procedure for boards.Kenji Chen
Original-Reviewed-on: https://chromium-review.googlesource.com/312743 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com> Change-Id: Ib0a891f229477cf359bff6cd02f305606468f07f Signed-off-by: Hannah Williams <hannah.williams@intel.com> Signed-off-by: Kenji Chen <kenji.chen@intel.com> Reviewed-on: https://review.coreboot.org/12750 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28intel/cyan: Disable SD Card Detect Simulation in FSPHannah Williams
CQ-DEPEND=CL:12742 Change-Id: Ifc95809e342d87f863dd60967f5b3a6ca5c0f7b3 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/13036 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28soc/braswell: Fix DSP clockfdurairx
The codec clock frequency was incorrectly set to 25MHz. The only available frequency is 19.2MHz through external clock and PLL. Original-Reviewed-on: https://chromium-review.googlesource.com/295768 Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I9bef334a5a3aaee28fcc4937180896ff49969bc5 Signed-off-by: Felix Durairaj <felixx.durairaj@intel.com> Reviewed-on: https://review.coreboot.org/12732 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22google/oak: Configurate SD card detection pinYidi Lin
BRANCH=none BUG=chrome-os-partner:47609 TEST=remove servo board connection and insert/remove an empty SD card in recovery mode. Change-Id: I89a1cb6914d634f07ff71b9793eb29b711381524 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d21bf091a576574cb9e976447ee2b9a69748d2b6 Original-Change-Id: I2083605c9ad88841885dfaad48dcd27e6fb5161d Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313073 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13099 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-22mediatek/mt8173: move rtc_boot() to romstageYidi Lin
BRANCH=none BUG=none TEST=boot to kernel Change-Id: I0630d7c172e97f81abb1722afe028542e9e7f106 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 608c66df0543c76be7e811b06718464776631b55 Original-Change-Id: I03426085121bfa44c99c351d63db28f567d0ee1d Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313969 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13097 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-22google/oak: setup usb and configure I2C level shift pinBen Lok
BRANCH=none BUG=none TEST=build pass and verified on rev3 Change-Id: I3849342e59c2b022db723ef0281cdd5153ae27cb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 495e978cd7381bd393099315ac6d60fe4446dd9f Original-Change-Id: I9626d06746e5d0bf6698a9b8e7594c58e7ff213a Original-Signed-off-by: Ben Lok <ben.lok@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292689 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13096 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22google/oak: Configure backlight control pinsYH Huang
Since backlight is controlled in depthcharge, we only configure control pins as output pin and set them power-off in the coreboot stage. BRANCH=none BUG=none TEST=Saw DEV screen during boot process. Change-Id: I3ed95e133417194ec8e774f42770bc61d879295f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e9628781801943903ba99ba1071aa374c6fc0754 Original-Change-Id: Ifd101f3e08698561d8516d83bc7d502d210e3b66 Original-Signed-off-by: YH Huang <yh.huang@mediatek.com> Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292686 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13093 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22google/oak: configure audioKoro Chen
BRANCH=none BUG=none TEST=build and verified pass on oak board Change-Id: I01eb059a3525bbbc5d17335cf43bc01be4355142 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bc2bb9f5b461ec848df8aba07940b895401004f8 Original-Change-Id: I848468cec04a36659fbb4b898dff9368305d72ac Original-Signed-off-by: Koro Chen <koro.chen@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292683 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13092 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22google/oak: Disable vboot mock data, now that I2C is functionalLiguo Zhang
BUG=none TEST=emerge-oak coreboot BRANCH=none [pg: split into multiple commits] Change-Id: I7a635c57ba271c8f568bd3334929acdf6a058ce8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2a3d867fd1e547cadc6c947f38082fddc2265d32 Original-Change-Id: I4f3a9b403b949d8ae8e3c393cc9441fb66ea5f1d Original-Signed-off-by: liguo.zhang <liguo.zhang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292667 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13078 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22google/oak: Enable MMU supportJimmy Huang
BRANCH=none BUG=none TEST=build pass [pg: split into multiple commits] Change-Id: I6e165cfa6a8345de3d8d5461a75d5ed626ece4ef Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3ee2a20ec56359e917bb8f4825846c54d4f6276a Original-Change-Id: Iedc81a85569b00524620e9ba128e7d77f17b0405 Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292666 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13077 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22google/oak: Add support for verstageItamar
Add support for verstage [pg: split original commit into multiple commits] Change-Id: I8c9fe02f26bf8fa8381a7502a778bed300684986 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2827aa08ff8712c0245a22378f3ddb0ca054255d Original-Change-Id: I94a9ee2c00e25a37a92133f813d0cd11a3503656 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292662 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13052 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22google/oak: Enable SPI supportLeilk Liu
BUG=none TEST=emerge-oak coreboot BRANCH=none [pg: split into multiple commits] Change-Id: I19f970db40fb8563ef1b782a9606ca3766ef2ac5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 41acc14e9fe54924d20e4e5a2d1519251f0e1c87 Original-Change-Id: I2559be4191da9af523944563729171bd92a86cd0 Original-Signed-off-by: Leilk Liu <leilk.liu@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292661 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13076 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22Cyan: Update DPTF parameters for higher temperatureT.H.Lin
TEST=Run DPTF CQ-DEPEND=CL:12729 Original-Reviewed-on: https://chromium-review.googlesource.com/295478 Original-Tested-by: T.H. Lin <T.H_Lin@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ifa58ad72105d377c00df577f0e16ff1148b70119 Signed-off-by: T.H. Lin <T.H_Lin@quantatw.com> Reviewed-on: https://review.coreboot.org/12747 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-22google/cyan: Add Wifi regulatory methodHannah Williams
WRDD method in wifi.asl returns the regulatory domain code. This value is read from VPD in wifi_regulatory_domain() and saved to global nvs if CONFIG_HAVE_REGULATORY_DOMAIN is enabled. It returns default code if CONFIG_HAVE_REGULATORY_DOMAIN is not enabled. Change-Id: I6e96bdf0fe93ae30a3afdcb63a0f89ce21023704 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/13055 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22skylake mainboards: Enable CONFIG_VBOOT_EC_SLOW_UPDATEDuncan Laurie
Updating EC+PD takes long enough to update that it is good to show the "critical update" screen when doing an EC/PD update. BUG=chrome-os-partner:49650 BRANCH=glados TEST=Build and boot on chell in normal mode with an EC update payload and ensure that it reboots to enable graphics, shows the "critical update" screen, and then reboots to disable graphics init again. Change-Id: I436b96b95595b68273e594bdcfe2db0789ee26b2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 08e45decd066f8f57ad103ff8b76cb7a916afa9e Original-Change-Id: Ie250f4531437e4a0ce14b5aeb0fe564e9461fe4d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/322783 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13075 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22intel/skylake: PL2 override changespchandri
Override the default PL2 values with ones recommended by Intel. BUG=chrome-os-partner:49292 BRANCH=glados TEST=MMIO 0x59A0[14-0] to find PL1 value (0x78) / 8 Watts = 15W MMIO 0x59A0[15] to find PL1 enable/disable = Disable MMIO 0x59A0[46-32] to find PL2 Value (0xC8) / 8 Watts = 25W Here PL2 is set to 25W and PL1 is disabled. CQ-DEPEND=CL:321392 Change-Id: I338b1d4879ae1b5f760e3c1d16e379a2baa1c965 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fa6a115227385bef44abfacf58af306c16ed478a Original-Change-Id: I3bfc50256c9bdd522c984b11faf2903d7c44c81f Original-Signed-off-by: pchandri <preetham.chandrian@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/322454 Original-Commit-Ready: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Original-Tested-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Preetham Chandrian <preetham.chandrian@intel.com> Original-Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/13071 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22google/veyron_*: Add dual-rank 2GB Hynix module to SDRAM configsDavid Hendricks
This is a follow-up to CL:320623 to make veyron DRAM configs uniform (except for Rialto). As discussed in chrome-os-partner:43626, the mr[3] value and ODT are set diffently for Mickey, thus the .inc files for other boards have mr[3] = 1 and ODT disabled. BUG=none BRANCH=veyron TEST=compile tested for veyron Change-Id: I61798cfef779b0a3a510fd354ab53ffc63ca6c95 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3b7cea6331bcec8aba09a204060e093d3dd732cb Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: Iacf821645a2dcceaed1c1c42e3e1b1c312b31eab Original-Reviewed-on: https://chromium-review.googlesource.com/321870 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13109 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2016-01-21chromeos: import Chrome OS fmapsPatrick Georgi
These are generated from depthcharge's board/*/fmap.dts using the dts-to-fmd.sh script. One special case is google/veyron's chromeos.fmd, which is used for a larger set of boards - no problem since the converted fmd was the same for all of them. Set aside 128K for the bootblock on non-x86 systems (where the COREBOOT region ends up at the beginning of flash). This becomes necessary because we're working without a real cbfs master header (exists for transition only), which carved out the space for the offset. Change-Id: Ieeb33702d3e58e07e958523533f83da97237ecf1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12715 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-21google/veyron_mickey: Update Hynix memory configurationLang Zhang
Update Hynix memory configuration for mickey so that it can boot on Hynix board. BUG=chrome-os-partner:48637 BRANCH=master TEST=Boot on mickey hynix board Change-Id: Ibbf90cf76793005e23a720b97540b268ebf0864d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 071167b667685c26106641e6899984c7bd91e84b Original-Change-Id: Id63d74cac36b9fd84bdb88969291982e14fa7d01 Original-Signed-off-by: Lang Zhang <kingsley_zhang@asus.com> Original-Reviewed-on: https://chromium-review.googlesource.com/320623 Original-Commit-Ready: lang zhang <kingsley_zhang@asus.com> Original-Tested-by: lang zhang <kingsley_zhang@asus.com> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://review.coreboot.org/13048 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-21google/tidus: initial upstream migrationMatt DeVillier
Migrate google/tidus (Lenovo ThinkCentre Chromebox) from Chromium tree to upstream, using google/guado as a baseline. TEST=built and booted tidus with full functionality Change-Id: I9d7a976345566bee63226d1a44ba7d5ec137a742 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/12801 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-19google/chell: Adjust nuvoton 8825 button thresholds, add propertiesBenson Leung
Set "nuvoton,sar-threshold" property to thresholds based on tuning with the Android Wired Headphone Compatibility Kit and Chell EVT. Also set properties nuvoton,sar-compare-time and nuvoton,sar-sampling-time. The values of compare and sampling time align with the ones from this CL: https://chromium-review.googlesource.com/306372 Signed-off-by: Benson Leung <bleung@chromium.org> BUG=chrome-os-partner:49333 BRANCH=none TEST=Run evtest, selecting the input event for sklnau8825adi Using the Nominal headphones from the kit, check that the buttons for "KEY_VOLUMEDOWN", "KEY_VOLUMEUP", "KEY_MEDIA", and code 582 (?) (should be voice search, but evtest doesn't understand) All of these buttons should work properly. Change-Id: I43dc1957f7d95744f41039a306d323806e66c56a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2bb545500afeb5b4fa0d1cd02dbf6453f19901ab Original-Change-Id: I126aae1e5ed1b9e1a2429e8c94fe08b3ba3ca736 Original-Reviewed-on: https://chromium-review.googlesource.com/322243 Original-Commit-Ready: Benson Leung <bleung@chromium.org> Original-Tested-by: Benson Leung <bleung@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13013 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19google/chell: Modify DqsMapMike M Hsieh
Modify Dqs Byte Swizzling for channel 0 to honor chell's memory routing BUG=chrome-os-partner:48986 BRANCH=glados TEST=verified on chell system Signed-off-by: Mike Hsieh <mike.m.hsieh@intel.com> Change-Id: Ic0485526bc1378e329c5eb0eeb57ff67a9501e86 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b60241e63381974655f5df5afcd913e95c17682b Original-Change-Id: I641502e8d303fa59e0f668d581745379e1ef4853 Original-Reviewed-on: https://chromium-review.googlesource.com/321524 Original-Commit-Ready: Duncan Laurie <dlaurie@chromium.org> Original-Tested-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/13012 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19google/chell: Add new memory part for DVT buildDuncan Laurie
After comparing datasheets it appears to have the same geometry and timings as the K4E6E304EE-EGCF part with just a new part number. BUG=chrome-os-partner:49357 BRANCH=glados TEST=build and boot on chell EVT (new part is not used until DVT) Change-Id: Ia1e67080b1d79600e00c3ea8bee088ecafea2ab2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fb1488ca5ff780b5f1f937dbf0d23610c28204b2 Original-Change-Id: I09e1ce1a45a217afc88f422cf7db7924fad6b6f9 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/321956 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13011 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-01-19google/chell: Set FSP params for min assertion widths and serirqDuncan Laurie
- Enable serial irq configuration in FSP. - Set minimum assertion width values for FSP to configure. - Set I2C4 voltage to 1.8V. - Enable SaGv feature to dynamically train memory frequency. BUG=chrome-os-partner:47688 BRANCH=none TEST=build and boot on chell EVT Change-Id: If6955c9ee4f08d1ebc6e98e0ba0786073919856f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7403149299ec2c6c66c2066a5dd8294608e71409 Original-Change-Id: Ia182396ad4eb7a283e183fce7c50c98f6d2de57c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/321212 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13009 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-31 21:47:10 +0000