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2018-09-21google/kukui: Set up EC_IN_RW GPIO for ChromeOSTristan Shieh
Set up EC_IN_RW GPIO to boot depthcharge. Without this patch, depthcharge will fail to tell if the EC firmware is RW. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui and see in logs, that depthcharge detects EC_IN_RW GPIO. Change-Id: Icb39d663f65b72e0ad54059c9590d9693106ee25 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/28670 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-21mb/google/poppy/variant/nocturne: set DMIC1 to NCNick Vaccaro
Change GPP_D17 and GPP_D18 to no connects as DMIC was moved to DMIC0. BUG=b:113744731,b:111106010 TEST=none Change-Id: I8ef42627e542182707c81389af9da33a114bc184 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/28689 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-21mainboard/google/kahlee: allow oem.bin file to update smbiosMartin Roth
Grunt variants need a way to customize the mainboard vendor based on the platform. For future boards, this can probably be done via CBI, but grunt doesn't support that method. BUG=b:79874904 TEST=Build, boot, see updated mainboard vendor Change-Id: I997dc39c7f36f70cf4320ef335831245889eb475 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/28651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@google.com>
2018-09-21mb/google/octopus/variants/fleex: Update DPTF parametersSumeet Pawnikar
Update Power Limit1 and Power Limit2 values along with stepsize. Correct the charger effect for Temperature sensor2. BUG=b:112448519 BRANCH=None TEST=Build coreboot for Octopus board. Change-Id: I01e0a94fe694537d9eebe3b92c11d0c83137d716 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/28530 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-20mb/google/zoombini: Use Chrome EC BOARDID definitionKarthikeyan Ramasubramanian
The board_id() definition is the duplicate of chrome EC board_id definition. Remove the duplicate definition and select EC_GOOGLE_CHROMEEC_BOARDID Kconfig item. BUG=b:114001972,b:114677884,b:114677887 Change-Id: Id8b7027d653649e8e5791e455652c4e893a746c2 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@codeaurora.org> Tested-by: Karthikeyan Ramasubramanian <kramasub@codeaurora.org> Reviewed-on: https://review.coreboot.org/28609 Reviewed-by: Jett Rink <jettrink@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-20ec/google/chromeec: Update google_chromeec_get_board_version prototypeKarthikeyan Ramasubramanian
The helper function to get the board version from EC returns 0 on failure. But 0 is also a valid board version. Update the helper function to return -1 on failure and update the use-cases. BUG=b:114001972,b:114677884,b:114677887 Change-Id: I93e8dbce2ff26e76504b132055985f53cbf07d31 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Tested-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/28576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@google.com>
2018-09-20mb/google/poppy/variants/nocturne: Update DPTF settingsPuthikorn Voravootivat
Update DPTF settings based on recommendation from thermal team. BUG=b:112550414 BRANCH=None TEST=Manually tested by thermal team. Change-Id: I26f09392a3293ce4b3481f2be341a667d606bc10 Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-on: https://review.coreboot.org/28666 Reviewed-by: Todd Broch <tbroch@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-20mb/google/octopus: Enable DRAM_PART_NUM_IN_CBI feature for meepWisley Chen
Enable DRAM_PART_NUM_IN_CBI feature to get DRAM part number from CBI and set DRAM_PART_IN_CBI_BOARD_ID_MIN to 1 for EVT. BUG=b:115965629 TEST=verified it in meep proto board which rework ram id. Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Change-Id: I962b099d5b9fbe0ca29708be1e9c6ed60b10d363 Reviewed-on: https://review.coreboot.org/28658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-09-18mb/google/kahlee/variants/careena/devicetree.cb: Set STAPM valuesRichard Spiegel
AMD has tested careena, and for the time being is recommending a scalar of 68%, power limit of 7.8 W and time constant of 2500. Using new STAPM configuration code, set the desired values. BUG=b:111561217 TEST=none, code was tested with grunt. Change-Id: I42671ab0e66b21dc4f8c8c326c1fa33328b1390e Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-09-18mainboard/google/kahlee: Set EMMC reset pin to output lowMartin Roth
While the pin was set to a pull-down, with the external pull-up, this wasn't enough to keep the pin low. Set to output low to drive to 0V. TEST=Boot grunt, verify EMMC_BRIDGE_RST is 0V. BUG=b:115661061 Change-Id: Ife014b8a879274df5d892c1de386976808de1df0 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/28649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-09-18mainboard/google/kahlee: Don't set global subsystem IDsMartin Roth
These values override the default subsystem IDs, and aren't needed. BUG=b:113253260 TEST=Boot grunt Change-Id: I3c56534b094ede8d8200b72f4433a891d0094064 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/28652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-09-17mb/google/kahlee/variants/baseboard: Set STAPM percentageRichard Spiegel
Default STAPM percentage causes a lot of thermal throttling on grunt. AMD experimented with 80%, it works for grunt. This is initial code to provide easy change path for other grunt based platforms. BUG=b:111608748 TEST=build and boot grunt. Change-Id: I22863f6ed76152bf872fce3e275f8a7fd8077504 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-17google/buddy: Add board as variant of google/auronMatt DeVillier
Add google/buddy (Acer Chromeboase 24) as a variant of google/auron, with the following changes: - add buddy-specific variant code - add handling to auron for buddy's lan init, which no other variants have - add handling to auron's mainboard ACPI due buddy having different PCIe port assigments than all other variants Ported from Chromium branch firmware-buddy-6301.202.B, commit ebb82ce [Buddy: Lock management engine + SPI descriptor] Test: build/boot Linux on google/buddy using SeaBIOS and Tianocore payloads Change-Id: Ib76eef47677b72ddaef81a2decef189a5f20c20a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/28613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-17google/auron: Clean up variant-specific romstage codeMatt DeVillier
Use an empty weak function for variant_romstage_entry(), rather than having separate empty functions for boards which don't utilize it. Change-Id: I7a278ed716484bea377a5dd98d4a534502c8bab6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/28612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-16google/kukui: Configure EMMCTristan Shieh
Set up EMMC gpios for payloads. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: I1e7ee9bfe3a26ed04374e8c74243f48552a1d254 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/28546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-09-16mb/google/poppy/variants/rammus: fix S0ix entering issueZhuohao Lee
As we don't use the MIPI camera on Rammus, disable SA Imaging Unit and CIO2 devices to avoid the system failed to enter S0ix. BUG=b:114502527 BRANCH=master TEST=On DUT, echo freeze > /sys/power/state 1. check the S0ix status on EC console 2. check the value of /sys/kernel/debug/pmc_core/slp_s0_residency_usec Change-Id: I91629732db01ee534f0ddb67a2b358d725ef810e Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/28543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-16google/kukui: Notify EC that AP is in S0Hung-Te Lin
We have a pin from AP to EC, called AP_IN_SLEEP_L (SRCLKENA0 on AP side, pad R23) that is supposed to be high in S0, and low in S3 (and X/don't care in S5). This should be set as early as possible in bootblock. BUG=b:113367227 TEST=make; boots and verified AP_IN_SLEEP_L GPIO is high. BRANCH=None Change-Id: Icd59fa366c162e7443b8932a851e65f110f551ab Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/28585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@google.com>
2018-09-16mb/google/poppy: Set UPD CmdTriStateDis for AtlasCaveh Jalali
This patch sets the MRC UPD CmdTriStateDis for the atlas boards. Atlas is a LPDDR3 design without RTT for CMD/CTRL. The original change for nocturne is I0f593761dcbd121e7e758421af178931b9d78295 mb/google/poppy: Set UPD CmdTriStateDis for Nocturne BUG=b:111812662 Change-Id: I45b6dd22412c689c8db64f4650e9fa9e87dec2ec Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/28540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-09-14mb/google/octopus: Query the EC for board versionKarthikeyan Ramasubramanian
The board version is part of EC's EEPROM, but is not being populated from EEPROM. Instead a default Kconfig parameter is returned as board version. Select GOOGLE_SMBIOS_MAINBOARD_VERSION Kconfig item to enable requesting the EC for board version. BUG=b:114001972,b:114677884,b:114677887 Change-Id: Ib404a9da35156e197d232088fd7ca69432effbca Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Tested-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/28539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-14mb/google/octopus: fetch DRAM part number from CBI for phaser after DVT phasepeichao.wang
This modification for DVT build and use CBI method enable all memory particles. BUG=b:112870780 TEST=verify it under the EVT unit and pre-test EVT unit(rework RAM ID follow the proposal) respectively. Change-Id: I488a0652ba348eff9a6d8591b0cfa6ed4fe808aa Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-12mainboards: Add SMMSTORE region in chromeos configsPatrick Georgi
Only for those that are x86 and also have a RW_LEGACY region. The assumption is that all devices touched have 64k block sizes when choosing size and alignment of the region. Change-Id: I12addb137604f003d1296f34f555dae219330b18 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/28532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-12rammus: add SPD mapping for rammus and shyvana supportkane_chen
Add MICRO 4G and 8G SPD file. BUG=none BRANCH=master TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, and make sure system boots up. Change-Id: I7cb5b7f2bcdc6fbe0cbc640cad4af014f1a0edd6 Signed-off-by: YanRu Chen <kane_chen@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28484 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-10mb/google/poppy/variants/nami: Add SPD for two memory partsRen Kuo
add two memory parts and ram id: hynix_dimm_H5ANAG6NCMR-VKC micron_dimm_MT40A1G16KNR-075E BUG=b:113983573 BRANCH=Nami TEST=emerge-nami coreboot chromeos-bootimage Change-Id: Ia052f16b6c1e64ee6458fbdeea56a482a728c35a Signed-off-by: Ren Kuo <Ren.Kuo@quantatw.com> Reviewed-on: https://review.coreboot.org/28536 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-10mainboard/google/poppy/variants/rammus: Enable DA7219marxwang
On rammus, headset uses DA7219 so that we need to enable it. BUG=b:112945714 BRANCH=master TEST=emerge-rammus coreboot chromeos-bootimage Flash FW and check in kernel to see if DA7219 is up. Change-Id: I92dd412374d007aab264661e698fbbbbcf1eae45 Signed-off-by: marxwang <marx.wang@intel.com> Reviewed-on: https://review.coreboot.org/28537 Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-10mb/google/poppy: Set UPD CmdTriStateDis for NocturneShaunak Saha
This patch sets the MRC UPD CmdTriStateDis for the nocturne boards.Nocturne is LPDDR3 design without RTT for CMD/CTRL. BUG=b:111812662 TEST=Run memtester app and also webgl fishtank on the LPDDR3 kabylake boards and also check the margin data is proper in FSP. Change-Id: I0f593761dcbd121e7e758421af178931b9d78295 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/28379 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-09drivers/vpd: Add VPD supportPatrick Rudolph
VPD reference: https://chromium.googlesource.com/chromiumos/platform/vpd/+/master/README.md Copy ChromeOS VPD driver to add support for VPD without CROMEOS. Possible use case: * Storing calibration data * Storing MAC address * Storing serial * Storing boot options + Now it's possible to define the VPD space by choosing one of the following enums: VPD_ANY, VPD_RW, VPD_RO. + CHROMEOS selects now VPD as part of it. + VPD is implemented as driver. Change-Id: Id9263bd39bf25d024e93daa57053fefcb1adc53a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25046 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-09mainboard/google/kahlee: Reset trackpad & touchscreenMartin Roth
AMD chips don't hold off a reset to the end of I2C transitions, so devices on the i2c bus can be left in a bad state. To avoid this, make sure the trackpad and touchscreen chips get disabled during boot. BUG=b:114411165 TEST=build, reboot watch trackpad enable go low Change-Id: Ie50f4a102249df79517da571a6e768dba804cd57 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/28538 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-07mb/google/poppy/variants/atlas: enable NVMeCaveh Jalali
This adds support for a x2 NVMe device on PCIe bus PCIe lines 5+6 and clock#4. BUG=b:113369699 TEST=booted on atlas Change-Id: I08e7c4d65662ddbb7d936915c896eb1fcb240ba8 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/28535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-09-06mb/google/octopus: Configure H1 interrupt pad using Rx level configFurquan Shaikh
This change configures GPIO_63 (which is used for H1 interrupts) as Rx Level. This ensures that the signal gets passed on to the next logic state as is and the APIC entry can be configured to trigger interrupt on level or edge as per the kernel driver expectation. TEST=Verified that no H1 interrupt timeouts are seen with 100 iterations of warm and 100 iterations of cold reboot. Change-Id: I7aac30300a4251d9b40276dcca7ebc6a6d814c40 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-06mainboard/google/poppy/variants/rammus: Enable GSPI clock for bus 0.kane_chen
On rammus, system halt was observed because of gspi clk value being set to 0. Log info from serial coreboot: FMAP: area RW_NVRAM found @ 9fa000 (24576 bytes) SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000 VBNV: Restore from flash failed ASSERTION ERROR: file 'src/soc/intel/common/block/gspi/gspi.c', line 443 gspi.c 442 443 assert(gspi_clk_mhz != 0); 444 assert(ref_clk_mhz != 0); 445 return (DIV_ROUND_UP(ref_clk_mhz, gspi_clk_mhz) - 1) & SSCR0_SCR_MASK; BUG=none BRANCH=master TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, and make sure system boots up. Change-Id: Ibe3937902901b2cdc1a196415c08fabb0f3155f2 Signed-off-by: YanRu Chen <kane_chen@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28405 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-06mb/google/poppy/variants/nocturne: Enable DMIC CLK0/DATA0Sathyanarayana Nujella
DMIC's are now connected to DMIC_CLK0/DMIC_DATA0. So, enable the pins accordingly. BUG=b:113744731,b:111106010 BRANCH=none TEST='emerge-nocturne coreboot chromeos-bootimage' builds the image Change-Id: I48cace3c6099a2853fcb377c695a5e325094baf6 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Signed-off-by: Harsha Priya <harshapriya.n@intel.com> Reviewed-on: https://review.coreboot.org/28433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-06mb/google/poppy/variants/nautilus: Bump VCC_SA voltage offset 75mVSeunghwan Kim
Nautilus-Wifi with m3 AP got a halt issue during CTS test. Nautilus-Wifi was FCS with Celeron AP first and also its PCB/BOM was validated only with Celeron. Since Celeron deos not support turbo boost mode, its steady power demend and lower CPU frequency may not reflect the potential noise hidden inside the board. Bumping VCC_SA voltage offset 75mV confirmed works to mitigate the potential noise coupling to VCC_GT/SA, and we verified this change makes this issue go away on Nautilus-Wifi board. Nautilus-LTE doesn't show this issue, since it has 10L PCB, will have better grounding and less noise/ripple than 8L PCB. BUG=b:111417632 BRANCH=poppy TEST=Verified CTS test pass without an issue. Change-Id: Id13fcc36a5b6ed42620c66f57a7303f30bff1a50 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/28439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-06mb/google/octopus: Enable TBMC deviceAmanda Huang
This change enables tablet mode ACPI device for all octopus boards. BUG=b:113348027 Change-Id: I69a5dd41cd0958b93f8eed338fed4b6ee77a178f Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28466 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-05mainboard/google/kahlee: Enable the BCLK bufferMartin Roth
Set GPIO135 high to enable audio through the BCLK buffer. BUG=b:113559558 TEST=None BRANCH=grunt Change-Id: I1dcecf5960d3c91e0c2165e7f8856ff423c06e8c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/28482 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-04mb/google/poppy/variants/rammus: add sku info into smbios tableZhuohao Lee
This patch adds the mainboard.c in order to support the sku id in smbios table where the sku id is queried from the eeprom via EC. BUG=b:113714761 BRANCH=master TEST=check the result of 'dmidecode' Change-Id: I3413784cca1ac10a2468d84f2d06c0e1d701fdcb Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/28426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-02mb/google/poppy/Kconfig: Fix missing device node /dev/tpm0 for H1Zhuohao Lee
This patch adds the DRIVERS_SPI_ACPI to enable the tpm device node. Without DRIVERS_SPI_ACPI, the kernel will popped out the below error: cr50-update[592]: Starting cr50 update cr50_get_name[595]: updater is /usr/sbin/gsctool -s cr50-update[609]: exit status: 3 cr50-update[613]: output: Could not open TPM: No such file or directory cr50_get_name[615]: board_id: '' board_flags: '0x', extension: 'prod' cr50-update[617]: hashing /opt/google/cr50/firmware/cr50.bin.prod cr50-update[678]: current state 3 in /var/cache/cr50.a3055efbc9.state cr50-update[682]: not running cr50-result[782]: Not running normal image. Skip setting Board ID trunksd[795]: TPM: Error opening tpm0 file descriptor at /dev/tpm0: No such file or directory BUG=none BRANCH=master TEST=/dev/tpm0 is created Change-Id: I35287c6c54299c2677c41fc830675570b9d45a94 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/28400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-02mainboard/google/kahlee/var/liara: Enable Synaptics touchpad deviceCrystal Lin
Enable Synaptics touchpad device for liara BUG=b:113309346 BRANCH=master TEST=Verify touchpad on liara works with this change Change-Id: Icdafe34a00fd55d5338fa07ffa304e48e7b85e7b Signed-off-by: Crystal Lin <crystal_lin@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-31google/cheza: Adjust FMAP to fit new requirementsJulius Werner
This patch overhauls the Cheza FMAP, removing some sections we don't seem to need (RW_CDT, the two RW_XBL_BUFFERs, and the second copy of RW_DDR_TRAINING), and adding new sections we're going to need soon or should have had anyway (RO_DDR_TRAINING, RO_FSG, RW_LEGACY). Make more use of implicit offsets and sizes, because we can and because it should make future adjustments easier. Change-Id: I0bd9e59e9cfa162c478c4bd1f048fcac61ad5062 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/28403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: T Michael Turney <mturney@codeaurora.org>
2018-08-31mb/google/kahlee/variants/liara: Update Audio/H1/TP i2c timingsChris Zhou
After adjustment on Liara Proto Audio: 399.2 KHz H1: 398.3 KHz TP: 399.0 KHz BUG=b:113319200 BRANCH=master TEST=emerge-grunt coreboot chromeos-bootimage measure by scope Change-Id: Ibba8c823ed8451a804cf731d49e7568a94ac7c6b Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-08-30mb/google/poppy/variants/nautilus: Set grip sensor thresholdSeunghwan Kim
Set threshold parameter for grip sensor STH9321 .ProxCtrl6: 75 .ProxCtrl7: 99 BUG=b:113303916 BRANCH=poppy TEST=Built and verified parameter passed to driver Change-Id: I8a410a23b5e3831fc8e90118b810fc2409a026eb Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/28381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Enrico Granata <egranata@chromium.org>
2018-08-30mb/google/octopus: Add missing IOstandy settings.Shamile Khan
Also removed internal pull ups for CX_PREQ_L and CX_PREQ_L signals as they have external pull ups. BUG=b:110654510 TEST=On Yorp Proto 2, flashed image and verified that it boots to OS. Checked Wake-on-Wifi works with both cnvi and pcie modules. Also executed a few suspend resume cycles. Change-Id: I0a76cd2a1481c828fc092aaf7e870a411624879c Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/28328 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-29mainboard/google/kahlee: Enable EC firmware update screenMartin Roth
Grunt takes a few seconds to update the EC, so display a notification screen while that's happening. BUG=b:113286040 TEST=Boot Grunt with old EC firmware, see update screen Change-Id: I95fc4d3430bac66c09f57a4d34abde08752e5f0e Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/28374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-08-28mb/google/octopus/variants/meep: Add weida touchscreen supportTony Huang
Add weida touchscreen support BUG=none BRANCH=master TEST=emerge-octopus coreboot, and verified that touchscreen works on meep. Change-Id: I4352322820237e4c2289410af6643e15109060a1 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-28soc/intel/cannonlake: Change LPDDR4 to MEMCFGLijian Zhao
Modify the previously SOC_CNL_LPDDR4_INIT to SOC_CNL_MEMCFG_INIT, to make the infrasturture to handle both LPDDR4 and DDR4 cases in the future. Consider the case of reading SPD from SMBus other than providing SPD pointer directly. BUG=N/A TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a" compiles successfully. Change-Id: I2f898147f67dd52b89cc3d9fc4e6b3854fa81f57 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28248 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-28google/kukui: Init SPI bus for ECTristan Shieh
Set EC SPI bus config and init SPI bus according to the config. BUG=b:80501386 BRANCH=none TEST=EC is not working yet. This makes depthcharge go forward a little. Change-Id: Id9209b6429417430cfcf7f5a5a1659e7e4bc7866 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/28251 Reviewed-by: Joel Kitching <kitching@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-28google/kukui: Set up GPIOs for ChromeOSTristan Shieh
Set up EC interrupt GPIO to boot depthcharge. Without this patch, depthcharge will fail to detect EC interrupt GPIO. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui and see in logs, that depthcharge detects EC interrupt GPIO. Change-Id: I0ec2c70c189a059219954e0384aaf98995285728 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/28250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-08-28google/grunt: Reset BayHub EMMC freq to SD base CLK 50MHzKevin Chiu
Bayhub eMMC controller default runs SD base 50MHz at the first power on. After boot into OS, mmc kernel driver will config controller to HS200/208MHz and send MMC CMD21 (tuning block). But Bayhub PCR register 0x3E4[22] (eMMC MODE select) is not clear after system warm reset. So eMMC will still run 208Mhz but there is no block tuning cmd in depthcharge. It will cause two Sandisk eMMC (SDINBDA4-64G-V/SDINBDA4-32G-V) to fail to load kernel and trap in 0x5B error (No bootable kernel found on disk). BUG=b:111964336 BRANCH=master TEST=emerge-grunt coreboot Change-Id: Ic080682e67323577c7f0ba4ed08f8adafca620cc Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/28353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-27mb/google/poppy/variants/atlas: Update DPTF parametersTodd Broch
Reduce the CPU passive threshold sample rate from 5 seconds to 1 second so DPTF will react faster to rapid temperature increases. Signed-off-by: Todd Broch <tbroch@chromium.org> BUG=b:113101335 BRANCH=atlas TEST=manual performance/power testing on nocturne. No longer see messages like below in syslog, 'CPU0: Package temperature above threshold' Change-Id: I2dc9d157b54500bae29e123978bb8ad6e05ef619 Reviewed-on: https://review.coreboot.org/28325 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-27mb/google/poppy/variants/nocturne: Update DPTF parametersTodd Broch
Reduce the CPU passive threshold sample rate from 5 seconds to 1 second so DPTF will react faster to rapid temperature increases. Signed-off-by: Todd Broch <tbroch@chromium.org> BUG=b:67459049 BRANCH=nocturne TEST=manual performance/power testing on nocturne. No longer see messages like below in syslog, 'CPU3: Package temperature above threshold' Change-Id: Ic20c718fd3a496db7c7192feec4f230d924cc458 Reviewed-on: https://review.coreboot.org/28324 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-27mb/google/octopus/variants/baseboard: Update DPTF parametersSumeet Pawnikar
Update TSR1 trip point from 48C to 50C. Also, change power limit2 minimum value from 8W to 10W. These are the values as per recent thermal tuning. BUG=b:79779737 BRANCH=None TEST=Build coreboot for Octopus board. Change-Id: I33a9d2dc3e0e5566d95b1f1e46d3922dc8965b2b Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/28187 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 17:06:30 +0000