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2019-02-18mb/google/sarien: Swap FMAP location for RW_LEGACY and NVRAMDuncan Laurie
The Intel SOC can only shadow the top 16MB of SPI into memory so in order to make it easier to access the NVRAM region with memory mapped interface move it above the much larger RW_LEGACY region. I tested to confirm that this region can now be read via MMIO interface and does not need to use the hwseq SPI controller. Change-Id: Iafacb01eec07beaf474b6a1f2b36a77117e327da Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/31436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-02-18mb/google/sarien: Create VR config settingsRoy Mingi Park
Create VR settings configuration as per board design. BUG=N/A TEST=Build and boot up into sarien platform. Change-Id: Ic196fd80e5211bd5146158d4d340b52c850a4e62 Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com> Reviewed-on: https://review.coreboot.org/c/31404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-02-18mb/google/kahlee: Enable mode change as wake source for S3Mengqi Guo
This change enables mode change as a wake source for S3. BUG=b:124132058 Change-Id: I95b1eac800858ab17cdf69bdd3f2c5828516c184 Signed-off-by: Mengqi Guo <mqg@chromium.org> Reviewed-on: https://review.coreboot.org/c/31429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-18src/mainboard/kahlee: Remove delan variantMartin Roth
BUG=b:121354442 TEST=None Change-Id: I348c7106772eecd513baf9abe60ef19008d0ba4d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/31424 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-18mb/google/sarien/variants/arcada: Update thermal configuration for DPTFCasper Chang
Update dptf for arcada EVT. BUG=b:123924662 TEST=Built and tested on arcada system Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: Ieed8021b83776fdb6320ff89b57c8d2747667fd5 Reviewed-on: https://review.coreboot.org/c/31331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2019-02-18mb/google/laser: Disable touch screen device that according to SKU IDpeichao.wang
We need disable touch screen device on laser SKU ID 6. BUG=none TEST=according to sku_id (Laser(convertible): 5, Laser14(clamshell): 6, Laser14(clamshell + touch):7) distinguish whether disable touch screen device. Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I6953c35a5e8c93d88fe63362156faa351e8ee71f Reviewed-on: https://review.coreboot.org/c/31428 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-15mb/google/hatch: Enable DPTF functionalitySumeet Pawnikar
Enable DPTF functionality on hatch platform. Change-Id: If9ef74364616f95b27b73c39fea42d2623d78ae2 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/31276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-15mb/google/octopus: Fix USB ACPI configuration for CNVi BT moduleKarthikeyan Ramasubramanian
CNVi Bluetooth module is at port 8 (zero-indexed) and not at port 9. Fix the device configuration in the devicetree. BUG=b:123296264 BRANCH=octopus TEST=Boots to ChromeOS. Checked the SSDT table to ensure that the reset gpio is exported under the device \_SB_.PCI0.XHCI.RHUB.HS09. Ensured that the kernel btusb driver is able to find the exported GPIO in the devices with CNVi BT module. Change-Id: I302bc87b18a1aaad77bfb73d607ba28b89b79c14 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/31387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-15mb/google/sarien: Set ELAN as the default for touch panelChris Zhou
According to request of comment 35, setting ELAN as the default. BUG=b:122019253 BRANCH=master TEST=Verify touchscreen on sarien works with this change. Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Change-Id: Iee5e7a21545ca798c0c22f86906acc8e7d81e945 Reviewed-on: https://review.coreboot.org/c/31430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-02-15mb/google/sarien/variants/sarien: Enable Elan touchscreenChris Zhou
Eanble Elan touch for sarien EVT build BUG=b:119763054 BRANCH=master TEST=Verify touchscreen on sarien works with this change. Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Change-Id: I790436338705fc9d68f714245e9b9bb518ddb30a Reviewed-on: https://review.coreboot.org/c/31413 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-13mb/google/hatch: Bump up the BIOS region to 28MiBFurquan Shaikh
This change bumps up the BIOS region to 28MiB to use the hole between SI_ALL and SI_BIOS. Since this SPI flash part is 32MiB, only the top 16MiB actually gets memory mapped. Thus, the change ensures that only RW_LEGACY lies in the 12MiB that is not memory mapped. BUG=b:123443737 TEST=Verified that hatch still boots up. Ensured that fmap dump looks correct. Change-Id: I5832d2b89c7eedfc270755e2add16131cfbddff4 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/31376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2019-02-13mb/google/poppy/var/rammus: Enable mode change wake source for S3/S0ixFurquan Shaikh
This change enables mode change as a wake source for S3 and S0ix. Change-Id: I2e7f9997776b1e024ea417eb69e6c2ffa8c62580 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/31296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-02-13mb/google/sarien: Support multiple touchscreen at same addressDuncan Laurie
The Sarien board may have different touchscreen devices that use the same I2C slave address but have different requirements such as needing a special driver or ACPI configuration. In order to support this the devicetree may be configured with multiple devices at the same address and at boot time the unused devices will be disabled. Because there is no GPIO for selecting the device that is present it can instead be selected with Kconfig, or by setting a VPD key to the HID of the touchscreen device that is present. The default for Sarien devices is to not enable a touchscreen for the OS. The touchscreen selection is currently limited to the Sarien variant but this also adds the touchscreen HID for Arcada to Kconfig so it would not complain about the key not being set. BUG=b:122019253 TEST=This was tested on a Sarien board by adding a second entry to the devicetree at the same address. Without this change the SSDT is not loaded by the kernel because of the address conflict. After this change no touchscreen is enabled by default, but one can be selected with Kconfig or by setting the 'touchscreen_hid' VPD key. Change-Id: I4da12b1de0c551bcd89325fe0d8c66c6ffeb7afc Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/31295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-13mb/google/sarien/variants/sarien: Add GPIO H3 for DVT1John Su
Follow Northbay and intermal project to add GPIO H3(CNVI_EN#) for DVT1. BUG=b:123461432 TEST=Built and tested on sarien system Change-Id: I580a6e094d84a7bada534b14c2b65ecf4b9942b0 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/31360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-02-13mb/google/sarien/variants/sarien: Add GPIO H15 for DVT1John Su
Follow b:123342945 to add GPIO H15(BT_RADIO_DIS#) for DVT1. BUG=b:123342945 TEST=Built and tested on sarien system Change-Id: I0caf97f6a2a8abf2914667350c76300733ead1b8 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/31330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-02-13coreboot: check Cr50 PM mode on normal bootKeith Short
Under some scenarios the key ladder on the Cr50 can get disabled. If this state is detected, trigger a reboot of the Cr50 to restore full TPM functionality. BUG=b:121463033 BRANCH=none TEST=Built coreboot on sarien and grunt platforms. TEST=Ran 'gsctool -a -m disable' and reboot. Verified coreboot sends VENDOR_CC_IMMEDIATE_RESET command to Cr50 and that the Cr50 resets and then the platform boots normally. TEST=Performed Cr50 rollback to 0.0.22 which does not support the VENDOR_CC_TPM_MODE command, confirmed that platform boots normally and the coreboot log captures the unsupported command. Tested-by: Keith Short <keithshort@chromium.org> Change-Id: I70e012efaf1079d43890e909bc6b5015bef6835a Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://review.coreboot.org/c/31260 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-02-13mb/google/hatch: Configure GPIO pad for non-inversionAamir Bohra
This implementation configures GPIO (GPP_A21, GPP_C21, GPP_D16) pad in non-inversion mode i.e Rx PAD state is not inverted as it is sent from GPIO to IOAPIC. BUG=b:123315212 TEST=Tested for below: -> Verify touchpad is working fine. -> TPM init is successful and boot with fixed boot media. Change-Id: I6034fd07ccc96a19218d57ef8bb9049c4b963ea5 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/31328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-13soc/intel/cannonlake: Don't use CAR_GLOBALArthur Heymans
All platforms using this code have NO_CAR_GLOBAL_MIGRATION. Change-Id: I72effa93e36156ad35b3e45db449d8d0d0cabf06 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-02-12mb/google/octopus/casta: Tune usb2eye settingSeunghwan Kim
It needs to tune usb2eye setting for these ports: USB2[4] - type-c port USB2[6] - camera BUG=b:122878632 BRANCH=octopus TEST=built and passed usb2eye SI test Change-Id: Iaa3adaab2f391e95730b141dc0237ca62c459e5a Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/31359 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-12google/kahlee: Remove unneeded HAVE_ACPI_RESUME guardKyösti Mälkki
We leave it to linker garbage collection to drop unreferenced code and symbols from final object files. Function declarations and definitions are to be guarded with preprocessor directives only as a last resort. Change-Id: Ie8748ccddc8e31569c58deba5d08c98a04326fa8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-02-11mb/google/kahlee: Use GPIO_10 for EC_SYNC_IRQEdward Hill
Use AGPIO 10 as the EC sync interrupt for MKBP events for sensor data. On this platform, interrupts are routed via the GPIO controller so need to be registered using GpioInt instead of Interrupt. BUG=b:123750725 BRANCH=grunt TEST=MKBP events still received (with matching EC and kernel changes) Change-Id: If499d24511bbaa7054207b7e0b98445723332c4f Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://review.coreboot.org/c/31278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Enrico Granata <egranata@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-02-08mb/google/hatch: Replace part-specific SPD files with generic onesShelley Chen
Traditionally, we have always allocated 1 DRAM ID per part number. However, on nami, we have run out of DRAM IDs because we have supported so many different parts. We are now adopting the use of generic SPD files that are feature-based rather than specific to each part, allowing us to support multiple parts with a single SPD. The common SPDs were created by taking current SPDs in Nami (which is using the same DDR4 parts as Hatch) and zeroing out all the manufacturer information and part names. Additionally, we zeroed out bytes 128 (raw card extension, module nominal height), 129 (module maximum thickness), and 130 (reference raw card used) after verifying that they are not used in FSP. We verified with these fields zeroed out, all nami devices could boot up without errors. We also verified on the two Hatch skus that we have (4G 2400, 8G 2666) that the generic SPDs boot properly. BUG=b:122959294 BRANCH=None TEST=Make sure that we can boot up on both 4G Samsung and 8G Hynix DDR4 devices that we currently have. Change-Id: I14d9e6b13975b6a65b506e6cd475160711b8f6d4 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/31261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-08drivers/gpio_keys: Remove redundant is_wakeup_source flagKarthikeyan Ramasubramanian
"is_wakeup_source" flag is used to indicate if the concerned device can trigger a wakeup. This flag is redundant with the "wake" GPE event definition. So remove the redundant flag and use the "wake" GPE event to mark the wakeup source. BUG=None BRANCH=None TEST=Boot to ChromeOS. Ensure that the device is marked as wakeup-source in SSDT if wake GPE is configured. Ensure that the system can suspend and the device acts as a wakeup source Change-Id: I99237323639df1cb72e3a81bcfed869900a2eefa Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/31258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-08mb/*/*/romstage: curly braces after the function definitionPeter Lemenkov
See Documentation/coding_style.md, specifically "Placing Braces and Spaces" section. Change-Id: Ia6a2f3d3547c16500996260b0ece9ec693f00113 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/31268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-02-07src: Remove unused include device/pnp_def.hElyes HAOUAS
Change-Id: Ibb7ce42588510dc5ffb04c950c4c8c64e9a2fa37 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-02-07mb/google/{hatch,sarien}: Configure GPIOs using cnl_configure_padsFurquan Shaikh
This change uses cnl_configure_pads to configure GPIOs in ramstage so that cannonlake SoC code can re-configure the GPIOs after FSP-S is run. This is just adding a workaround until FSP-S is fixed. BUG=b:123721147 BRANCH=None TEST=Verified that there are no TPM IRQ timeouts in boot log on hatch. Change-Id: I9973c6c49154f1225f0ac34a3240a0d19f911f18 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/31251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-02-07soc/intel/cannonlake: Add Whiskeylake SoC kconfigSubrata Banik
This patch performs below tasks 1. Create SOC_INTEL_COMMON_CANNONLAKE_BASE kconfig. 2. Allow required SoC to select this kconfig to extend CANNONLAKE SoC support and add incremental changes. 3. Select correct SoC support for hatch, sarien, cflrvps and whlrvp. * Hatch is WHL SoC based board * Sarien is WHL SoC based board * CFLRVP U/8/11 are CFL SoC based board * WHLRVP is based on WHL SoC 4. Add correct FSP blobs path for WHL SoC based designs. Change-Id: I66b63361841f5a16615ddce4225c4f6182eabdb3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/31133 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-06mb/google/hatch: Configure I2C busesFurquan Shaikh
This change enables I2C bus 2, 3 and 4 in devicetree and configures GPIO pads for the same. It also configures pads for I2C5 as no-connect. BUG=b:123711244 TEST=Verified that i2c shows up in "i2cdetect -l" after booting to OS. Change-Id: Ib4714a670d73228332115415e4393f82802c6475 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/31237 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-06mb/google/reef: Expand the coreboot RO sectionMathew King
Current coreboot size is not adequate for adding new features. Note for cros: This change is for merge to ToT only and should not be cherry-picked into reef's firmware branch. BUG=chromium:903833 TEST=emerge-reef coreboot Change-Id: Ie7a25c4638c474e81fb34b57de0dfc1bf393ea67 Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/31230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-05mb/google/sarien: Set system type for the board variantsDuncan Laurie
Select the appropriate system type for the different variants of the Sarien board. This will allow the Arcada variant to use the tablet mode feature of the Intel Virtual Button driver. Change-Id: I8a829aab012256ec196c8ec0fa298fd2bc77f2e1 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/31207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-05mb/google/hatch: Add keyboard backlight supportIvy Jian
This change adds keyboard backlight feature for Hatch platform. BUG=b:122799544 BRANCH=none TEST=keyboard backlight works when EC reports correct info. Change-Id: I29273122f061e0e442f6629351ef3670535c0507 Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/31175 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-05mb/google/poppy/variants/atlas: config GPP_D1 as no-connectCaveh Jalali
This reconfigures the GPP_D1 GPIO pin as a no-connect. It really doesn't go anywhere today or on previous revs of the board. BUG=b:110614620 BRANCH=none TEST=atlas still boots Change-Id: Iea53cf909f8f060c4e0f14e8b4ad579b838b7caa Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/31210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-05Revert "mb/google/poppy/variant/atlas: I2C: run trackpad at 1MHz"Caveh Jalali
This reverts commit 7696290004b6490c7ef8027d7ddf67b163e7dad8. We're seeing trackpad problems on some units with the I2C bus running at 1MHz but not at 400KHz. So, revert back to 400KHz until we understand how to make 1MHz operation more robust. BUG=b:123650686 Change-Id: Ifb06afece9eee0c153240d35e6c3001f5b74f310 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/31212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-05mb/google/kukui: Add default HWID for Chrome OSHung-Te Lin
The default value for Chrome OS HWID should be different. Calculated as HWID v1. BUG=b:123336677 BRANCH=kukui TEST=build and boots properly. Change-Id: I39c640562c1c3b117292b8abacd36a4a9c2fa6c6 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/31088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: You-Cheng Syu <youcheng@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-02-05mb/google/octopus: Add USB ACPI configuration for CNVi BT moduleKarthikeyan Ramasubramanian
This change enables exporting the reset GPIO for CNVi Bluetooth module to the kernel for use in an rf-kill operation. BUG=b:123296264 BRANCH=octopus TEST=Boots to ChromeOS. Checked the SSDT table to ensure that the reset gpio is exported under the device \_SB_.PCI0.XHCI.RHUB.HS09. Ensured that the kernel btusb driver is able to find the exported GPIO in the devices with CNVi BT module. Change-Id: I10f28bfe705da5104d709ae2ed91a8ae003fa639 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/31183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-05mb/google/hatch: Add USB port capability ACPI support for USB2 port10Aamir Bohra
This implementation adds support to create ACPI package for USB port capability (_UPC) and physical location of device (_PLD) for USB2 port 10. BUG:b:123375275 TEST:Verify _UPC and _PLD ACPI packages gets published for USB2 Port 10 in SSDT and BT is functional in discrete and integrated mode. Change-Id: Ifeab24505a700e8e4677be20074c7d0400769cec Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/31197 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-04soc/intel/cannonlake: Remove SOC_INTEL_CANNONLAKE_MEMCFG_INIT KconfigSubrata Banik
This patch removes duplicate selects of same SOC_INTEL_CANNONLAKE_MEMCFG_INIT from various CFL/WHL SoC based boards to include cnl_memcfg_init.c file and include the cnl_memcfg_init.c file by default in CNL SoC Makefile.inc. Change-Id: Ib21ea305871dc859e7db0720c18a9479100346c3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/31134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-01mb/google/hatch: Enable S0ixShelley Chen
BUG=b:123540469 BRANCH=None TEST=None Change-Id: I713e6ad70efdd152895afa45aee44a5b53a8136b Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/31157 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-31mb/google/sarien: Turn on ASPM L1.2 for Card ReaderLijian Zhao
Enable ASPM L1.2 support for embedded realtek card reader, after change the power consumption for SD controller from 5mW to less than 2mW. BUG=N/A TEST=Build and boot up on Arcada platform, check the PCI configuration on pcie root port offset 0x208 is 0x0f, and offset 0x168 on card reader is also 0x0f. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I08d85ee332ceee8ed85cd816bc3e6c895528fdb0 Reviewed-on: https://review.coreboot.org/c/31145 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-31mb/google/octopus: Add Bluetooth USB ACPI configurationKarthikeyan Ramasubramanian
Enable USB ACPI driver for octopus boards and add bluetooth USB ACPI configuration in devicetree. This change enables exporting the bluetooth reset GPIO to the kernel for use in an rf-kill operation. BUG=b:123296264 BRANCH=octopus TEST=Boots to ChromeOS Change-Id: Ie40f1ad70f21a6fd398ce23d060e0c588ba6ce41 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/31130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-01-31google/kukui: Set GPIO_RESET to output modeTristan Shieh
In payloads, we didn't set GPIO modes. We have to set up GPIO mode in coreboot for payloads. BUG=b:80501386 BRANCH=none TEST=HW reboot works in depthcharge Change-Id: Ibd2c6c071871edc59497fbb245cdbec6a814f621 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/c/31148 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-30mainboard/{google,intel}: Remove SaGv hard codingRonak Kanabar
Remove hard coding for SaGv config in devicetree.cb and apply macro for SaGv config for CNL variants boards Change-Id: If007589d5c1368602928b1550ec8788e65f70c05 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/31120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-01-30mb/google/sarien/variants/arcada: Adjust TP/TS/H1 I2C CLK to meet specCasper Chang
After adjustment on Arcada EVT TouchScreen: 390 KHz TouchPad: 389 KHz H1: 389 KHz BUG=b:120584026, b:120584561 BRANCH=master TEST=emerge-sarien coreboot chromeos-bootimage measure by scope Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: Ia6eb332e7a664b211a5025ad07e0d01bf7f8d5bb Reviewed-on: https://review.coreboot.org/c/31124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-01-30mb/google/octopus/casta: Correct unused GPIO pad configurationSeunghwan Kim
Real unused GPIO pad is GPIO_123, but GPIO_122 is configured as unused pad. This patch corrects the configuration. BUG=NONE BRANCH=octopus TEST=emerge-octopus coreboot Change-Id: I4473bd66a4162f5aee3b998aacba906824728fc8 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/31135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2019-01-30mb/google/hatch: Enable AP Wake from ECShelley Chen
Initialize EC_PCH_WAKE_ODL GPIO to make sure that ec events will wake the AP from suspend. Also create a task to initialize the hostevent wake mask properly. BUG=b:123325238,b:123325720 BRANCH=None TEST=from AP console: powerd_dbus_suspend from EC console: hostevent (make sure wake mask set) from EC console: gpioset PCH_WAKE_L 0 Make sure device wakes up Also, checked to make sure keyboard press wakes up device from S3. Change-Id: I53d5291a6b9ab9a21e89ccd21f172180ce473bd5 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/31100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-29mb/google/octopus/var/phaser: Hook up Raydium touchscreenHao He
List Raydium touchscreen in the devicetree so that the correct ACPI device are created. BUG=b:121105424 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage reflash the coreboot to DUT, make sure the Raydium touchscreen can work. Change-Id: I9ffb2a858f31a8b003086806de07f4079870cddf Signed-off-by: Hao He <hao.he@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/31116 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-29google/kukui: Move some initialization from bootblock to verstageYou-Cheng Syu
MT8183 only allows booting from eMMC, so we have to do eMMC emulation from an external source, for example EC, which makes the size of bootblock very important. This CL moves some initialization steps from bootblock to verstage. This will save us about 2700 bytes (before compression) / 1024 bytes (after LZ4 compression) in bootblock. In case of CONFIG_VBOOT is disabled, these initialization steps will be done in romstage. BRANCH=none BUG=b:120588396 TEST=manually boot into kernel Change-Id: I9968d88c54283ef334d1ab975086d4adb3363bd6 Signed-off-by: You-Cheng Syu <youcheng@google.com> Reviewed-on: https://review.coreboot.org/c/30331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-29google/kukui: Implement HW reset functionTristan Shieh
Asserting GPIO PERIPHERAL_EN8 will send a signal to EC to trigger a HW reset for SoC and H1. BUG=b:80501386 BRANCH=none TEST=emerge-kukui coreboot; manually verified the do_board_reset() on Kukui P1 Change-Id: I9afad84af2031a766bc08fc76c8b5f55588c453a Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/c/31118 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-29mediatek: Separate WDT reset function from WDT driverTristan Shieh
Separate WDT reset function from WDT driver, then we can use the common WDT driver and have a board-specific reset function on different boards. In Kukui, we plan to use GPIO HW reset, instead of WDT reset. Add config "MISSING_BOARD_RESET" in Kukui to pass the build for now. BUG=b:80501386 BRANCH=none TEST=emerge-elm coreboot; emerge-kukui coreboot; Change-Id: Ica07fe3a027cd7e9eb6d10202c3ef3ed7bea00c2 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/c/31121 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-28mb/google/octopus: Fix termination for unused dual voltage pinsShamile Khan
These pins should not have pull downs configured in standby state as that can cause contention on the termination circuitry and lead to incorrect behavior as per Doc# 572688 Gemini Lake Processor GPIOTermination Configuration. BUG=b:79982669 TEST=Checked that code compiles with changes. Change-Id: If3cadc000ec6fc56019ee3f57e556dc819d5e0a5 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/c/30823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-16 13:54:10 +0000