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2020-08-12mb/google/volteer/halvor: Update settings for WiFi/BT functionsFrank Wu
Configure gpio/overridetree settings for WiFi/BT functions. Then WiFi/BT functions are enabled on Halvor. BUG=b:153680359, b:163004808 TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage Verify that WiFi/BT can scan devices successfully. Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I085b192bb768c2c1238f3f857d315502ac10857e Reviewed-on: https://review.coreboot.org/c/coreboot/+/44372 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-12mb/google/zork: expose stop gpio for trembyleAaron Durbin
In CB:43701 the trembyle touchscreen parameters were not updated to expose the stop gpio properly. BUG=b:162973325 Change-Id: I6f5da1c556ba1c6ccabf699491d3b635aa79f7c0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-12mb/google/dedede/variants/drawcia: add DTT supportSumeet R Pawnikar
Add DTT (Dynamic Tuning Technology) support on Jasper Lake based drawcia system. Add information on sensors, power limits and tcc_offset for DTT based thermal control. BRANCH=None BUG=b:161993459 TEST=Built for dedede system Change-Id: If50052864fb246a6a8f7d96fa50529e5f55968c0 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-08-12volteer: Create lindar variantJulia Tsai
Create the lindar variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.1.2). BUG=b:161089195 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_LINDAR Signed-off-by: Julia Tsai <julia.tsai@lcfc.corp-partner.google.com> Change-Id: I08923cde932b7304bcb01cd747530c87949e4692 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-12mb/google/zork: Reorganize chromeos.fmd to increase WP_RO to 8MiBFurquan Shaikh
This change reorganizes flash map layout for zork to allow WP_RO to grow to 8MiB. This is to allow more space for the firmware UI screens in RO. Following changes are made in the layout: 1. MRC_CACHE_HOLE is dropped since only one slot of 64K is used for MRC cache. Next section can start on 64K boundary immediately after MRC cache. 2. RW_SECTION_A and RW_SECTION_B are dropped down in size to 3MiB each. Each region is currently at ~2MiB of usage. 3. RW_ELOG is restrictred to 4KiB as that is the maximum elog size supported by coreboot. 4. SMMSTORE is restricted to 4K. 5. RW_LEGACY region is dropped down to ~1.9MiB. BUG=b:161949925 TEST=Verified that write-protection for RO still works fine, device boots in recovery and non-recovery mode. Also, verified that the dump of fmap looks correct: dump_fmap -h firmware/image-trembyle.serial.bin name start end size WP_RO 00800000 01000000 00800000 RO_SECTION 00804000 01000000 007fc000 COREBOOT 00875000 01000000 0078b000 GBB 00805000 00875000 00070000 RO_FRID 00804800 00804840 00000040 FMAP 00804000 00804800 00000800 RO_VPD 00800000 00804000 00004000 RW_LEGACY 0061d000 00800000 001e3000 SMMSTORE 0061c000 0061d000 00001000 RW_NVRAM 00617000 0061c000 00005000 RW_VPD 00615000 00617000 00002000 RW_SHARED 00611000 00615000 00004000 VBLOCK_DEV 00613000 00615000 00002000 SHARED_DATA 00611000 00613000 00002000 RW_ELOG 00610000 00611000 00001000 RW_SECTION_B 00310000 00610000 00300000 RW_FWID_B 0060ff00 00610000 00000100 FW_MAIN_B 00312000 0060ff00 002fdf00 VBLOCK_B 00310000 00312000 00002000 RW_SECTION_A 00010000 00310000 00300000 RW_FWID_A 0030ff00 00310000 00000100 FW_MAIN_A 00012000 0030ff00 002fdf00 VBLOCK_A 00010000 00012000 00002000 RW_MRC_CACHE 00000000 00010000 00010000 SI_BIOS 00000000 01000000 01000000 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I882f3d813c08ba5fb0ad071da4f79e723296f4b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Joel Kitching <kitching@google.com>
2020-08-12mb/google/kukui: revise per-device memory mapping tableHung-Te Lin
In order to help identifying right DRAM info (especially in user space), we want to unify the mapping table and do the device-specific mapping by a virtual offset based on build config. BUG=b:161768221,b:159301679 BRANCH=kukui TEST=emerge-jacuzzi coreboot Change-Id: If89bf18c48d263deb79df3e7a60c33bec000d8a3 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-08-11mb/google/zork: config ddi for dirinbozKevin Chiu
dirinboz does not support native HDMI, config DDI as below: DDI0: eDP DDI1: DP DDI2: DP BUG=b:161579679 BRANCH=master TEST=1. emerge-zork coreboot chromeos-bootimage 2. power on proto board successfully Change-Id: I9dffdf5654680e3c2c0b259ee82a471f8ff14f56 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-11mb/google/zork: fix incorrect DRAM SPD table load for dirinbozKevin Chiu
BUG=b:161579679 BRANCH=master TEST=1. emerge-zork coreboot chromeos-bootimage 2. power on proto board successfully Change-Id: Ia736b0f25824eebe4ef25a11646f82963611e3b3 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-11mb/google/zork: move USB OC pin mapping to trembyle base boardFelix Held
The USB OC pin mapping is similar enough to move it to the base board and just have two overrides for trembyle, which is based on an older version of the schematics, and one override for woomax, which doesn't use one USB port. BUG=b:163081097 Change-Id: I7e305d7e6f51d7ef7a4c699e3bacc6bcd699d2f2 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-08-10mb/google/volteer: Pull up GPP_D16 instead of driving itCaveh Jalali
The latest realtek RTS5261 SD daughterboard exposes the PRSNT# pin to GPP_D16 but there is a RTS5261 requirement to pull up this pin and not drive it at power on. We can meet this requirement without breaking other boards by changing GPP_D16 to be a no-connect with an internal pull up. Other boards use this signal as an enable input, so changing this to pull up is OK. BUG=b:162722965 TEST=Verified RTS5261 and GL9755 daughterboards enumerate on PCI and can read SD cards. Change-Id: I096d76ec12b7c3afaf02e621fd301b6704913d5d Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-10mb/google/volteer/var/terrador: Update gpio settings for Proto2David Wu
Based on latest schematic and gpio table of terrador, update gpio settings for terrador Proto2. BUG=b:151978872 TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I64b4fcbaabc487206d14d794af319e6df6f99581 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-08-08mb/google/zork/trembyle: comment why USB OC pin mapping is differentFelix Held
Change-Id: I68b7529733e604ac45919a54e094be7eeb044458 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-08soc/intel/skylake: Enable CIO depending on devicetree configurationFelix Singer
Currently, CIO gets enabled by the option Cio2Enable, but this duplicates the devicetree on/off options. Therefore, depend on the devicetree for the enablement of the CIO controller. All corresponding mainboards were checked if the devicetree configuration matches the Cio2Enable setting, and missing entries were added. Change-Id: I65e2cceb65add66e3cb3de7071b1a3cc967ab291 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44032 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-08soc/intel/skylake: Enable SA IMGU depending on devicetree configurationFelix Singer
Currently, SA IMGU gets enabled by the option SaImguEnable, but this duplicates the devicetree on/off options. Therefore, depend on the devicetree for the enablement of the SA IMGU controller. All corresponding mainboards were checked if the devicetree configuration matches the SaImguEnable setting, and missing entries were added. Change-Id: I293a20a321c75f82a57cbd5339656d93509b7aa6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-08-08soc/intel/skylake: Enable SDXC depending on devicetree configurationFelix Singer
Currently, SDXC gets enabled by the option ScsSdCardEnabled, but this duplicates the devicetree on/off options. Therefore, depend on the devicetree for the enablement of the SDXC controller. All corresponding mainboards were checked if the devicetree configuration matches the ScsSdCardEnabled setting, and missing entries were added. Change-Id: I298b7d0b0fe2a7346dbadcea4be22dc67fce4de8 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44028 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-08-07mb/google/zork: Revert Don't expose reset GPIO for touchscreen to OSMartin Roth
This reverts the code from commit 728c0787f2 that removes the reset GPIO from the touchscreen ACPI interface. That patch exposes a bug which leads to an invalid opcode trap in the touchscreen code. Reverting this gets the system working again, but is not a long-term solution. BUG=b:162596241 TEST=System boots to login screen. Change-Id: I57a070d94f961cec43834c8bedd5dafc8a54171a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43078 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-07soc/intel/skylake: Enable thermal subsystem depending on devicetreeFelix Singer
Currently SA thermal subsystem gets enabled by the option Device4Enable, but this duplicates the devicetree on/off options. Therefore depend on the devicetree for enablement of the SA thermal subsystem controller. All corresponding mainboards were checked if the devicetree configuration matches the Device4Enable setting, and missing entries were added. Change-Id: I7553716d52743c3e8d82891b2de14c52c6d8ef16 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44026 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-07soc/intel/cnl: Set Heci1Disable depending on devicetree configFelix Singer
Currently HECI1 gets enabled by the option HeciEnabled, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement/disablement of the HECI1 device. All corresponding mainboards were checked if the devicetree matches the HeciEnabled setting, and adjusted where necessary. Change-Id: I03dd3577fbe3f68b0abc2d196d016a4d26d88ce5 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-08-07mb/google/volteer: support variant defined spd pathsNick Vaccaro
Allow variants to override the SPD_SOURCE_PATH to allow supporting different types of DDR. BUG=b:163065661 TEST="emerge-volteer coreboot" and verify all variants build. Change-Id: Id52e651848548a783d6d9f57e88f6099425b063e Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-08-07Revert "mb/google/volteer/var/halvor: Update dq/dqs mappings"Paul Fagerburg
This reverts commit 3d813cbede650a89a519d5896652328e4ecf88c6. Reason for revert: the CL made the build unstable. Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Change-Id: I9d067eb13196ff7d537d557d8ff864b1572a3b04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43076 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-07mb/google/dedede/var/magolor: Select 16 MB SPI ROMRen Kuo
Decrease the SPI ROM size from 32 MB to 16 MB BUG=b:58540772 BRANCH=None TEST= build firmware and check the magolor bin size Change-Id: Ie7ddf698fde1dbf663859d5654946bc08abe737c Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-08-06mb/google/volteer/var/halvor: Update dq/dqs mappingsAmanda Huang
Update dq/dqs mappings based on halvor schematics. BUG=b:162892573 BRANCH=none TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage Change-Id: I98f79283aa18f6fd41114fb6b60cac1cbed69de7 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43988 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-06mb/google/zork: Configure GPIO_89 as PAD_NCFurquan Shaikh
GPIO_89 was marked as EN_DEV_BEEP_L in pre-v3.6 schematics, but it was never really used on any of the zork variants. Starting with v3.6, GPIO_89 is left unused in schematics. This change configures GPIO_89 as PAD_NC in baseboard GPIO table. Since EN_DEV_BEEP_L still needs to be driven high to allow speakers to work, GPIO_89 is configured as PAD_GPO driven high on pre-v3.6 schematics. BUG=b:62108046 Change-Id: I026cd6cb598667ce6e115c3ec9357a6a56051d39 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44190 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-06mb/google/zork: Add touchscreen power controlFurquan Shaikh
This change adds support for touchscreen power control using: * GPIO_90 for trembyle based boards * GPIO_32 for dalboz based boards By default, baseboard tables configure these GPIOs as PAD_GPO driven low and override trees expose these pads as enable_gpio to be used by ACPI power resource. In order to support pre-v3.6 boards, override tables configure these pads as PAD_NC and drop the enable_gpio setting from device tree based on board version. BUG=b:161935640, b:162747210 Change-Id: Iba5e36b65b44ea11613b4d5fc8f13ce6433f83ab Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44193 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-06mb/google/zork: Switch USI_RESET to active low polarity for v3.6+Furquan Shaikh
v3.6 of reference schematics have switched the polarity of reset signal to touchscreen controller from active high to active low. This change updates the default configuration in baseboard gpio tables to set the reset GPIO to output low and override tables in variants to set the reset GPIO to output high. Additionally, devicetree by default exposes ACTIVE_LOW configuration for reset GPIO. In order to support pre-v3.6 boards, reset GPIO is updated to ACTIVE_HIGH based on board version. BUG=b:161937506 Change-Id: I092f274d8eb1920a1cd6d3eccbe8f26b0b28928a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-06mb/google/zork: Use dev_nested_path for dmic gpio updateJosie Nordrum
Create function update_dmic_gpio to update DMIC GPIO for ACP machine and use find_dev_nested_path function for consistency. BUG=None BRANCH=None TEST=None Change-Id: I96cf207f24c6117d98ff2bf7e6e5cd282489e805 Signed-off-by: Josie Nordrum <josienordrum@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44158 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-06mb/google/zork: Make SW changes for HP_INT_ODL in schematic v3.6Josie Nordrum
HP_INT_ODL is no longer connected to CODEC_GPI in schematic version 3.6. Split variant_audio_update into update_dmic_gpio and update_hp_int_odl. Changed GPIO_29 from PAD_NC to PAD_GPI in Trembyle. Changed GPIO_84 from PAD_NC to PAD_GPI for Dalboz. Changed HP_INT_ODL to appropriate pin in both boards devicetree.cb. BUG=b:161938476 BRANCH=None TEST=None Cq-Depend: chromium:2335424 Change-Id: I05ffb063ab99823d07be6eaa911efbde3cc4ff55 Signed-off-by: Josie Nordrum <josienordrum@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44157 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-06mb/google/zork: Add kconfigs to check schematic version 3.6Josie Nordrum
Added VARIANT_SUPPORTS_PRE_V3_6_SCHEMATICS and VARIANT_MIN_BOARD_ID_V3_6_SCHEMATICS. Added helper functions to check if variant uses v3.6 and if variant uses CODEC GPI. BUG=b:161938476 BRANCH=None TEST=None Change-Id: If86e1ea3c02db354c7b410f1bbc1daacb483cc51 Signed-off-by: Josie Nordrum <josienordrum@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44156 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-06mb/google/volteer: add support for ddr4 memoryNick Vaccaro
Add new ddr_memory_cfg structure to support both DDR4 and LPDDR4x memory types. Change existing variant code to use the new meminit_ddr() call instead of calling meminit_lpddr4x() directly. BUG=b:161772961 TEST='emerge-volteer coreboot chromeos-bootimage' and verify that volteer still boots. NOTE that this only tests the lpddr4 side of the implementation as I do not have a DDR4 board to test this on. Change-Id: Id4bca2bfa97530f0d04a0e8d90f01b8281d2aea6 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-08-06mainboard/google/puff: Remove second temp sensorAndrew McRae
Newer boards have removed the second temperature sensor and relocated the remaining sensor. BUG=b:162909373 TEST=Confirm on hardware. Change-Id: Ie41a57598b0c87a6632f4c55c0f60a94a89cae43 Signed-off-by: Andrew McRae <amcrae@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-06mb/google/kukui: Add ddr geometry to support 6GB, 8GB DDR bootupHuayang Duan
Set correct DDR geometry for all existing memory modules. BUG=none BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: I9b53ab2bf43e0dfb7448eb37a18faf686267eaed Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-08-06mb/google/kukui: Add a new config 'Fennel'xiatao5
A new board introduced to Kukui family. BUG=b:162478693 TEST=make # select Fennel BRANCH=kukui Signed-off-by: xiatao5 <xiatao5@huaqin.corp-partner.google.com> Change-Id: I1f742a36793f38c37fbd4e1b4cbddbd542e785ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/44061 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Zhaoyou Hong <hongzhaoyou@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-05mb/google/volteer/var/voxel: Add Raydium touchscreen supportDavid Wu
Update gpio GPP_E7 and enable the Raydium TS support BUG=b:157402209,b:162632701,b:162636271 BRANCH=master TEST= 1. emerge-volteer coreboot chromeos-bootimage 2. boot up on voxel DUT and make sure the raydium TS can work. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I377aded4982ece71f4dabb58f307f68c713edcd2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
2020-08-05mb/google/vilboz: update telemetry settings for vilbozPeichao Wang
update telemetry value for SDLE test result. BUG=b:160698427 BRANCH=None TEST=emerge-zork coreboot Change-Id: Icce57f9be2732ff79f336daa6c447a30247366cf Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-05mb/google/zork/ezkinil: Fix ELAN touchscreen ACPI nodeLucas Chen
a. USI_REPORT_EN is no longer set to high in coreboot. Instead GPIO_144 is exposed as stop_gpio in ACPI to allow OS to control this pad as required. b. Add Delay after stop_gpio Low - 300ms BUG=b:162263398 Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Change-Id: I3d4dcb6e5cae5d9515abfd415315ec4114ca80b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44107 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-05src: Use space after 'if', 'for'Elyes HAOUAS
Change-Id: I5d3a5ede47aefc7cc2ee330f8a0bcded16138764 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44173 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-05baytrail mainboards: Clean up mainboard.cArthur Heymans
This cleans up some unneeded no-ops in the mainboard.c files of baytrail boards. Change-Id: I7662f6e860d672a99b211488122bec073cc78acf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Máté Kukri <kukri.mate@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-05mb/google/zork: update DRAM SPD table for dirinbozKevin Chiu
DRAM support list 0x00 HYNIX HMA851S6CJR6N-VK 0x01 HYNIX H5ANAG6NCMR-VKC 0x02 Samsung K4A8G165WC-BCTD 0x03 Samsung K4AAG165WB-MCTD 0x04 Samsung K4A8G165WC-BCWE 0x05 HYNIX H5AN8G6NDJR-XNC 0x06 HYNIX H5ANAG6NCMR-XNC 0x07 Micron MT40A512M16TB-062E:J 0x08 Micron MT40A1G16KD-062E:E 0x09 Samsung K4AAG165WA-BCTD 0x0A Samsung K4AAG165WA-BCWE BUG=b:161579679 BRANCH=master TEST=build Change-Id: Ib9fa5ae98568d659326d431a4006174a343fa299 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-04mb/google/zork/var/vilboz: Enable support for garaged stylusFurquan Shaikh
This change adds support for pen insert/eject operations in S0 and wake on pen eject from S3 for vilboz. BUG=b:157628650 Change-Id: I7ba0881b67dfb67c032667d591f7d1806a50af22 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-04soc/intel/baytrail: Factor out `acpi_fill_madt()`Angel Pons
It is the same for the two Bay Trail boards in the tree. Change-Id: I5110cfa8807406232e4f7f1fe79dfe9c3ae4dac4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Máté Kukri <kukri.mate@gmail.com>
2020-08-04mb/**/{devicetree,overridetree}.cb: Indent with tabsAngel Pons
Use tabs instead of eight (sometimes less) spaces. Change-Id: Ic3d61f5210d21d9613fc50b47b90af71f544169a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-03mb/google/zork: Pass oscout system clk to rt5682Akshu Agrawal
In kernel clk for AMD SoCs we expose a generic clk by the name oscclk1. This oscclk1 is a fixed 48Mhz frequency clk in RV. In Zork oscout system clock is linked to rt5682 mclk. Setting mclk-name to oscclk1 tells rt5682 driver its mclk is oscclk1. Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> BUG=b:158906189 TEST=rt5682 driver get the correct clk and tested audio playback Change-Id: Ic565e8e0573e085e5759b2d3688cc0a4533b67fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/44010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-03mb/google/dedede: Update CPU critical temperatureSumeet R Pawnikar
Observed thermal shutdown initiated by DPTF due to CPU temperature reaching critical temperature trip value. During stress testing with heavy workload like WebGL Aquarium, sometime CPU temperature spikes till 99 degree Celsius and DPTF initiates system shutdown. This updates CPU critical temperature trip value to 105 degree Celsius to avoid system shutdown. BUG=b:161993459 BRANCH=None TEST=Built and tested on dedede system Change-Id: If15a873a997aa80f20940f27bbafd4498908c091 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44054 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-03mb/google/kukui: Add Micron 8GB discrete LPDDR4X DDR supportHuayang Duan
Support 8GB MT53E2G32D4NQ-046 discrete DDR bootup. BUG=b:159301679 BRANCH=kukui TEST=Boots correctly on Kukui. Change-Id: Ide01f029c5ebd6c3ae6350f73f3c60b818d51353 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-08-03mb/google/dedede/var/madoo: Add discrete WiFi configurationDtrain Hsu
Add RTL8822CE support for Madoo. BUG=b:162390420 BRANCH=None TEST=FW_NAME=madoo emerge-dedede coreboot chromeos-bootimage, build successful Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I6e471be2b2856977e6f728d5a2ca78942725bea6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2020-08-03mb/google/dedede/var/madoo: Support Elan touchpad and configure I2C portsDtrain Hsu
1. Add Elan touchpad support. 2. Follow schematic to disable I2C1 and I2C3. BUG=b:160869188,b:161407664 BRANCH=NONE TEST=emerge-dedede coreboot chromeos-bootimage", build successful Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I154a1ff2597968d200d1d0693718f90cd2744616 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2020-08-03mb/google/dedede/var/madoo: Enable Goodix touchscreenIan Feng
Add Goodix touchscreen support. BUG=b:160868197 BRANCH=None TEST=emerge-dedede coreboot chromeos-bootimage", build successful Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I9bf27d69d0895cb4ea8620a6da49e98d25e05c23 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44012 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-03mb/google/volteer: Change wake to be triggered on a raising edgeAlex Levin
ACPI_GPIO_IRQ_EDGE_BOTH sets both edges as wake. The desired behavior is wake on rising edge, change to ACPI_GPIO_INPUT_ACTIVE_LOW. Fixing for both Volteer and Volteer2 variants. BUG=b:146083964 BRANCH=None TEST=tested on a Volteer Change-Id: I2d3339151bf4e2cbae60aaf97ba1bd7909a2b9a9 Signed-off-by: Alex Levin <levinale@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-08-03mb/google/kukui: indent config names for burnet and escheHung-Te Lin
The 'burnet' and 'esche' in Kconfig.name should have two spaces after the arrow. BUG=None TEST=make menuconfig BRANCH=kukui Change-Id: If7cc31cf459082a797445fb8223b3d9cbde72901 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43986 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-03mb/google/volteer/var/todor: Support ELAN i2c-hid touchpadDavid Wu
Update ELAN i2c-hid touchpad configuration BUG=b:160741785 BRANCH=None TEST=Verify touchpad is working fine. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I2549048766d0707666910bd86c46ac9201bf3905 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43998 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-16 12:21:24 +0000