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2017-08-25google/cyan: Increase RO coreboot size on flashMatt DeVillier
Commit 05627831826cab096789bd19f004b33a4cd70c0e applied this change to other Google boards, but cyan was left out. Bring cyan in line with other Google boards. Change-Id: Id86bea538a7b82367ea6ddbd3fe3efb1b1c0078d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-25google/cyan: Remove support for pre-EVT boardMatt DeVillier
Cleaning up code to remove support for pre-EVT rev of cyan board. Analogous to what was done for intel/strago in commit 103f00d. Change-Id: I29b32da8064e0743cc9c5df02ce7d3441459ee8f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25google/cyan: Use GpioInt for Keyboard IRQJagadish Krishnamoorthy
Cherry-pick from Chromium commit a162348. Remove the hard coded IRQ number for the keyboard interrupt. IRQ number can change based upon the gpio bank index ordering. Hence pass the gpio bank and index number so that kernel calculates the IRQ number. Original-Change-Id: Icfe5c3995007164bf617575b541758c18ee63a1d Original-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I81ff19e3060c533ee76023c7651f741294e9db30 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25google/cyan: Disable L1 sub stateT.H. Lin
Adapted from Chromium commit dc59188. Disable L1 sub state to prevent WiFi randomly disappear condition. Original-Change-Id: I8975bb4bbbc2fc89b91b06ae02716367890c672d Original-Signed-off-by: T.H. Lin <T.H_Lin@quantatw.com> Original-Reviewed-by: Rajat Jain <rajatja@chromium.org> Original-Reviewed-by: Vincent Wang <vwang@chromium.org> Oriignal-Tested-by: TH Lin <t.h_lin@quanta.corp-partner.google.com> Change-Id: I51a1bcca6431e6bc28baf9b09433cec13db925c3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25google/cyan: Add 2nd source memory 2-channel 4G (Micro/Samsung)T.H. Lin
Cherry-pick from Chromium commit 7f0cdf0. Cyan board add 4G DDR3L 2nd source memory (Micro/Samsung) Original-Change-Id: I12f82082d8227e61a97ce0a001d7d2b1f6613e06 Original-Signed-off-by: T.H. Lin <T.H_Lin@quantatw.com> Original-Reviewed-by: Shawn N <shawnn@chromium.org> Change-Id: Ieca7201346414d7a962f9619dbe846c67c0f02d6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25google/cyan: Add 2nd source memory (Micro/Samsung)T.H. Lin
Cherry-pick from Chromium commit 3b578ef. Cyan board use new 2nd source memory (Micro/Samsung) Original-Change-Id: I6f4e8438faede7ac742776a622c265922e498898 Original-Signed-off-by: T.H. Lin <T.H_Lin@quantatw.com> Original-Reviewed-by: Shawn N <shawnn@chromium.org> Change-Id: Ie2febe4de57c00c269def15d57f2b5a6f0f378aa Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25google/cyan: Fix Touchscreen InterruptJagadish Krishnamoorthy
Cherry-pick from Chromium commit 1138727. Elan touchscreen driver expects the first gpio resource in asl to be the reset line. The driver considers the gpio based irq line as reset gpio resource and changes the direction to output. This will cause irq registration to fail. Solution is to pass Interrupt resource for touchscreen irq instead of GpioInt. Original-Change-Id: Ia72d4ad80117f3c0014098113c9027416026e65e Original-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I1c4b029851e321feeedf713186976fbec42dd82e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25google/cyan: Enable CA MirrorShobhit Srivastava
Cherry-pick from Chromium commit e49deb1. Configuring UPD PcdCaMirrorEn. This is a board specific parameter. CA mirror is the Command Address mirroring option that is board specific. Original-Change-Id: I05174e18d650332d838e5036c713e91c4840ee75 Original-Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Change-Id: Ibd0c811d41cb592634f7785edb83ad2f423546c5 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25google/cyan: Disable unused lines on Gpio North BankJagadish Krishnamoorthy
Cherry-pick from Chromium commit 1940eb6. The unused lines leads to spurious interrupts on few of the systems. Original-Change-Id: Ie539e1debc15dd1fd8707f8866c65714fc43e44b Original-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Bernie Thompson <bhthompson@chromium.org> Original-Tested-by: Bernie Thompson <bhthompson@chromium.org> Change-Id: I6f4f7cec8ef11e781c66b6efff4188259469e41c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25google/cyan: Clean-up the devicetreeRavi Sarawadi
Cherry-pick from Chromium 2b51633. Disable unused PCI devices. Update PCI DeviceID. Original-Change-Id: I34fa6e25f9178de959aad30cc979d787cf76b8ad Original-Signed-off-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I7a06a1d44ce933000cbfe2eb71823ee66cb46a34 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25google/cyan: Support reading Memory strap GPIOs to select SPDSubrata Banik
Cherry-pick from Chromium commit 8f63720. SoC GPIO to read Memory strap not getting configured correctly causing incorrect RAMID read during ROMSTAGE TEST=Build and boot the platform with differnt Memory type and read RAMID correctly inside spd.c RAMID = 0 => 4GB Samsung Memory RAMID = 1 => 4GB Hynix Memory RAMID = 2 => 2GB Samsung Memory RAMID = 3 => 2GB Hynix Memory Original-Change-Id: Ide9d4b5f73565cddd74cedf7afe4b7d168dde74c Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: If2ba9ec5be111b9c30360ffde41a2c644a69ecae Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-08-25soc/intel/skylake: Add LPC and SPI lock down config optionSubrata Banik
This patch to provide new config options to perform LPC and SPI lock down either by FSP or coreboot. Remove EISS bit programming as well. TEST=Build and boot Eve and Poppy. Change-Id: If174915b4d0c581f36b54b2b8cd970a93c6454bc Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25mainboard/google/coral: Add USB2 phy setting override for SantaTim Chen
In order to pass type C USB2 eye diagram for sku Santa, USB2 port#1 PHY register needs to be overridden. port#1: PERPORTPETXISET = 7 PERPORTTXISET = 2 BUG=b:64880573 BRANCH=master TEST=emerge-coral coreboot chromeos-bootimage Change-Id: I07c0b7b0f08263a348befb7d6fd8d01028314470 Signed-off-by: Tim Chen <Tim-Chen@quantatw.com> Reviewed-on: https://review.coreboot.org/21199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-24mb/google/coral: Copy devicetree.cb from baseboardTim Chen
It is a copy from baseboard/devicetree.cb (coreboot.org ToT) BUG=b:64880573 BRANCH=master TEST=emerge-coral coreboot chromeos-bootimage Change-Id: I5db730c1974a96547fe7fda63689b7c5bfaefc66 Signed-off-by: Tim Chen <Tim-Chen@quantatw.com> Reviewed-on: https://review.coreboot.org/21130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-23soc/amd/stoneyridge ACPI: Sync sleepstates.asl definitionsKyösti Mälkki
Sync file with southbridge/amd/common/sleepstates.asl. SSFG was meant to be used as a mask to enable sleepstates _S1 thru _S4. However as a logical instead of bitwise 'and' operation was used, all the states were enabled if only one was marked available. Change-Id: I674953f1a5add74e16ddd84c252e8d21501ffefd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-08-22google/kahlee: Enable ALS connected to ECAkshu Agrawal
Kahlee has an ambient light sensor connected to the EC. TEST=Can see the device in /sys/bus/iio BUG=b:62030268 Change-Id: Id1138a0fc5270489a734bdf8b1f4ac02d358c0df Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-on: https://review.coreboot.org/21146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-22mainboard/google/coral: Overwrite family code for coral models.Harry Pan
This patch assigns the code of coral family, such that, the 'mosys platform family' returns 'Google_Coral'. BUG=b:64467244, b:64501879 BRANCH=none TEST=Examine 'mosys platform family' w/ new firmware. Change-Id: I1d8f8ca2166a1d80855608cf5b64b0cc7bf3dc93 Signed-off-by: Harry Pan <harry.pan@intel.com> Reviewed-on: https://review.coreboot.org/21136 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-21google/snappy: Add Raydium touch screen supportKevin Chiu
Current coreboot does not create ACPI device for OS to recognize Raydium touchscreen. List the touch screen in the devicetree so that the correct ACPI device are created. BUG=b:64821783 BRANCH=reef TEST=emerge-snappy coreboot Change-Id: I8852e38f01f82b80c2c9718b93baf5894dbd745b Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/21083 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-08-21google/snappy: Add MELFAS touch screen supportKevin Chiu
Current coreboot does not create ACPI device for OS to recognize MELFAS touchscreen. List the touch screen in the devicetree so that the correct ACPI device are created. BUG=b:64779224 BRANCH=reef TEST=emerge-snappy coreboot Change-Id: If2bc910d641e0cf2b120ed883c5788542959f568 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/21067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-21mainboard/google/poppy: Update VR config settingsFurquan Shaikh
Update Psi2Threshold, IccMax, ACLoadline and DCLoadline VR config settings to match that of soraka. BUG=b:62063434 BRANCH=None TEST=Build and boot poppy. Change-Id: I2c294eb14257d319e1e2d4d1e529481d921ba6f8 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21105 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
2017-08-21mainboard/google/poppy: Remove MPS IMPV8 workaroundFurquan Shaikh
Poppy uses MPS2949 IMVP8 controller and does not need the VR workaround similar to Eve. Change-Id: If6fb1890e024e1488d278bbe0a71a1a63ee321af Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21104 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
2017-08-18include/device: Split i2c.h into threeNico Huber
Split `i2c.h` into three pieces to ease reuse of the generic defi- nitions. No code is changed. * `i2c.h` - keeps the generic definitions * `i2c_simple.h` - holds the current, limited to one controller driver per board, devicetree independent I2C interface * `i2c_bus.h` - will become the devicetree compatible interface for native I2C (e.g. non-SMBus) controllers Change-Id: I382d45c70f9314588663e1284f264f877469c74d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-17mainboard/google/poppy: Add ACPI objects for NVMEM device GT24C16S and CAT24C16V Sowmya
The Giantec semiconductor GT24C16S and ON semiconductor CAT24C16 are the industrial standard electrically erasable programmable read only memory (EEPROM's) and this patch adds ACPI objects and power resources for NVMEM device. Update DOVD method to set sensor IO LDO voltage and remove repetitive code from OVFI, VCMP and NVMP power resources. BUG=b:38326541 BRANCH=none TEST=Build and boot soraka. Dump and verify that the generated DSDT table has the required entries. Read the NVMEM content via sysfs interface. Change-Id: If49ed33b7e1de1eabf317b31ceed8568dfca0aae Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/20495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-08-17mainboard/google/coral: Add keyboard backlight supportSheng-Liang Pan
BUG=b:64705535 BRANCH=master TEST=emerge-coral coreboot chromeos-bootimage and verify the keyboard backlight can be bright and alt+f6, alt+f7 function keys can be used. Change-Id: I777247a6b58d3d50b72f12ca2fcab49a06ed5431 Signed-off-by: Pan Sheng-Liang <Sheng-Liang.Pan@quantatw.com> Reviewed-on: https://review.coreboot.org/21027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-08-15google/coral: Fetch SKU ID from ECPatrick Georgi
BUG=b:64468585 BRANCH=none TEST=with the other sku-id related patches applied, coreboot obtains the right SKU ID from EC Change-Id: I96a0e030bbc5f1c98165e70353340c413f8dc352 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/20947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-15soc/intel/common/block: Add LPC Common code and use it for APLRavi Sarawadi
Add LPC common code to be shared across Intel platforms. Also add LPC library functions to be shared across platforms. Use common LPC code for Apollo Lake soc. Update existing Apollolake mainboard variants {google,intel,siemens} to use new common LPC header file. Change-Id: I6ac2e9c195b9ecda97415890cc615f4efb04a27a Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/20659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-14stoneyridge: Rename hudson to southbridgeMarc Jones
Simplify funciton names and remove reference to hudson in stoneyridge. The southbridge in Stoney Ridge is Kern and hudson naming is no longer accurate. BUG=b:62200157 BRANCH=none TEST=Build and booted on Kahlee. Change-Id: Ide7a72dae69b881997101f1e37a1ac739901744d Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20912 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-11mb/google/poppy: Update PL2 settingsSumeet Pawnikar
Update PL2 override setting to 15W as per KBL Power Arch Guide. Change-Id: I4a6f875f8c3bdb012d6ff97c1429f32db5210893 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/20943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-10google/kahlee: Set eMMC slotMarc Jones
Set AGESA SD/eMMc variable to non-removable eMMc. BUG=b:63891719 BRANCH=none TEST=Boot eMMC on Kahlee. Change-Id: I76ed9cec36a9688ebe75db2077f1ece4ab750c16 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20911 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-09intel/common/block/smm: Update smihandler to handle gpiBrandon Breitenstein
Updating the common smihandler to handler gpi events which originally were going to be left to each soc to handle. After some more analysis the gpi handler can also be commonized. Change-Id: I6273fe846587137938bbcffa3a92736b91982574 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/20917 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-06rockchip: gpio: add gpio_pull argument in gpio_input_irq() functionLin Huang
some gpio irq need to set input pull initialization status to guarantee to get the right irq trigger. let's add this argument in gpio_input_irq() function BRANCH=None BUG=None TEST=boot from bob Change-Id: I9b8e6497f07146dafdb447a6ea10d039a2a2fa33 Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/20866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-08-04mainboard/google/poppy: Decrease link-frequencies for OV13858 and OV5670V Sowmya
Decrease the link-frequencies as recommended by Omnivision for OV13858 and OV5670 camera sensors. BUG=b:38326541 BRANCH=none TEST=Build and boot soraka. Dump and verify that the generated DSDT table has the required entries. Verified that sensor probe is successful. Change-Id: I78fb2d3527f66b5147123a9c8fc4cb95650f86b6 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/20787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
2017-08-04mainboard/google/soraka: Configure GPP_B8 in bootblockFurquan Shaikh
GPP_B8 acts as input to the inverter whose output controls PERST# signal to wifi module. Out of reset, GPP_B8 is configured as input by default. Since there is no external pull-down on it, this line is floating and results in PERST# being asserted until ramstage where the GPIO was originally configured. Because of this the wifi chip is not ready during the PCIe initialization step. Move the configuration of GPP_B8 to bootblock so that wifi device is taken out of reset as early as possible. BUG=b:64181150,b:62726961 TEST=Verified with warm reboot and suspend-resume stress test that wifi is still functional. Change-Id: I68e1bd67499262a17daade72e9a9fd32934a184d Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20869 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-04mainboard/google/soraka: Add gpio.c to bootblockFurquan Shaikh
Add gpio.c to bootblock so that the variant early_gpio_table can be used for configuration in bootblock. BUG=b:64181150,b:62726961 Change-Id: I77181334257f2fd19982ecafc1f58afe912f4280 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20878 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-04google/kahlee: Add ChromeOS SMBIOS Board IDMarc Jones
Kahlee uses 3 GPIO(144, 140, 135) pins to identify the board revision. Change-Id: Ia9693db6d6506af7ff40db0b3ce4cc6c1469f6ef Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-04soc/amd/stoneyridge: Use generic gpio libraryMarc Jones
Use the genric GPIO library. Add the required functions. Also, update the Kahlee mainboard dependency to match. Change-Id: I2ea562b052401efff3101f736788ca77d21e6de6 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20543 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-03google/kahlee: Add Realtek audio codec ASLIvy Jian
Add the RT5650 codec ASL for proper Linux driver loading. Devices visible to OS: /sys/bus/acpi/devices/AMDI1002:00 /sys/bus/acpi/devices/I2SC1002:00 Change-Id: I60b256f68372c9d17d67c9cb2accaca616a0b9a5 Signed-off-by: Ivy Jian <ivy_jian@compal.com> Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-01google/gru: Correct Scarlet pwm regulator minimum value and maximum valueLin Huang
In Scarlet pwm regulatoror minimum value and maximum value differs from other board variants, Correct it so we can get the right voltage. Change-Id: I1f722eabb697b3438d9f4aa29c205b0161eb442a Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/20831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-08-01google/gru: Correct the Sdcard control gpio setting for ScarletLin Huang
in Scarlet the Sdcard control gpio differs from other board variants, So set the GPIO to high on Scarlet. Change-Id: I5fa19b212a716213462eea58b6242392d32a2c5c Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/20803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-01google/gru: Use 1.8V powerdomain for gpio4cd on ScarletLin Huang
Scarlet gpio4cd use 1.8V powerdomain, let's make a correct register setting, otherwise even the uart does not work. Change-Id: Ib5a8b2a4d92502fb829688d0a3e1b645d53cd7fc Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/20802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-07-31google/kahlee: Add mainboard GPIOs to ACPIMarc Jones
Add the Google mainboard GPIOs to the ACPI table. Change-Id: I9b5952ed3934b938cb50650890a7b434e6306fd1 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-31google/kahlee: Fix CTRL+U USB bootMarc Jones
The EC KBC controller was not initialized, so the EC wouldn't put keys in the output buffer. With nothing in the buffer, vboot didn't try to boot the USB stick. Add the driver to setup the KBC called by EC init. BUG=b:62066405 BRANCH=none TEST=Boot Kahlee with USB stick and CTRL+U boots the stick. Change-Id: If9346fda558e802536c7de38da5b21fd25320e40 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20480 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-31google/kahlee: Move mainboard_ec_init to chip init phaseMarc Jones
Move mainboard_ec_init out of mainboard enable to the more appropriate mainboard init phase. Change-Id: Ieabcecf70e4de0b42fc639d031755b6d0b66f08a Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-31soc/amd/stoneyridge: Move ACPI MADT table to socMarc Jones
Move the mainboard MADT tables to generic soc ACPI code. Change-Id: I49fb55b1315da8fe65421b43fc4312ed588d5ecb Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20277 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-31google/kahlee: Add EC and GNVS ACPIMarc Jones
Add ACPI support for the Google EC, which requires GNVS support for passing information from the EC to firmware and OS. Change-Id: I0a308bcd608a135cc9633273a05527f020b60743 Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/20276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-31google/kahlee: Enable TPMMarc Jones
Set up the TPM decode to SPI prior to verstage. Enable LPC TPM and remove the mock data. Note, Kahlee TPM is on SPI, but decoded by the LPC block. BRANCH=none BUG=b:62103024 TEST=coreboot and Depthcharge reports TPM found. Change-Id: Iab92259ebeaa40937309fad05cc45d9ca6d41357 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-31google/kahlee: Save VBNV data to CMOSMarc Jones
Store VBOOT NV data in CMOS. This allows VBOOT to save flags and data to be used in multiple stages and depthcharge. Fixes developer mode USB boot. Change-Id: I50b45e687a1a1c71838bcc390212b28d7e634a19 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-31google/kahlee: Set DDI port 2 to DPMarshall Dawson
Set DDI port 2 type to Display Port. Change-Id: Idc5e57e01d4f0073ac50533c1b04a95bcae67473 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-31google/kahlee: Setup the I2S audio codecMarshall Dawson
Inform AGESA to setup an I2S codec instead of an Azalia codec. This is step one for audio to work. ASL to connect the driver and the hardware is in a follow-on patch. Change-Id: I7ece5d8c317ddc76e0e6b2a005256bc384fe51e2 Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/19841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-30intel/sandybridge: Gather MMCONF_BASE_ADDRESS defaultsNico Huber
All affected boards did the same USE_NATIVE_RAMINIT distinction or actually selected USE_NATIVE_RAMINIT. Also update autoport. Change-Id: I924c43cec1e36e84db40e4b8e1dd0e05cad2b978 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/20813 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-18 07:58:34 +0000