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2021-05-18mb/google/dedede: To support ELAN Touchpad device on I2C0Alex1 Kao
Add ELAN Touchpad device under I2C0 BUG=b:188373661 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com> Change-Id: I15b9cb0d0276b5e2dd06694530cc35e5643efb9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/52936 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-18mb/google/brya: Enable HECI1 communicationSridhar Siricilla
The patch enables HECI1 interface to allow OS applications to communicate with CSE. TEST=Verify PCI device 0:16.0 exposed in the lspci output Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I73acdd99788f9b60b7bcea372145e9694a124174 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54210 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-18mb/google/dedede/var/cret: Enable/disable LTE function based on FW_CONFIGDtrain Hsu
Enable/disable LTE function based on LTE bit of FW_CONFIG. The LTE function settings are included GPIO settings, USB port settings and power off sequence. BUG=b:187797408 BRANCH=dedede TEST=Build and test the change on cret. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Ib926e99aaf9df433a7cff71180ee55431d69f718 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-05-18mb/google/cherry: Pass reset gpio parameter to BL31Yidi Lin
To support gpio reset SoC, we need to pass the reset gpio parameter to BL31. TEST=execute `echo b > /proc/sysrq-trigger` to reboot system Change-Id: I1a55216c0d5a00bbdb373d931bd50ebe7ca5694f Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-16mb/google/mancomb: enable DDI0-DP portIvy Jian
Configure DDI-0 connector type to DP. BUG=b:187856682 TEST=Build and boot into OS Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: Ic8af14509b0d246c5c2da6e1a48991384471e69f Reviewed-on: https://review.coreboot.org/c/coreboot/+/54297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-05-14mb/google/volteer: Configure TCSS OC pinsNick Vaccaro
TCSS OC pins have not been correctly configured for volteer. This patch fills the value from devicetree to correct the OC pins mapping. BUG=b:184660529 BRANCH=None TEST="emerge-volteer coreboot chromeos-bootimage", flash volteer2 and verify CpuUsb3OverCurrentPin UPDs get set correctly. Change-Id: I12da755a1d3b9ec3ed0a2dbfb0782313dd49c7e9 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-14mb/google/cherry: Add DRAM calibration supportRex-BC Chen
Initialize and calibrate DRAM in romstage. Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.com> Change-Id: Ib7677baef126ee60bf35da3a4eaf720eaa118a27 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-05-14mb/google/dedede/var/boten: Modify DPTF parametersStanley Wu
DPTF parameters from thermal team. 1. Modify TSR1 sensor as charge sensor. 2. Modify P-state parameter BUG=b:180641150 BRANCH=dedede TEST=build and verified by thermal team. Change-Id: I43002db61de650d29cd85944a4eaea1b2f99aec4 Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52755 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-14mb/google/zork: update DRAM table for berknip/dirinboz/gumbozKevin Chiu
Add Samsung DDR4 memory part K4AAG165WB-BCWE 16Gb index was generated by gen_part_id BUG=b:180986354 TEST=none Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I94b950b51b41767676ab3ddf89e88860c42f5f1d Reviewed-on: https://review.coreboot.org/c/coreboot/+/54250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-05-14mb/google/volteer/var/volteer: add specific wifi SAR for voltaSheng-Liang Pan
volta will use different wifi SAR from voxel. Using clamshell mode of fw config to decide to load volta wifi sar. BUG=b:184820057 TEST=build and verify wifi power as expect. Cq-Depend: chrome-internal:3824093 Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I000aefca63346c70556688f232ca54360b3badef Reviewed-on: https://review.coreboot.org/c/coreboot/+/54051 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-14mb/google/brya: Use FW_CONFIG LTE_PCIE to turn on/off the PCIE6Eric Lai
PCIE6 only needed when use the PCIE LTE. BUG=b:180166408 BRANCH=none TEST=FM350 can/can't be detected when enable/disable this config. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I9dce05fdb6eb956a054d3815ff706b94f0d3fc37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-14mb/google/brya: Add the first FW_CONFIG fields to brya0Tim Wawrzynczak
1) USB sub-board 2) SD sub-board 3) GSC 4) Keyboard backlight 5) Audio sub-board 6) LTE module Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I74ca5ab5366a17e9e1784ec872b9cd77f8663c7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/54097 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-14mb/google/mancomb: Update HUB_RST_L setting in GPIOIvy Jian
Configure USB HUB_RESET_L gpio to high. BUG=b:187485847 TEST=Build and boot from USB to OS, check the USB function. Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: I94e4806c7463030df31f8d819510f9533a622f2a Reviewed-on: https://review.coreboot.org/c/coreboot/+/54078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-05-14mb/google/guybrush,mancomb: select GOOGLE_SMBIOS_MAINBOARD_VERSIONIvy Jian
Select GOOGLE_SMBIOS_MAINBOARD_VERSION allows querying board revision from the EC. BUG=b:187904819 TEST=1. emerge-guybrush coreboot chromeos-bootimage 2. flash the image to the device and check board rev by using command `dmidecode -t 1 | grep Version` Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: I48dc83d85cfc49e2e4155e389814fce08693c4bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/54084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-05-14cbfs: Increase mcache size defaultsJulius Werner
The CBFS mcache size default was eyeballed to what should be "hopefully enough" for most users, but some recent Chrome OS devices have already hit the limit. Since most current (and probably all future) x86 chipsets likely have the CAR space to spare, let's just double the size default for all supporting chipsets right now so that we hopefully won't run into these issues again any time soon. The CBFS_MCACHE_RW_PERCENTAGE default for CHROMEOS was set to 25 under the assumption that Chrome OS images have historically always had a lot more files in their RO CBFS than the RW (because l10n assets were only in RO). Unfortunately, this has recently changed with the introduction of updateable assets. While hopefully not that many boards will need these, the whole idea is that you won't know whether you need them yet at the time the RO image is frozen, and mcache layout parameters cannot be changed in an RW update. So better to use the normal 50/50 split on Chrome OS devices going forward so we are prepared for the eventuality of needing RW assets again. The RW percentage should really also be menuconfig-controllable, because this is something the user may want to change on the fly depending on their payload requirements. Move the option to the vboot Kconfigs because it also kinda belongs there anyway and this makes it fit in better in menuconfig. (I haven't made the mcache size menuconfig-controllable because if anyone needs to increase this, they can just override the default in the chipset Kconfig for everyone using that chipset, under the assumption that all boards of that chipset have the same amount of available CAR space and there's no reason not to use up the available space. This seems more in line with how this would work on non-x86 platforms that define this directly in their memlayout.ld.) Also add explicit warnings to both options that they mustn't be changed in an RW update to an older RO image. BUG=b:187561710 Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I046ae18c9db9a5d682384edde303c07e0be9d790 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-05-13mb/google/brya: enable DPTF functionality for bryaSumeet R Pawnikar
Enable DPTF functionality for Alder Lake based brya BRANCH=None BUG=b:188028732 TEST=Built and tested on brya board Change-Id: I33266c85aa30869466034ccbab04a3c7820ae2b0 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-13mb/google/zork/var/shuboz: update USB OC pin mappingKane Chen
modify USB OC pin setting for Shuboz/Jelboz/Jelboz360 Shuboz/Jelboz: usb_port_overcurrent_pin[0] = "USB_OC_PIN_0" # USB C0 usb_port_overcurrent_pin[1] = "USB_OC_PIN_0" # USB A0 usb_port_overcurrent_pin[2] = "USB_OC_PIN_1" # USB A1 usb_port_overcurrent_pin[3] = "USB_OC_PIN_1" # USB C1 Jelboz360: usb_port_overcurrent_pin[0] = "USB_OC_PIN_0" # USB C0 usb_port_overcurrent_pin[1] = "USB_OC_PIN_0" # USB A0 usb_port_overcurrent_pin[2] = "USB_OC_NONE" # NONE usb_port_overcurrent_pin[3] = "USB_OC_PIN_1" # USB C1 BUG=b:182879559 BRANCH=zork TEST=emerge-zork coreboot, validate the OC mapping. Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: Icc1fa090109e6be54e2a5f49e364f5502f53aca2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51523 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-05-13mb/google/volteer/variants/copano: Redefine GPIO_EC_IN_RW to GPP_F17Hao Chou
Redefine GPIO_EC_IN_RW to GPP_F17 Signed-off-by: Hao Chou <hao_chou@pegatron.corp-partner.google.com> Change-Id: I428eb8db34c80d38899a2b823ec7193de4a8f5e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-13mb/google/dedede/var/magolor: Select touchscreen based on SSFC in FW_CONFIGDavid Wu
Select touchscreen(s) based on touchscreen source provisioned in SSFC of CBI (higher 32 bits of FW_CONFIG in coreboot). The reason is to avoid to enable multiple touchscreen ICs with the same slave address. BUG=b:186609348 TEST=build and boot to OS. Change-Id: I087ea677a8865fc8c5b3f7c9773bd7f97924dbb3 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52851 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Marco Chen <marcochen@google.com>
2021-05-13soc/mediatek/mt8195: Enable SCP SRAMRex-BC Chen
Enable SCP SRAM to allow module in SCPSYS to access DRAM. TEST=AFE acess DRAM successfully Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I40862f8d74e5aa17361f1c91ea31a10b0a4ffb31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54014 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-12mb/google/dedede/var/metaknight: Update DPTF parametersDavid Wu
Remove TSR2 and use DPTF parameters from internal thermal team. BUG=b:175938681 TEST=build and boot to OS. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: If0ec1ec48b8971efe87f1f8d10332a9c16352122 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raymond Wong <wongraymond@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-05-12mb/google/guybrush: Configure wake resource for WiFiKarthikeyan Ramasubramanian
In order to support wake on WLAN events, configure the wake resource. BUG=b:186011392 TEST=Build and boot to OS in guybrush. Ensure that WiFi power resource is added to SSDT. Device (\_SB.PCI0.GP20.WF00) { Name (_UID, 0x38B82CBC) // _UID: Unique ID Name (_DDN, "WIFI Device") // _DDN: DOS Device Name Name (_ADR, 0x0000000000000000) // _ADR: Address } Scope (\_SB.PCI0.GP20.WF00) { Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x08, 0x03 }) } Change-Id: Ic238d9606aea20c058e9b47093693f10b14e6288 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2021-05-12mb/google/guybrush,mancomb: Adjust GBB size to 12KBMartin Roth
The 448KB size of the GBB is larger than is needed, so adjust it down to the minimum size needed. BUG=b:186761897 TEST=Build & Boot guybrush Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I7a24945cd9ecc8872871f57b09ca71fc40e92473 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-12mb/google/octopus/var/phaser: add audio codec into SSFC support for PhaserKevin Chang
Add audio codec module RT5682 in project and define GPIO_137 in the override_table for SSFC framework to adjust IRQ configuration. BUG=b:182221327 BRANCH=octopus TEST=adjust SSFC value of CBI to select RT5682I or DA7219 then check whether device tree is updated correspondingly by disabling unselected one. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I202f71f57ad2db84fb90b52f9ffd7a1fd05494a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52878 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com>
2021-05-12mb/google/volteer: Create chronicler variantSheng-Liang Pan
Create the chronicler variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:187318819 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_CHRONICLER Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Iebfea87b7c4cfc2a83e88a6c479a0842774ae018 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: YH Lin <yueherngl@google.com>
2021-05-12mb/google/octopus/var/fleex: Add cs42l42 HSBIAS settingIan Feng
Disable HSBIAS sense setting. BUG=b:184103445 TEST=boot to check cs42l42 is functional. Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I12c0e0a0f7490d35d36fe8ccbc940f29e1bb7976 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Vitaly Rodionov <vitaly.rodionov@cirrus.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-12mb/google/dedede/var/boten: Probe and enable amplifier operation modeStanley Wu
Probe the fw_config for RT1015 speaker amplifier operation mode and enable it accordingly in the device tree. BUG=b:180570923 BRANCH=dedede TEST=ALC1015Q-VB drive speaker OK Change-Id: I756bfa6f604ed320de9a515821979aa95c869ebf Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-05-12mb/google/dedede: Add GPIO and SPD for pirika supportKirk Wang
Add support for GPIO and SPD driver for pirika BUG=b:184157747 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com> Change-Id: Id367a83b04aad62b7deabae99b3f91905a2fc46c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-05-11mb/google/dedede/var/metaknight: Update LTE USB port configurationKarthikeyan Ramasubramanian
Update LTE USB port configuration at run-time after probing the firmware config. By default the concerned USB port takes the Type-A port configuration. BUG=b:186380807 BRANCH=dedede TEST=Build and boot to OS in metaknight Change-Id: I5ad5a1670adef54075923cf912fb41a1ce776155 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Raymond Wong <wongraymond@google.com>
2021-05-11mb/google/dedede: Add a variant callback to update devicetree configDavid Wu
This callback is required to update the devicetree config at run-time after probing the firmware config. BUG=b:186380807 BRANCH=dedede TEST=Build and boot to OS in metaknight. Change-Id: I857211bfc4beb36ab225f3786c1707336a34aae9 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Raymond Wong <wongraymond@google.com>
2021-05-11mb/google/kukui: Add discrete EMCP LPDDR4X table for Kakadu/KatsuSunway
Add EMCP LPDDR4X DDR FEPRF6432-58A1930 for ram id 9. BUG=b:186141919 BRANCH=kukui TEST=New Emcp can boot normally on kakadu/katsu Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com> Change-Id: Ieaf05a0a7b0c0671c07b0df29319ebd91fe63e57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54009 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-10mb/google/cherry: Configure TPMYidi Lin
Change-Id: I1d6ecdb31eef65d2e96d9251348390aa8598be6c Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-10mb/google/cherry: Enable Chrome ECYidi Lin
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Iab3549b5c4e7d845ddd284a0df3fb448e11fbdcb Reviewed-on: https://review.coreboot.org/c/coreboot/+/53899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-10mb/google/mancomb: Fix TPM setting in devicetreeIvy Jian
Fix I2C3 setting for TPM in devicetree. BUG=b:187341277 TEST=Build and boot into OS Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: I728da76cee0c92c29df4c6ee8bfb4cd07a6366c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-05-10mb/google/guybrush: Enable GFX HDA deviceKarthikeyan Ramasubramanian
Enable Display Controller Engine Audio endpoint to enable HDMI audio. BUG=b:186479763 TEST=Build and boot to OS in guybrush. Change-Id: I5e35440e8e70ee125d37c7ac30c9219ec69c7c6e Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-05-10mb/google/guybrush: Enable PP5000_PENEric Peers
Everybody wants a stylish stylus. Enable the power system to it. BUG=b:186267293 TEST=connect multimeter to PP5000_PEN and see it go from 0 to 1. MAGIC! Signed-off-by: Eric Peers <epeers@google.com> Change-Id: I11d05c118ec9451d26136c320f3650c489e02c59 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-05-10soc/mediatek/mt8195: Add RTC driverYuchen Huang
Both mt8192 and mt8195 use MT659P RTC. Move mt8192/rtc.c to common folder and rename to rtc_mt6359p.c. Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com> Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: I73ea90512228a659657f2019249e7142c673e68e Reviewed-on: https://review.coreboot.org/c/coreboot/+/53897 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-10soc/mediatek/mt8195: Add clk_buf driverYuchen Huang
Both mt8192 and mt8195 use mt6359p clk_buf. But mt8195 clk_buf uses legacy co-clock mode without srclken_rc. Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com> Change-Id: Ie9ee91449a7a14e77231493f807b321b2dbaa6a6 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-10soc/mediatek/mt8195: Configure eMMC and SDCardWenbin Mei
Change-Id: I0ed82e860612e8a62f361e60d217280f775ab239 Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com> Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53895 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-09mb/google/guybrush: Populate PIC IRQ dataRaul E Rangel
The PIC IRQs are required so we can correctly set up the PCI_INT registers. This only matters when booting in PIC mode. We don't need to set the IO-APIC registers since the linux kernel will auto-assign those to reduce conflicts. BUG=b:184766519 TEST=Boot guybrush with `pci=nomsi,noacpi amd_iommu=off noapic` and verify xhci and graphics continue to work. $ cat /proc/interrupts 12: 285064 XT-PIC nvme0q0, nvme0q1, rtw88_pci 13: 100000 XT-PIC xhci-hcd:usb1 14: 4032 XT-PIC amdgpu, xhci-hcd:usb3 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1d66ccd08a86a64242dbc909c57ff9685828f61f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52915 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-08mb/google/volteer: adjust the size for RO/RW mcacheZhuohao Lee
The mcache is overflowed in the latest build. In order to fix the mcache overflow, we increase the mcache size to 0x4000 and adjust the percentage to 50% for the ro/rw mcache. This change is for all of the volteer variants as we see many of the volteer variants which use the latest bios having the mcache overflow issue. BUG=b:187095474, b:187095765, b:187234881, b:162052593 TEST=no mcache overflow in the bios log Change-Id: If9552bc9fa5d36b1ca662c9da030ae7b137b60a8 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-05-08trogdor: Add backlight support for sn65dsi86bridge for HomestarVinod Polimera
Add backlight support in sn65dsi86bridge through the AUX channel using eDP DPCD registers, which is needed on the GOOGLE_HOMESTAR board. Change-Id: Ie700080f1feabe2d3397c38088a64cff27bfbe55 Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org> Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52663 Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-07skylake mainboards: Use enum values for SaGvAngel Pons
Replace `3` with `SaGv_Enabled`, which has the same value. Change-Id: I05cfddfefc45ba5bfb0e684445a6d8e02d7865e3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-05-07mb/google/volteer: Create volet variantSheng-Liang Pan
Create the volet variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:186334008 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_VOLET Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Ic6ca9a78494e3819b0fb39c0bcc70fed95c2c589 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-05-07mb/google/cherry: configure GPIOsYu-Ping Wu
Configure Chromebook specific GPIOs, including EC_AP_INT, SD_CD, EC_IN_RW, GSC_AP_INT and EN_SPK. Change-Id: Id553f632412af440d21a3b51e017cb74cc27fd22 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52924 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-07mb/google/volteer/var/elemi: Add spd for K4AAG165WB-BCWEWisley Chen
Add SPD support to elemi for K4AAG165WB-BCWE BUG=b:187379245 TEST=FW_NAME=elemi emerge-volteer coreboot chromeos-wqbootimage Change-Id: I839447a9e7c7b6558b2d0877c67dc9cf89ee792a Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-05-07mb/google/mancomb: Update AMDFW config fileMartin Roth
Mancomb uses DDR4 SODIMMs, but the default cezanne configuration is for the LPDDR4 version. This changes to use SODIMMS. Further changes may be needed for platform customization, so I put the config file in variants/baseboard instead of the root mancomb directory. BUG=b:187094481 TEST=Build only Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Icc4dc8aec2053cb177765f57e57cac7a099508fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/52900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-06mb/google/mancomb: Implement tis_plat_irq_statusMartin Roth
This patch was implemented on Guybrush at CB:52352 BUG=b:185397933 TEST=Build Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I141a504a827f37724fab0aaed7498fd543e471d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-06mb/google/mancomb: Update Kconfig with needed optionsMartin Roth
DISABLE_KEYBOARD_RESET_PIN - This pin goes to a test point and is not used for the reset. DRIVERS_UART_ACPI - Add the UART ACPI code FW_CONFIG - Mancomb uses the firmware config interface PSP_DISABLE_POSTCODES - The PSP is not yet initializing eSPI correctly to send post codes to the EC, so disable them for now. BUG=None Test=Build Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I39efcc8d1e0fb1e7ac0b0541a49db0ac0ee56481 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-06mb/google/mancomb: Fix EC SCI configurationMartin Roth
This change fixes two problems: 1) We had the enum values for .direction and .level swapped. The naming is very confusing... 2) ESPI_SYS is not a good event to use for EC SCI. It is a level/low event that is only cleared by reading the eSPI status register 0x9C. Cezanne has added a new event source that directly exposes the SCI bit. This is the correct event source to use for EC SCI. This same patch was added for Guybrush at CB:52673 BUG=b:186045622, b:181139095 TEST=Build Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Iac86d2ef5bdd21fbb0a0d4e235efe4fe621023b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52948 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-11 11:01:53 +0000