Age | Commit message (Collapse) | Author |
|
Most affected boards set the function disabled (FD) register to an
arbitrary state dumped from systems running the vendor BIOS. This
makes it impossible to enable the devices in devicetree and a pretty
big mess of course because nobody cared to keep the register in sync
with the devicetree.
To get completely rid of most of the writes to FD, move setting of
PCH_DISABLE_ALWAYS into the southbridge code where it belongs.
Change-Id: Ia2a507cbcdf218d09738e2e16f0d3ad1dcf57b8b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/23255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hal Martin <hal.martin+coreboot@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Bill XIE <persmule@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
this enables the MRC recovery cache for zoombini & variants.
the Kconfig options are:
HAS_RECOVERY_MRC_CACHE
MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
one note of caution: early board builds will likely fail to boot with:
tlcl_extend: response is 0
tlcl_extend: response is 0
tlcl_lock_nv_write: response is 0
tlcl_lock_nv_write: response is 28b
Failed to lock rec hash space(1f)
Saving nvdata
hard_reset() called!
the fix is to boot into recovery once, then it's business as usual.
using servo, this can be done with:
dut-control power_state:rec
BUG=b:71785303
BRANCH=chromeos-2016.05
TEST=boots on meowth...
Change-Id: I77f36d36a70c8c9c74a7fa3a114d3177f33a708b
Signed-off-by: Caveh Jalali <caveh@google.com>
Reviewed-on: https://review.coreboot.org/23298
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
this adds missing ACPI entries for the EC, CPU, and power button.
also, the EC to AP wakeup pin assignment is fixed.
BUG=b:71819257
BRANCH=chromeos-2016.05
TEST=booted on meowth. /sys/class/power_supply now gets populated.
Change-Id: I0d091bdf25f9a806bd36329d1f17ac34b3115e48
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/23237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
|
|
This patch removes IccMax settings from device tree since they
are handled in SoC code from patch e1a75d.
BUG=b:71369428
BRANCH=None
TEST="USE=fw_debug emerge-fizz chromeos-mrc coreboot
chromeos-bootimage" & ensure the IccMax settings passed
to FSP are from SoC code.
Change-Id: I6b01c50a2589d1722c5bf4aa2f44a9574df818f4
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/23278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
|
|
Turn on the load switch to the FP MCU at startup, so the kernel can
detect it and use it.
The load switch enable pin is connected to the GPP_A11 PCH pin (aka
PCH_FP_PWR_EN).
BRANCH=none
BUG=b:71986991
TEST=on Meowth, see the kernel detecting a cros_fp device at startup:
[ 2.133456] cros-ec-spi spi-PRP0001:00: Fingerprint MCU detected.
[ 2.157420] cros-ec-spi spi-PRP0001:00: Chrome EC device registered
Change-Id: Id3c40b965a5f018c63481c2e2eea3fc8307352bd
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://review.coreboot.org/23329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Configure the FP MCU interface on GSPI1.
BRANCH=none
BUG=b:71986991
TEST=boot on reworked Meowth with a ZerbleBarn board attached to
GSPI1 and see the cros_ec kernel driver detecting it.
Change-Id: Ib874ddaf4948a766fd05c11f4675dbfdb679059d
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://review.coreboot.org/23328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Add support for new memory stuffing options that will appear on
the P1 meowth boards.
new strap setting - associated SPD file
----------------------------------------
0b001 - Hynix_H9HCNNN8KUMLHR_1GB.spd.hex
0b010 - Samsung_K4F6E3S4HM_2GB.spd.hex
0b011 - Hynix_H9HCNNNCPUMLHR_4GB.spd.hex
BUG=b:69011806
BRANCH=none
TEST=none
Change-Id: Ief07f3de351d01cbc195b785c36e96de0cbf7ddb
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/23267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
* Rename tlcl* to tss* as tpm software stack layer.
* Fix inconsistent naming.
Change-Id: I206dd6a32dbd303a6d4d987e424407ebf5c518fa
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/22104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
* Move code from src/lib and src/include into src/security/tpm
* Split TPM TSS 1.2 and 2.0
* Fix header includes
* Add a new directory structure with kconfig and makefile includes
Change-Id: Id15a9aa6bd367560318dfcfd450bf5626ea0ec2b
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/22103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Our current U22 skus (celeron and i3) actually don't support PL2,
but making sure that if we do decide in the future to use it to
make sure PL2 and PsysPl2 values are set appropriately.
BUG=b:71594855
BRANCH=None
TEST=Make sure that PsysPL2 value set to 90W with barrel jack for U42
and 65W with barrel jack for U22.
Change-Id: I084d0320128a6e05948023520a30c497c41be23b
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/23294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Enable S0ix wake mask programming from coreboot using unified host event
programming interface. Lazy s0ix wake mask helps to configure s0ix wake
mask during boot and EC sets the wake mask during S0ix entry.
BRANCH=none
BUG=b:63969337
TEST=verify masks with ec hostevent command on S0,S3,S5 and S0ix
Change-Id: I65173104fce258d03956bbb0e80073c47fe80fab
Signed-off-by: Jenny TC <jenny.tc@intel.com>
Reviewed-on: https://review.coreboot.org/21086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
* Add IMX258 sensor entity
* Add DW9807 VCM control entity
* Enable CIO2 and IMGu in devicetree.cb
TEST: Verified the MIPI camera function on DUT board
Change-Id: Iebd41ac3631829bbb0b008761eb67c3db3e94638
Signed-off-by: Andy Yeh <andy.yeh@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/23056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
|
|
Right now the poppy baseboard camera topology allows to add maximum of 2
sensors. The sensors can be of different vendors. The current ASL code
structure doesn't allow sensor customization. Moving PMIC specific objects
from sensor objects to PMIC scope and having separate sensor ASL files will
help in unbinding the PMIC and sensor objects and allow some customizations.
BUG=None
BRANCH=None
TEST=Build and boot soraka, make sure both camera's are working fine
and also verify that the generated DSDT looks fine.
Change-Id: I63ae1a685b78bda212c5c48a4c2dc744164a3cb5
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/23168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
|
|
The variant boards can have a custom endpoints, splitting the ASL code
aids customizing the endpoints as per the variant board setup.
BUG=None
BRANCH=None
TEST=build boot soraka, verify that the cameras are working fine and
generated DSDT tables are same as before.
Change-Id: I5f1cded25bfb6a7baf18b211f9773dfecdc2f264
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/23167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
|
|
BUG=b:71838954
TEST=
1. emerge-nami coreboot chromeos-bootimage
2. check touchpad function
3. evtest
/dev/input/event5: Elan Touchpad
Change-Id: I14471d1473a3b3ecf15aaf362b47874704cd3bf0
Signed-off-by: van_chen <van_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/23133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
GPIO 90 is being used as a GPIO. The IOMUX register is set correctly,
but these additional registers need to be set to use it as a GPIO.
- Split structures into variant specific versions. These will be
moved into the variant tree in a follow-on patch
- Set GENINT_DISABLE bit
- Disable interrupts for this GPIO.
BUG=b:71867096
TEST=Build and boot grunt. Verify registers are set correctly.
Change-Id: I4b8d12720167b298ee6e0acf80edf414539975b0
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23228
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The GPIOs that are being set low had the wrong value getting set.
FCH_GPIO_OUTPUT_VALUE was being set instead of FCH_GPIO_OUTPUT_ENABLE.
BUG=b:70234300
TEST=Build and boot Grunt
Change-Id: I16792b76252506a43aac92738b04096ae3fde01c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
|
|
Grunt and Kahlee touchpads are on different i2c busses; I2CC and I2CD,
respectively.
Since grunt is the 'baseboard', put its configuration under baseboard, and
include it from the grunt variant.
BUG=b:71820409
TEST=Boot grunt to kernel, use evtest to test trackpad.
TEST=Boot kahlee to kernel, use evtest to test trackpad.
Change-Id: I1aeacf9a840342e73c1e219a825b39a124b4dd57
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/23232
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Grunt and Kahlee have different audio codecs.
Create a new audio .asl for the baseboard for grunt's codec, link
to it from the grunt mainboard, and move the kahlee codec table
from the baseboard mainboard to its own .asl in variant/kahlee.
Note, we can't use the generic drivers due to the PCI scope
expectation. The AMD I2C are not PCI devices.
BUG=b:69397774
TEST=Codec driver loads. Check dmesg.
Change-Id: I1cc245357d1f3d444e5a5012466eaa5d75d637eb
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/23226
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Move the apci/ to the baseboard and move mainboard.asl to
each variant.
BUG=b:71873651
TEST=build
BRANCH=none
Change-Id: I8a829f2946e4b280cd78574eb8dbda6c2a9a1028
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23229
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
|
|
Meowth uses GPD_2 as a dedicated lan_wake pin, so GPD_2 must
be set to use NF1 instead of gpio.
BUG=b:64395641
BRANCH=none
TEST=none
Change-Id: Iadf7158a792dfae0ea5e824d197a558524cdb5fd
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/23222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Change PAD_CFG_GPI_GPIO_DRIVE to PAD_CFG_GPI_APIC for GPIO D9 to
meet the requirement of DA7219 IRQ pin.
BUG=b:70646770
BRANCH=none
TEST=Use aplay and arecord to verify headphone function.
Change-Id: Id6cff8325c4c7f02f6f4df547fde286e2ef83d5c
Signed-off-by: Kaiyen Chang <kaiyen.chang@intel.com>
Reviewed-on: https://review.coreboot.org/23160
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
TCPU:
_CRT: 100
_PSV: 93
_TRT: 100/5(s)
TSR0:
_CRT: 83
_PSV: 70
_TRT: 100/10(s)
TSR1:
_CRT: 73
_PSV: 67
_TRT: 100/30(s)
TCC: 6 for 94'C
PL1:
max: 15W
min: 3W
BUG=b:70294260
BRANCH=master
TEST=build
Change-Id: Ie17f4395d2199009fd68a600d818f2be54bc8935
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/23155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Fizz has external Lan on PCIE port.
The Lan device on PCH is not used.
BUG=b:70889517
Change-Id: I99894bedec14a44724ac7c22d0c894132a795b78
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/23180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Digitizer power is not controlled by SoC. Also, since the digitizer
uses I2C-HID driver in Linux kernel, the device is put into sleep
anytime system is suspended. Thus, there is no need to control the
reset gpio using ACPI power resource.
TEST=Verified that digitizer device is properly detected on boot-up
and after suspend/resume.
Change-Id: Id11b8412d0ac48b2701d53b0a22ad3b747b544ec
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/23212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
- Add pen device property into devicetree.cb.
- Set GPP_C9 to 0 as default.
BUG=none
BRANCH=master
TEST=emerge-nautilus coreboot and check pen device operation
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Change-Id: I050671c8b46fd92b1dd9164be2646727cd67da9f
Reviewed-on: https://review.coreboot.org/23010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
The Port initializer had been changed from PortDisabled to PortEnabled,
but engine inializer hadn't been updated from PcieUnusedEngine to
PciePortEngine. Update this so the port works.
Also change disabled port to PcieUnusedEngine.
BUG=b:71818026
TEST=PCIe device now shows up on D2F4
Change-Id: I11eb8c1fbad12fa9cf34d758a4ef3c22ef8ba4f7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23210
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Chris Ching <chingcodes@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
If using type-C charger, then PsysPl2 may be lower than barrel jack
value of 90W, so need to override value to the max power of type-C
charger.
BUG=b:71594855
BRANCH=None
TEST=Make sure that PsysPL2 value set to 60W with zinger, but 90W
when using proper barrel jack adapter on and i7.
Change-Id: If955b9af0e23f47719f001f1d73ec37113937cea
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/23182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
BUG=b:64395641
BRANCH=none
TEST=none
Change-Id: I92969384cd32766be4595494aa70b4eb9c74f099
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/23206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
-add initialization of gpio table to mainboard_silicon_init_params()
-fix input parameter type for mainboard_silicon_init_params() for
FSP2_0.
BUG=b:69011806
BRANCH=chromeos-2016.05
TEST=none
Change-Id: If8cba786a127a8704eb240380841362e3eb06552
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/23194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Map EC io space in devicetree.cb
BUG=b:69011806
BRANCH=none
TEST=none
Change-Id: Ic3806b5f9b7bf272a77360060cd71db9a03d5763
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/23207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
BUG=b:69011806
BRANCH=chromeos-2016.05
TEST=Compiles successfully using "./util/abuild/abuild -p none
-t google/zoombini -x -a"
Change-Id: I8276fa26af664557e9964cb6b8a5a076eacdf00c
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/23198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
-add ec.c to bootblock if CONFIG_EC_GOOGLE_CHROMEEC
-add ramstage.c to ramstage.
BUG=b:69011806
BRANCH=chromeos-2016.05
TEST='emerge-meowth coreboot' compiles correctly.
Change-Id: I7ec1e22339f3e4d9a8d83093bcc2ce725c9c99e7
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/23196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
-change GPP_C12 (H1 IRQ) to use GPI_SCI_LOW and level triggered
-set gspi gpios to no connects if CONFIG_ZOOMBINI_USE_SPI_TPM not set
BUG=b:69011806
BRANCH=chromeos-2016.05
TEST='emerge-meowth coreboot' succeeds
Change-Id: Ida1d1050db12982c3c497656162cc84c62a77f70
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/23195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
-add USB2 and USB3 to devicetree
-add TPM_TIS_ACPI_INTERRUPT to Kconfig
-map gpe0_dw0, gpe0_dw1, and gpe0_dw2 blocks
BUG=b:64395641
BRANCH=chromeos-2016.05
TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a"
compiles successfully.
Change-Id: Ia7ed76591d9d8d94bbf5652313c478495ce005fa
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/23191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
The spd.bin file was not getting generated properly, so moved logic
to variant's makefile.
BUG=b:64395641
BRANCH=none
TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a"
compiles successfully and spd.bin is found when booting.
Change-Id: I4642d6ddb5e65f721d1bde31ca0ca5b4438da554
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/23190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
The .spd.hex text is added to the name by the build process. This
was causing a failure because we were trying to add the files:
'file.spd.hex.spd.hex' to the build.
Remove the additional .spd.hex text.
BUG=b:71535311
TEST=Build
Change-Id: I11df7a90c979503676a66c6502900a13f1a8e359
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23189
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chris Ching <chingcodes@chromium.org>
|
|
turn off SATA SALP to prevent 0x5A/0x5B error on Sandisk SSD
in below conditions:
1. reboot stress
2. FAFT BIOS qualification
BUG=b:70146894,b:69984821,b:70590720
BRANCH=master
TEST=pass firmware_ConsecutiveBoot 2500 loops
FAFT BIOS test pass
Change-Id: I5d57dd8ef256d5f0a1027ab77f63da62c6c9ce74
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/23153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
|
|
Add Meowth board, which derives from Zoombini, a CNL reference board.
BUG=b:69011806
BRANCH=master
TEST=Compiles successfully using "./util/abuild/abuild -p none
-t google/zoombini -x -a" and boots Meowth.
CQ-DEPEND=CL:22908
Change-Id: Ie6ed7ebb4a00a87fc93fc694d74c08a716380a54
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/22401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
Add support for memory configuration by providing weak implementation
from the baseboard. All SPD files are present under spd/
directory. SPD_SOURCES must be provided by the variants to ensure
that required SPD hex files are included in the SPD binary.
BUG=b:64395641
BRANCH=None
TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a"
compiles successfully.
Change-Id: I449ab56dfc7a75752944b58ba6291b5ee32f81ad
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/22205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
Since the current hardware revision does not have external pull on the
pen eject signal, this change adds internal pull-up on it.
Change-Id: I426d9833d7efbd8735b6f2b4896d1012b62cb4b8
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/23143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tony Lin <tonycwlin@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Rainier, a scarlet derived board, was configured to use spi0 for tpm
driver by default. This patch switches it to spi2 to reflect recent
changes in scarlet-derived boards.
Change-Id: Ib67109786512c068bb957890f456bccff7addc86
Signed-off-by: Ege Mihmanli <egemih@google.com>
Reviewed-on: https://review.coreboot.org/23129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
BUG=b:64395641
BRANCH=None
TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a"
compiles successfully.
Change-Id: I417a1c606e4968120414af57aa3b17d5c3b3cad0
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/23035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
- Enable I2C #2, #3, and #5
- Enable UART #2
- Enable GSPI #0 and #1
- Disable SATA
- Set pci 1f.0 to chromeec
BUG=b:64395641
BRANCH=None
TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a"
compiles successfully.
Change-Id: Ie29652beff36f19a59746a1ad5f8e7f995ef1281
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/23034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Add mainboard.c to ramstage.
BUG=b:64395641
BRANCH=None
TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a"
compiles successfully.
Change-Id: Ic7275b07f28a99a91b978d2e8c4118c6858705bc
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/23032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Grunt's devicetree dropped some entries when it was split from the
kahlee variant. This commit restores:
spd_addr_lookup - memory information for AGESA
dram_clear_on_reset - keeps DRAM contents on reset
uma_mode - needed for vbios
uma_size - needed for vbios
Change-Id: I1d8cdc97594867f1d706318370055087976a5104
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
The spd size of DDR4 is 512, but the size empty.spd.hex is 256.
With empty.spd.hex and DDR4, it will cause mainboard_get_spd_data
loads spd data incorrectly due to the offset is wrong.
Change-Id: Iea3f216898525a2a602fabf1835c8a0c1245ee57
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/23038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
This change is to enable SataPwrOptEnable.
With this change, we no longer see SError message in kernel during
suspend_stress_test.
BUG=b:70491485
Change-Id: Ieb991f6889c5ff3181a670bc7702314049fa983c
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/23019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
This patch revises LED0 Green light behavior from patch 2ecf3f8c.
For 100Mb link speed, LED0 should be OFF.
BUG=b:65437780, b:68284778, b:69950854, b:65808944
BRANCH=None
TEST=Run DUT with 100Mb and 1000Mb ethernet connection and observe
LED0 is behaving as expected.
Change-Id: Ia805c955711b8ce77eba087a28427a005c456fa1
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/22964
Reviewed-by: David Wu <david_wu@quantatw.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
New UPD PcieRpClkSrcNumber introduced in FSP V2.9.2 to configure
clock source number of PCIe root ports. This UPD array is set to clock
source number(0-6) for all the enabled PCIe root ports, invalid(0x1F)
is set for disabled PCIe root ports.
BUG=b:70252901
BRANCH=None
TEST= Perform the following
1. Build and boot soraka
2. Verify PCIe devices list using lspci command
3. Perform Basic Assurance Test(BAT) on soraka
Change-Id: I95ca0d893338100b7e4d7d0b76c076ed7e2b040e
Signed-off-by: Divya Chellap <divya.chellappa@intel.com>
Reviewed-on: https://review.coreboot.org/22947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|