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2021-04-26mb/google/mancomb: PCIe GPIOs - enable enables, disable resetsIvy Jian
To train PCIe devices, the devices need to be enabled and taken out of reset. This patch does the bare minimum needed to train PCIe. It is not intended to handle timings, which will be addressed later. Copy the enables for WLAN into early GPIO Init so that they're enabled before FSP-M runs and trains the PCIe busses. Again, this patch is the minimum to let the FSP train the PCIe busses. BUG=b:182202136 TEST=Boot guybrush from NVME. Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: I5e3e9fe21f44b832e26b0942759ae2ec96ec6c82 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-04-26mb/google/volteer/variant/lindar: Create dynamic fan table mechanismKevin Chang
Add dynamic fan table mechanism for Lindar and Lillipup. Create different fan tables that provided from thermal team. BUG=b:185308432 TEST=Build FW and boot to OS modify CBI test with DPTF tool. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I1b79dbe1ae6ee7aa41cef832b4ee305cc8f4b753 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-04-26mb/google/guybrush: Enable S0i3Karthikeyan Ramasubramanian
BUG=b:185939089 TEST=Build and boot to OS in Guybrush. Enter S0i3 after passing the sleep state configuration from the mainboard. Change-Id: I4b23b014ca45bd09c76b626b73b0332586dec056 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-26mb/google/brya: Enable GL9755 SD card readerEric Lai
Enable GL9755 SD card reader. BUG=b:185397257 TEST=SD card is functional in the OS. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ib3be54274ca796bedda76ce807a0bd630d1d8e4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-23mb/google/dedede/var/storo: Modify eeprom setting for MIPI cameraTao Xia
Currently, it fails to dump the nvme data by test command. It reports the following error: cat: '/sys/bus/i2c/devices/i2c-PRP0001:01/eeprom': Connection timed out So increase the value from 0x0400 to 0x2000 and double the address width from 0x08 to 0x10 to solve this problem. BUG=b:177393430 TEST=1. cat /sys/bus/i2c/devices/i2c-PRP0001:01/eeprom > /tmp/ov8856_eeprom.bin 2. hexdump -C /tmp/ov8856_eeprom.bin > ov8856_eeprom_dump.log 3. cat ov8856_eeprom_dump.log Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: Ia933927981f07e0f7954a4bc6d82f0bdd70181f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52048 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: ShawnX Tu <shawnx.tu@intel.com> Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-23mb/google/guybrush: Update memory configurationMartin Roth
The next guybrush build uses 2 new LPDDR4X memory chips: - Micro MT53E1G32D2NP-046 WT:B - Hynix H9HCNNNBKMMLXR-NEE The MT53E2G32D4NQ-046 WT:A chip has been added to the global LPDDR4X list since the last time guybrush was updated, so that's brought into the guybrush SPD directory as lp4x-spd-10.hex, but it's not used. BUG=b:186027256 TEST=Build only Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ia5efd548f8b9442fb3703518387175aba8933a33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-23mb/google/octopus/var/fleex: Add ssfc codec cs42l42 supportEric Lai
Add cs42l42 codec support in fleex. BUG=b:184103445 TEST=boot to check cs42l42 is functional. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I1571003f8b272a573e6ab9fb525f17659bae8c4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-22mb/google/brya: Enable display and DSP audio UPDSugnan Prabhu S
This patch includes changes to enable display and DSP audio UPD. BUG=b:181219097,b:183482000 TEST=Audio sound card is detected and listed by the linux kernel. Audio playback and capture is working on the Brya. Change-Id: I3dab02bedb6df995b1efd27332d3aa26985e188e Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-22mb/google/dedede/var/magolor: Select camera module based on SSFC valueSugnan Prabhu S
This patch has changes to support multiple cameras modules, based on the value set in the SSFC_CONFIG. BUG=b:176065425 TEST=Tested the changes with magolor 5MP and 8MP camera. Change-Id: I764abf70bacbe61452e7b0fd59c1b375227b5748 Signed-off-by: Shawn Tu <shawnx.tu@intel.com> Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-22guybrush: Increase eSPI bus frequency to 33MhzRob Barnes
Change eSPI bus frequency to 33Mhz. BUG=b:184356693, b:185514521 TEST=Boot guybrush, observe no eSPI bus errors Change-Id: Ie2c1b256531f5c7354600e35e9e5191567197feb Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52402 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-22guybrush: Add Kconfig for PSP eSPI and port80Rob Barnes
Add PSP_DISABLE_POSTCODES and PSP_POSTCODES_ON_ESPI kconfig options for cezanne. Select PSP_DISABLE_DISABLE_POSTCODES and unselect PSP_POSTCODES_ON_ESPI for guybrush. Port80 codes from PSP can cause bus errors on guybrush. BUG=b:185514903, b:184356693 TEST=Boot guybrush, observe no port80 codes from PSP Change-Id: I7241e47ec1b89782e699135370c796eb251afcaa Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52401 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-22soc/intel/cannonlake: Set DIMM_SPD_SIZE to 512Felix Singer
All related mainboards are setting DIMM_SPD_SIZE to 512. Therefore, default to 512 in the SoC Kconfig and drop it from related mainboard Kconfigs. Change-Id: Idb6a0e42961eeb490afd76b4aa7d940961991733 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52513 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-21mb/google/volteer/variants/drobit: Update DPTF parametersWayne3 Wang
Update the DPTF parameters. Modify TDP, Critical Policy and Active Policy setting. BUG=b:177777472 BRANCH=firmware-volteer-13672.B TEST=build test firmware and verified by thermal team. Change-Id: Ib57de5535f3d37765ac7051c17445c311c098927 Signed-off-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ariel Chang <ariel_chang@pegatron.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Paul Yang <paul.f.yang@intel.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-04-21ChromeOS: Use CHROMEOS_NVS guardKyösti Mälkki
Replace CONFIG(CHROMEOS) with CONFIG(CHROMEOS_NVS) for cases where the conditional and dependency are clearly about the presence of an ACPI NVS table specified by vendorcode. For couple locations also CONFIG(HAVE_ACPI_TABLES) changes to CONFIG(CHROMEOS_NVS). This also helps find some of the CONFIG(CHROMEOS) cases that might be more FMAP and VPD related and not about ChromeOS per-se, as suggested by followup works. Change-Id: Ife888ae43093949bb2d3e397565033037396f434 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50611 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-21mb/google/volteer/variants/copano: Modify touch controller power sequenceHao Chou
Based on the measurement, adjust the delay time between the main power rail and reset signal to 7ms in order to match the spec. of touch controller, eKTH7918U. BUG=b:184126265 BRANCH=firmware-volteer-13672.B TEST=build test firmware and verified by EE team. Change-Id: Iea84046c1b1f3fe6ab8bb89d86d00b1e89325f71 Signed-off-by: Hao Chou <hao_chou@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-04-21mb/google/volteer/variants/copano: Fix pen ejection eventHao Chou
Modify PENH device GPIO GPP_E17 for pen ejection event. BUG=b:182867209 BRANCH=firmware-volteer-13672.B TEST=emerge-volteer coreboot, check evtest if SW_PEN_INSERTED event (value:1/0) when insert/eject pen, and eject pen to wake system from s0ix Change-Id: I1b13d09ed6d065779de9441f2137dcf6559b8f27 Signed-off-by: Hao Chou <hao_chou@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52494 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul2 Huang <paul2_huang@pegatron.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-21mb/google/dedede/var/sasuke: Update DPTF parametersSeunghwan Kim
Add control charging current from TSR0 and correct charger_perf table value. BUG=b:179067801 BRANCH=dedede TEST=emerge-dedede coreboot Change-Id: Ie0d969898defe76952e5c136fa93b7edffe51de3 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Edward Doan <edoan@google.com>
2021-04-21mb/google/*: allow LAN MAC to be read from VPD w/o ChromeOSMatt DeVillier
Condition use of RO_VPD for LAN MAC address on CONFIG_VPD rather than CONFIG_CHROMEOS. Test: build/boot google/{beltino,jecht} with RO_VPD propagated from stock firmware, verify MAC address set correctly. Change-Id: I1606fe1936ccee6e03dee145901767c8e73bfe2d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52517 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-21mb/google/dedede/metaknight: Add device list and probe daughter-boardDavid Wu
Metaknight has two daughter-board (DB_PORTS_1A_HDMI and DB_PORTS_LTE_HDMI), LTE and USB Type A use the same usb port,so needs to probe daughter-board to avoid USB device cannot recognize correctly. BUG=b:184809456 TEST=build and verify USB device can recognize correctly Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ie42d12c7ce5c7341751c3cf92b5f37b6cd4d479f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52369 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raymond Wong <wongraymond@google.com> Reviewed-by: Kaiyen Chang <kaiyen.chang@intel.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-19Revert "mb/google/mancomb: Enable early EC Software Sync"Karthikeyan Ramasubramanian
This reverts commit 800193414148d5f39be42110fc2c76ad1ceb7d2f. EC software sync needs to be enabled in payload once the EFS2 requirements are met. BUG=b:185277224 TEST=Build. Cq-Depend: chromium:2829948 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ib22a89e221e1e057d82ef76b7008e5d3f14df5e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52451 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-19Revert "mb/google/guybrush: Enable early EC Software Sync"Karthikeyan Ramasubramanian
This reverts commit 1e36dc078e4012f884d67a32f1faac5f80406285. With EFS2 already enabled in EC, enabling early EC sync is not required. Also a workaround has been added in payload to address any boot issues. BUG=b:185277224 TEST=Build and boot to OS in Guybrush in both normal and recovery mode. Cq-Depend: chromium:2832032 Change-Id: I921dc5c814e5187dce283eeff43075b59885723a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52418 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-18mb/google/hatch: Guard ChromeOS fmd selection on CHROMEOSMatt DeVillier
Ensure the ChromeOS FMAPs are used only when CONFIG_CHROMEOS is selected, so non-ChromeOS targets use the default x86 FMAP. Change-Id: Id5d3e7a44973f2fadba3ea15e0e544eee7fa53e6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-18mb/google/mancomb: Remove PS/2 mouse configEric Lai
Sync from guybrush. BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I02b375b6fc134e56b7f55e1421f694daa4aa994d Reviewed-on: https://review.coreboot.org/c/coreboot/+/52407 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-18mb/google/guybrush/var/guybrush: Add GPIO override tableKarthikeyan Ramasubramanian
EN_SPKR is routed to SD pin in the ALC1019 speaker amplifier. The concerned pin has a voltage rating of 1.8V whereas the EN_SPKR GPIO has a voltage rating of 3.3 V. The schematics has been updated to bridge the gap. So enable the speaker amplifier by default and add a gpio override table to disable the speakers before board version 2. Also update the codec ACPI HID name for the kernel machine driver to probe the codec successfully. BUG=b:182960979 TEST=Build and boot to OS in guybrush. Ensure that the GPIO output state is high. Change-Id: I32b29bfae9bc94b5119b33a535d8bc825ef89445 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52355 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-18mb/google/guybrush: Enable AMD I2S Machine DriverKarthikeyan Ramasubramanian
Enable AMD I2S machine driver and configure the devicetree with HID information so that the machine driver ACPI objects can be passed to the kernel. BUG=b:182960979 TEST=Build and boot to OS in guybrush. Ensure that the ACPI objects for machine driver is populated. Change-Id: I8ed474d25273082d1e0742ba93746d97930deb19 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-18soc/intel/cnl and mainboards: Drop `cnl_configure_pads()`Furquan Shaikh
CB:31250 ("soc/intel/cannonlake: Configure GPIOs again after FSP-S is done") introduced a workaround in coreboot for `soc/intel/cannonlake` platforms to save and restore GPIO configuration performed by mainboard across call to FSP Silicon Init (FSP-S). This workaround was required because FSP-S was configuring GPIOs differently than mainboard resulting in boot and runtime issues because of misconfigured GPIOs. This issue has since been fixed in FSP (verified with FSP v1263 on hatch). However, there were still 4 boards in coreboot using `cnl_configure_pads()`. As part of RFC CB:50829, librem_cnl, clevo/cml-u and system76/lemp9 were tested to ensure that this workaround is no longer required. This change drops the workaround using `cnl_configure_pads()` and updates all mainboards to use `gpio_configure_pads()` instead. Signed-off-by: Furquan Shaikh <furquan@google.com> Tested-by: Angel Pons <th3fanbus@gmail.com> (Tested purism/librem_cnl) Tested-by: Michael Niewöhner <foss@mniewoehner.de> (Tested clevo/cml-u which is similar to system76/lemp9) Change-Id: I7a4facbf23fc81707cb111859600e641fde34fc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52248 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-18mb/google/guybrush/var/guybrush: Add FPMCU configrationIvy Jian
Enable CRFP in devicetree and configure GPIOs. BUG=b:182201937 BRANCH=None TEST=Boot into OS and confirm FPMCU is responding. Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: I7c56b0db193be6804d07c2f333445c2a1dbf9f59 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-16mb/google/guybrush: Enable backlight in the OSMartin Roth
Add ACPI code to enable the backlight when we enter the OS. BUG=b:184198808 TEST=Backlight enabled in the OS Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I3e0a6c06120ac5abf0a0d82494e03d9cf80c1f8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52113 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-16mb/google/zork: Configure HID over I2C related GPIO as level-triggeredVictor Ding
Both touchpads supported by zork use level-triggered wakeup signal. BRANCH=zork BUG=b:172846122,b:182911201 TEST=1. cros build-ap -b zork 2. both Synaptics and ELAN touchpads work fine on Vilboz 3. Wakeup source is correctly reported on Vilboz Signed-off-by: Victor Ding <victording@google.com> Change-Id: Icc2b5ad3bd434c9759a0fdfc121aa3c94f46630e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52367 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-16mb/google/zork: Configure IRQs as level triggered for ELAN touchpadVictor Ding
Based on the datasheet provided by ELAN, the /INT pin is "low active" and "indicates touchpad likes to send data to system(host) when low". The signal is level-triggered. BRANCH=zork BUG=b:172846122 TEST=cros build-ap -b zork Signed-off-by: Victor Ding <victording@google.com> Change-Id: I1f2182aaf483932304591ab14592f35214ea6efd Reviewed-on: https://review.coreboot.org/c/coreboot/+/52366 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-16mb/google/dedede/var/galith: support Audio AMP I2C/Auto modeFrankChu
support audio AMP selection with fw_config. BUG=b:185082705 BRANCH=dedede TEST=build pass Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Ieb169c69a6716082dd218d05479bca46bbc09a3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-16mb/google/dedede: Add AUDIO_AMP FW_CONFIG in devicetreeFrankChu
Add AUDIO_AMP ports bit field in devicetree. UNPROVISIONED 0 MAX98360 1 RT1015_I2C 2 RT1015P_AUTO 3 BUG=b:185082705 BRANCH=dedede TEST=build pass Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I54f1e44036857dc00df074c38fde0fa82e589320 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52317 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-16mb/google/dedede/var/storo:Add P-sensor for storoZanxi Chen
Modify GPIO_D22/D23/E11 configuration for P-sensor BUG=b:185214363 BRANCH=dedede TEST=built storo firmware and verified P-sensor function Change-Id: Ia2df1a227b04688a6b98384cd3a4e63023c0c1d9 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52315 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-16soc/amd/cezanne: Add uart controllers to chipset.cbIvy Jian
Add uart controller to chipset.cb and leave it off by default. Turn uart0 on for console for mainboards. BUG=none TEST=builds and boot into OS Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: Iaeb7fea4b92bd89331c7ae7c1c000f8d9961fe9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-04-16mb/google/brya: Configure TCSS OC pins for bryaMaulik V Vaghela
TCSS OC pins has not been correctly configured for brya. This patch fills the value from devicetree to correct the OC pins mapping BUG=b:184653645 BRANCH=None TEST=check if UPD value has been reflected correctly Change-Id: Ia21cdbf5768ad7516ea52bff7e247291a7d2ebd1 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-04-16mb/google/octopus: Add log for ssfc update codecEric Lai
Add log to show the codec has been disabled. BUG=b:185193926 TEST=cbmem -c | grep disabled, can find the codec name Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I8ce7e435ce73beb2a5cbf5883905554227b1989b Reviewed-on: https://review.coreboot.org/c/coreboot/+/52314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com>
2021-04-16mb/google/guybrush: Implement tis_plat_irq_statusRaul E Rangel
BUG=b:185397933 TEST=boot guybrush and no longer see tis_plat_irq_status warnings Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I9b67cb59221d4e355df8e8a2205e03ead7dba51f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-16mb/google/{guybrush,mancomb}: Add VBOOT_VBNV_OFFSETRaul E Rangel
This is the same as zork. BUG=b:184126844 TEST=Boot guybrush in developer mode and switch to normal mode. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib11c255ab7e937de334ecd18dc030006f7724275 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-16mb/google/guybrush: Sort VBOOT_EARLY_EC_SYNCRaul E Rangel
BUG=none TEST=none Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I658372d082a8276f15c7165fe4104de4613fe7d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-15mb/google/guybrush,mancomb: include soc/gpio.h in baseboard/gpio.hFelix Held
This include provides the GPIO_x definitions. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I12a0d95f79658f3852132876e92c389b715f3001 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52358 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-15mb/google/zork: move include to the files where it's usedFelix Held
platform_descriptors.h is unrelated to the contents of baseboard/gpio.h where it was included, so move the includes to the files where it is actually needed. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I94e59b5aac2df834d956106ac953eebfc5cf6921 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52357 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-15mb/google/zork: include amdblocks/gpio_defs.h in baseboard/gpio.hFelix Held
amdblocks/gpio_defs.h provides the definitions of GEVENT_x. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I65d398667e6777de6f1fa4e027cf1c75a3e235c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52356 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-15mb/google/kahlee: use defines for GEVENT numbersFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I353f0d241391dd1122c85866a74984b95ed54770 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52305 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-15herobrine: sc7280: Provide initial mainboard supportT Michael Turney
BUG=b:182963902 TEST=Validated on qualcomm sc7280 developement board Change-Id: I428cf1a461ee63215f5683abbfed90202d1b2a88 Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-04-15mb/google/guybrush,mancomb: use EC_SCI_GPI in espi_sci_sources structFelix Held
The board's ec.h file defined EC_SCI_GPI as GEVENT_24, so use that definition in all places in the mainboard code instead of a mix of the board specific define and the SoC's GEVENT number define. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I46525ed24e9993acd3d850959dd63761a690d5df Reviewed-on: https://review.coreboot.org/c/coreboot/+/52309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-15mb/google/brya: Add FPMCU power controlEric Lai
Enable CRFP power control in gpio table. RST needs to drive low before PWR enable. Since reset signal is asserted in bootblock, it results in FPMCU not working after a S3 resume. This is a known issue. BUG=b:181377402 BRANCH=None Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I8a8fae80c3cc186e0a097ab2007abb656f382cbd Reviewed-on: https://review.coreboot.org/c/coreboot/+/52185 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-15mb/google/dedede/var/kracko: Add LTE modem supportTony Huang
Add LTE modem to devicetree Configure GPIO control for LTE modem BUG=b:178092096 TEST=Built image and verified with command modem status Change-Id: Id8f483e1132a08500fbe950711cc84197ce40b12 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-15mb/google/dedede/var/sasukette: Enable Wifi SAR for sasuketteTao Xia
BUG=b:185084331 BRANCH=dedede TEST=enable CHROMEOS_WIFI_SAR in config of coreboot, emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage. Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: Ie982741cb7b328623cf27f41c31f819e8cdb7bc9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-15mb/google/zork: fine tune stamp_boost parameter for dirinbozKevin Chiu
The new discovery from Google & AMD, the value currently used STAPM Time Constant of 1640 is reducing real PPT TSP from the target 4.8W to 4.68W. Furthermore, when using the "default" STAPM Time Constant of 1400, the actual real PPT TSP becomes 4.89W. Operating at this default settings therefore uses a higher real PPT TSP, which results in a significant performance improvement. BUG=b:175364713,b:184902568 BRANCH=zork TEST=1. emerge-zork coreboot 2. run balance performance and skin temperature test => pass Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I9cf4d51f42fe250340bcb642db07796c9a480c34 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52312 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-15mb/google/zork: fine tune stamp_boost parameter for gumbozKevin Chiu
The new discovery from Google & AMD, the value currently used STAPM Time Constant of 1640 is reducing real PPT TSP from the target 4.8W to 4.68W. Furthermore, when using the "default" STAPM Time Constant of 1400, the actual real PPT TSP becomes 4.89W. Operating at this default settings therefore uses a higher real PPT TSP, which results in a significant performance improvement. BUG=b:184902568 BRANCH=zork TEST=1. emerge-zork coreboot 2. run balance performance and skin temperature test => pass Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I102c1c5f8215a6c5f7a4451f5731167c32e27c90 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52313 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-09 05:12:59 +0000