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Use acpigen_write_processor_cnot to implement notifications to the CPU.
Automatically generate \PPKG in SSDT.
Change-Id: Iecc54e94484f5f11e0ba8ef6d1d844276e484b4d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29886
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use acpigen_write_processor_cnot to implement notifications the CPU.
Generate PPKG in SSDT.
Change-Id: I126989e8737720f55f7ce113ff4e32bfe0f22620
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29885
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The reason for this code cleanup is the legacy
Google Purin board which isn't available anymore
and AFAIK never made it into the stores.
* Remove broadcom cygnus SoC support
* Remove /util/broadcom tool
* Remove Google Purin mainboard
* Remove MAINTAINERS entries
Change-Id: I148dd7eb0192d396cb69bc26c4062f88a764771a
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29905
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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According to aleena thermal testing to set STAPM values.
skin scalar for 80%.
time constant for 2500s.
power limit for 7.8w.
BUG=b:72979852
TEST=test build for thermal check.
Change-Id: I09f1c1052dd317969546ac7d2bbde14cc563c160
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/29795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Correct Ram_ID=0b0001 SPD Module Part Number to "H5ANAG6NAMR-UH" from "HMAA51S6AMR6N-UH".
BUG=b:120000816
BRANCH=master
TEST=mosys memory spd print all
Change-Id: I59d920498ff6b73e9e7b2887771ad6bc6c6c0b66
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/29873
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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This commit create a casta variant for Octopus. The initial settings
override the baseboard GPIO configuration for Touchscreen, LTE, Pen and
Trace modules.
BUG=b:119056117
BRANCH=None
TEST=None
Change-Id: I5d3f7df66981d84fb47a6aa248480ef53dfd90d0
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/29763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Implement HD Audio verb table for RealTek ALC 3204/3254 codec on google
sarien and arcada board.
BUG=b:119058355,119054586
TEST=Confirm audio play back is working on Sarien and Arcada board.
Change-Id: Icedbb510c7668d96c99c657091fc865f03bf7783
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/29484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
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This removes CEIL_DIV and div_round_up() altogether and
replace it by DIV_ROUND_UP defined in commonlib/helpers.h.
Change-Id: I9aabc3fbe7834834c92d6ba59ff0005986622a34
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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PMIC provides power features like auxadc, buck/ldo,
interrupt-controller..etc
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui
Change-Id: Ic247faf73517f6512f9c9a69ba0254c749d68d4c
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/29422
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The aleena board uses a display that's not compatible with current VBIOS.
A VBIOS specific for aleena has been merged into blobs, so modify Kconfig
so that it loads the new VBIOS when building aleena, but load original VBIOS
for all other boards under kahlee folder.
BUG=b:112618193
TEST=Build each board under kahlee, one at a time. After each build, opened
build/config.h and searched VGA_BIOS_FILE to verify that the string only
changed for aleena, all other boards remained with original string.
Change-Id: Iccd0853692680908d951edd142a2d8e13a561391
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/29870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: Ibdff50761a205d936b0ebe067f418be0a2051798
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hellsenberg <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: David Guckian
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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This change gets rid of bid0_override_table as part of clean up effort
to deprecate bid0. Additionally, it updates the touchscreen enable
GPIO in overridetree and gets rid of code in variant.c to update enable
gpio at runtime.
BUG=b:119885949
Change-Id: I527973747e7d81ec47997da57eeb15f38d3ac2fd
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/29787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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This change is to bump fsp_memory_mainboard_version in order to
trigger MRC full training
BUG=b:119481870
CQ-DEPEND=CL:*716558
BRANCH=reef, coral
TEST=make sure MRC retraining is triggered and the MRC cache is
updated to newer version.
Change-Id: I92463045f7a808fb25aaa7a2d5f6fcde36dfb458
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/29647
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:116191230
BRANCH=None
TEST=1. verified boot beep support at depthcharge.
Change-Id: Ia4843185dd79a35476c4f0fc0666ebaf3773db4c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/29753
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:112282079
BRANCH=None
TEST=1. run evtest and make sure trackpad shows up in list
2. Able to wake system from S3 using trackpad
Change-Id: I86d6b7815147d558065611604363bb607119c154
Signed-off-by: Shelley Chen <shchen@google.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/29752
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:112332115
BRANCH=None
TEST=ensure at bootup that /sys/devices/pnp0/00:05 exists
and driver link to '../../../bus/pnp/drivers/i8042 kbd'
Also, can now see keyboard in evtest.
Change-Id: I2a6b382be84bc5201beafe21ff8ddee3738bc5c2
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/29750
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch includes support for both ICL ES0 and ES1 samples.
Detailed document is here: Documentation/soc/intel/icelake/iceLake_coreboot_development.md
TEST=Able to build and boot dragonegg.
Change-Id: I2cc269cb0050bf5b031f48cfe114485c55ab8fa9
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/29749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This change adds ACPI properties for GTCH7503 device.
BUG=b:119169362
BRANCH=firmware-nami-10775.B
TEST=Verify touchscreen works with this change
Change-Id: I26e16b7e118121b3dd9a88c76d04898b97753df0
Signed-off-by: Crystal Lin <crystal_lin@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/29768
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The SD cardreader is on USB bus, not on SDIO/SDXC.
BUG=b:119798840
BRANCH=master
TEST=Compiles successfully and boot on DUT.
Change-Id: I8015fe35a4ff79469b5781942f588c3e1b88b751
Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/29765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Set GPIO GPP_B4 to high to enable touchscreen wakeup.
BUG=b:119594783
BRANCH=master
TEST=DUT can wake up with touchscreen.
Change-Id: If0c9493dec367c7813047c7994cc83537aaef141
Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/29769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The touchpad and touch-panel CLK frequency should be smaller
than 400 kHz which described in spec.
Overwrite i2c speed parameters by overridetree.cb
BUG=b:119540449
BRANCH=master
TEST=emerge-octopus coreboot chromeos-bootimage
flash bios and check the touchpad i2c frequency meets the spec.
Change-Id: I32c3e1bbfc2cdf39e9b7865a69996e54346d5f93
Signed-off-by: Carl Yang <carl_yang@asus.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/29694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This change deprecates boards with id < 2. It updates touchscreen enable
GPIO in overridetree and gets rid of variant.c to update enable GPIO at
runtime. Additionally, it configures old enable GPIO as NC.
BUG=b:119885949
Change-Id: I42fb7ef90e421118a8fdfa0d343d0bcf4a9bc087
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/29786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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This change gets rid of bid0_override_table as part of clean up effort
to deprecate bid0. Additionally, it updates the touchscreen enable
GPIO in overridetree and gets rid of variant.c to update enable gpio at
runtime.
BUG=b:119885949
Change-Id: If14abb324d9422720ca4d0f0859e092319d454ee
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/29785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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This change updates the configuration of GPIO_178 to be active low as
per latest revision on different octopus variants. This effectively:
1. Gets rid of early_gpio_table in different variants -- phaser, meep,
fleex, bobba.
2. Deprecates board id < 2 for bobba, board id < 1 for fleex and
phaser.
3. Adds special early_gpio_table in yorp which has GPIO_178 as an
active high signal.
BUG=b:119885949
Change-Id: I024199a8f1f96db57f8fa60c4d265789cd3a0493
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/29784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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This change configures all the pads going to debug header as not
connected.
BUG=b:111569213
BRANCH=None
TEST=None
Change-Id: Ie3ffdbf6ad9b1682deaada91b5c225b4c8dd035b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/29780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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Change the board id detection to support rev5, since the 2T mode still
needed in DVT build.
BUG=b:116082728
TEST=verify by ODM.
Change-Id: Ibb4cc1fd2bb54984cb7a8856ed7b9f49b78eddce
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/29779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Field 'OEMID' & "OEM Table ID" are related to DSDT table
not to mainboard.
So use macro to set them respectvely to "COREv4" and
"COREBOOT".
Change-Id: I060e07a730e721df4a86128ee89bfe168c69f31e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: David Guckian
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We need to default this to low so the speakers don't activate in S3.
BUG=b:118248953
TEST=Used a scope to look at the line and made sure depthcharge still
beeps.
Change-Id: I70d2f4a3261d212b62e784fa7414e45b1d575612
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/29783
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Main objective for this change is to export the bluetooth reset
gpio to the kernel for use in an rf-kill operation.
To do so, we enable USB acpi and define all of the USB2 devices,
which includes bluetooth's reset gpio information.
This change produces the following nodes in the SSDT :
Scope (\_SB.PCI0.XHCI.RHUB.HS01)
{
Name (_DDN, "USB Type C Port 1") // _DDN: DOS Device Name
Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities
{
0xFF,
0x09,
Zero,
Zero
})
Name (_PLD, ToPLD (
PLD_Revision = 0x2,
PLD_IgnoreColor = 0x1,
PLD_Red = 0x0,
PLD_Green = 0x0,
PLD_Blue = 0x0,
PLD_Width = 0x0,
PLD_Height = 0x0,
PLD_UserVisible = 0x1,
PLD_Dock = 0x0,
PLD_Lid = 0x0,
PLD_Panel = "UNKNOWN",
PLD_VerticalPosition = "CENTER",
PLD_HorizontalPosition = "CENTER",
PLD_Shape = "OVAL",
PLD_GroupOrientation = 0x0,
PLD_GroupToken = 0x0,
PLD_GroupPosition = 0x0,
PLD_Bay = 0x0,
PLD_Ejectable = 0x0,
PLD_EjectRequired = 0x0,
PLD_CabinetNumber = 0x0,
PLD_CardCageNumber = 0x0,
PLD_Reference = 0x0,
PLD_Rotation = 0x0,
PLD_Order = 0x0,
PLD_VerticalOffset = 0x0,
PLD_HorizontalOffset = 0x0)
) // _PLD: Physical Location of Device
}
Scope (\_SB.PCI0.XHCI.RHUB.HS03)
{
Name (_DDN, "Bluetooth") // _DDN: DOS Device Name
Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities
{
0xFF,
0xFF,
Zero,
Zero
})
Name (_PLD, ToPLD (
PLD_Revision = 0x2,
PLD_IgnoreColor = 0x1,
PLD_Red = 0x0,
PLD_Green = 0x0,
PLD_Blue = 0x0,
PLD_Width = 0x0,
PLD_Height = 0x0,
PLD_UserVisible = 0x0,
PLD_Dock = 0x0,
PLD_Lid = 0x0,
PLD_Panel = "UNKNOWN",
PLD_VerticalPosition = "CENTER",
PLD_HorizontalPosition = "CENTER",
PLD_Shape = "UNKNOWN",
PLD_GroupOrientation = 0x0,
PLD_GroupToken = 0x0,
PLD_GroupPosition = 0x0,
PLD_Bay = 0x0,
PLD_Ejectable = 0x0,
PLD_EjectRequired = 0x0,
PLD_CabinetNumber = 0x0,
PLD_CardCageNumber = 0x0,
PLD_Reference = 0x0,
PLD_Rotation = 0x0,
PLD_Order = 0x0,
PLD_VerticalOffset = 0x0,
PLD_HorizontalOffset = 0x0)
) // _PLD: Physical Location of Device
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly,
"\\_SB.PCI0.GPIO", 0x00, ResourceConsumer, ,
)
{ // Pin list
0x0062
}
})
Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
Package (0x01)
{
Package (0x02)
{
"reset-gpio",
Package (0x04)
{
\_SB.PCI0.XHCI.RHUB.HS03,
Zero,
Zero,
One
}
}
}
})
}
Scope (\_SB.PCI0.XHCI.RHUB.HS05)
{
Name (_DDN, "USB Type C Port 2") // _DDN: DOS Device Name
Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities
{
0xFF,
0x09,
Zero,
Zero
})
Name (_PLD, ToPLD (
PLD_Revision = 0x2,
PLD_IgnoreColor = 0x1,
PLD_Red = 0x0,
PLD_Green = 0x0,
PLD_Blue = 0x0,
PLD_Width = 0x0,
PLD_Height = 0x0,
PLD_UserVisible = 0x1,
PLD_Dock = 0x0,
PLD_Lid = 0x0,
PLD_Panel = "UNKNOWN",
PLD_VerticalPosition = "CENTER",
PLD_HorizontalPosition = "CENTER",
PLD_Shape = "OVAL",
PLD_GroupOrientation = 0x0,
PLD_GroupToken = 0x0,
PLD_GroupPosition = 0x0,
PLD_Bay = 0x0,
PLD_Ejectable = 0x0,
PLD_EjectRequired = 0x0,
PLD_CabinetNumber = 0x0,
PLD_CardCageNumber = 0x0,
PLD_Reference = 0x0,
PLD_Rotation = 0x0,
PLD_Order = 0x0,
PLD_VerticalOffset = 0x0,
PLD_HorizontalOffset = 0x0)
) // _PLD: Physical Location of Device
}
Scope (\_SB.PCI0.XHCI.RHUB.HS07)
{
Name (_DDN, "POGO") // _DDN: DOS Device Name
Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities
{
0xFF,
0xFF,
Zero,
Zero
})
Name (_PLD, ToPLD (
PLD_Revision = 0x2,
PLD_IgnoreColor = 0x1,
PLD_Red = 0x0,
PLD_Green = 0x0,
PLD_Blue = 0x0,
PLD_Width = 0x0,
PLD_Height = 0x0,
PLD_UserVisible = 0x0,
PLD_Dock = 0x0,
PLD_Lid = 0x0,
PLD_Panel = "UNKNOWN",
PLD_VerticalPosition = "CENTER",
PLD_HorizontalPosition = "CENTER",
PLD_Shape = "UNKNOWN",
PLD_GroupOrientation = 0x0,
PLD_GroupToken = 0x0,
PLD_GroupPosition = 0x0,
PLD_Bay = 0x0,
PLD_Ejectable = 0x0,
PLD_EjectRequired = 0x0,
PLD_CabinetNumber = 0x0,
PLD_CardCageNumber = 0x0,
PLD_Reference = 0x0,
PLD_Rotation = 0x0,
PLD_Order = 0x0,
PLD_VerticalOffset = 0x0,
PLD_HorizontalOffset = 0x0)
) // _PLD: Physical Location of Device
}
BUG=b:119275094
TEST=build and flash to nocturne, log into nocturne and
'cat /sys/firmware/acpi/tables/SSDT > /tmp/ssdt.dml', copy
that ssdt.dsml to /tmp/ssdt.dml on host machine,
'iasl -d /tmp/ssdt.dml', then verify that "reset gpio"
shows up in the HS03 node's _DSD package in the table.
Change-Id: I65d9b580fd69fd0a2c84f14b78a8e8b5e9217b16
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/29622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rajat Jain <rajatja@google.com>
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We are seeing problems (interrupt storm) with using the same gpio for
FP MCU wake and irq signals. Reverting back to using separate gpios
for wake and irq until we resolve the issue.
BUG=b:119447525, b:115706071
BRANCH=Nami
TEST=Run powerd_dbus_suspend from kernel and make sure see DUT drop
into S0ix in the EC console. Also, unlock from lock screen with
fingerprint.
Change-Id: Id7987f28526256808b8ed49e66f66298f7cdbcee
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/29665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Vincent Wang <vwang@google.com>
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The dependencies of CONSOLE_SERIAL and DRIVERS_UART were somehow
backwards. Fix that. Now, CONSOLE_SERIAL depends on DRIVERS_UART,
because it's using its interface. The individual UART drivers
select DRIVERS_UART, because they implement the interface and
depend on the common UART code.
Some guards had to be fixed (using CONSOLE_SERIAL now instead of
DRIVERS_UART). Some other guards that were only about compilation
of units were removed. We want to build test as much as possible,
right?
Change-Id: I0ea73a8909f07202b23c88db93df74cf9dc8abf9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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DSDT revision is =1 for ACPI v1 and =2 for greater ACPI version.
This will cause the AML interpreter to use 32-bit integers and math
if the version is 1, and 64-bit if the version is >=2.
Current spec version is 2 for ACPI 6.2-a.
Change-Id: I77372882d5c77b7ed52dcdd88028403df6f6fa7f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29626
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update passive temperature threshold value from 50C to 52C and
critical temperature threshold from 90C to 80C for TSR1 sensor.
BUG=b:79779737
TEST=Build and verified on Bobba/Bobba360/Sparky/Sparky360 boards
Change-Id: Iffef8afe0f1c6c80a6ae8ecb831aaf749443980e
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/29264
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I44f27405fc8ccbe54c7d19b70327da866390a156
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/28603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
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This change adds ACPI properties for WDT8752A device.
BUG=b:117174180
BRANCH=master
TEST=Verify touchscreen on delan works with this change
Change-Id: Id1484a482de6282c97f3aac329f217bbcb7dbd18
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
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Change-Id: I85cf93e30606bc7838852bd300a369e79370629a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Needs to increase ROPmax to 80W (includes both panel and audio),
hence the Pmax = 71W (PL4) + 80W (ROPmax) = 151W.
BUG=b:119644629
BRANCH=master
TEST=USE=fw_debug emerge-kalista chromeos-mrc coreboot chromeos-bootimage
& ensure the Pmax value is passed to FSP-S.
Change-Id: I504ff66a218bf4e385270c2cb385a83dca312a81
Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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GPP_D6 needs to be inverted to enter S0ix because FPMCU_INT_L is
active low. Keeps device awake otherwise.
BUG=b:119447525, b:115706071
BRANCH=Nami
TEST=Run powerd_dbus_suspend from kernel and make sure see DUT drop into
S0ix in the EC console.
Change-Id: Iad5df124e2439bbdc078d6a33f8d0510d25ecf6f
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/29650
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Setting sku_id() is not enough to get a value to show up in the SMBIOS
tables, it also needs to be returned as a string for the table creation
to consume. This change defines the smbios_mainboard_sku() function
and returns a string constant of "sku#" as expected.
Change-Id: I03013bab89d53d1eba969c6ffb7e95fcbb315a81
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Trent Begin <tbegin@google.com>
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Change-Id: I49554d13f1b6371b85a58cc1263608ad9e99130e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
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Change tcc offset from 0 to 10 degree celsius for bobba.
BUG=b:118099582
TEST=Cross verified the value using TAT UI.
Change-Id: I68527c27635844f4edb0dda5f6018589d7bae297
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/29636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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GPIO's that use GPI_APIC setting with DEEP causes an IRQ storm after
S3 resume. GPIOs that fire IRQs via IOAPIC need to get their logic
reset over PLTRST to prevent IRQ storm after S3 resume and hence
configuring GPP_F10 (HP_IRQ_GPIO) to use PLTRST.
BUG=none
TEST=none
Change-Id: Idc6c42cb4dc6e8eb368d605c83f584f4c69077dc
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/29540
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I89e03b6def5c78415bf73baba55941953a70d8de
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29302
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Iab0bd1c5482331a0c048a05ab806bf5c4dbda780
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29303
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The function `acpi_fill_fadt()` is based on that of sb/intel/bd82x6x.
Tested on an ASRock H81M-HDS and a Google Peppy board, both using Linux
4.9 with `acpi=strict`. No ACPI errors or warnings appear in the kernel
log. System reset, poweroff, and S3 suspend/resume continue to work.
General improvements
--------------------
- `fadt->preferred_pm_profile` is set based on the value of
`CONFIG_SYSTEM_TYPE_LAPTOP` instead of being hardcoded.
- Constants are used instead of magic values in more locations.
- `fadt->gpe0_blk`, `fadt->gpe0_blk_len`, and `fadt->x_gpe0_blk` are set
appropriately depending on whether the system uses Lynx Point LP or
not.
- Boards can indicate docking support in the FADT via the devicetree.
Changes to existing Lynx Point boards
-------------------------------------
- `header->asl_compiler_revision` changes from 1 to 0.
- `fadt->model` is left at 0 instead of being set to 1. This field is
only needed for ACPI 1.0 compatibility.
- `fadt->flush_size` and `fadt->flush_stride` are set to 0. This is
because their values are ignored, since `ACPI_FADT_WBINVD` is set in
`fadt->flags`.
- `fadt->duty_offset` is set to 0 instead of 1. None of the existing
boards indicate support for changing the processor duty cycle (as
`fadt->duty_width` is set to 0), so `fadt->duty_offset` does not
currently need to be set.
- Access sizes of registers are set.
- On mb/intel/baskingridge, the pmbase is now read using the common
function `get_pmbase()` instead of `pci_read_config16(...)`.
- On mb/intel/baskingridge, the value of `fadt->x_gpe0_blk.bit_width`
changes from 64 to 128. The correct value should be 128 (bits), to
match `fadt->gpe0_blk_len`, which is set to 16 (bytes).
- On Lynx Point LP systems, the unused extended address
`fadt->x_gpe0_blk` sets its address space ID to be consistent with
other unused extended addresses. Such a change should not alter the
interpretation of the registers as being unused. Why not set them all
to zero? Simply because the existing practice, in both coreboot and
some other vendors' firmware, has them set in such a case.
A diff of the FADT from a Google Peppy board is below:
--- pre/facp.dsl 2018-10-30 20:14:52.676570798 +1300
+++ post/facp.dsl 2018-10-30 20:15:06.904381436 +1300
@@ -1,179 +1,179 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20180810 (64-bit version)
* Copyright (c) 2000 - 2018 Intel Corporation
*
- * Disassembly of facp.dat, Tue Oct 30 20:14:52 2018
+ * Disassembly of facp.dat, Tue Oct 30 20:15:06 2018
*
* ACPI Data Table [FACP]
*
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
*/
[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
[004h 0004 4] Table Length : 000000F4
[008h 0008 1] Revision : 04
-[009h 0009 1] Checksum : 61
+[009h 0009 1] Checksum : 6E
[00Ah 0010 6] Oem ID : "CORE "
[010h 0016 8] Oem Table ID : "COREBOOT"
[018h 0024 4] Oem Revision : 00000000
[01Ch 0028 4] Asl Compiler ID : "CORE"
-[020h 0032 4] Asl Compiler Revision : 00000001
+[020h 0032 4] Asl Compiler Revision : 00000000
[024h 0036 4] FACS Address : 7BF46240
[028h 0040 4] DSDT Address : 7BF46280
-[02Ch 0044 1] Model : 01
+[02Ch 0044 1] Model : 00
[02Dh 0045 1] PM Profile : 02 [Mobile]
[02Eh 0046 2] SCI Interrupt : 0009
[030h 0048 4] SMI Command Port : 000000B2
[034h 0052 1] ACPI Enable Value : E1
[035h 0053 1] ACPI Disable Value : 1E
[036h 0054 1] S4BIOS Command : 00
[037h 0055 1] P-State Control : 00
[038h 0056 4] PM1A Event Block Address : 00001000
[03Ch 0060 4] PM1B Event Block Address : 00000000
[040h 0064 4] PM1A Control Block Address : 00001004
[044h 0068 4] PM1B Control Block Address : 00000000
[048h 0072 4] PM2 Control Block Address : 00001050
[04Ch 0076 4] PM Timer Block Address : 00001008
[050h 0080 4] GPE0 Block Address : 00001080
[054h 0084 4] GPE1 Block Address : 00000000
[058h 0088 1] PM1 Event Block Length : 04
[059h 0089 1] PM1 Control Block Length : 02
[05Ah 0090 1] PM2 Control Block Length : 01
[05Bh 0091 1] PM Timer Block Length : 04
[05Ch 0092 1] GPE0 Block Length : 20
[05Dh 0093 1] GPE1 Block Length : 00
[05Eh 0094 1] GPE1 Base Offset : 00
[05Fh 0095 1] _CST Support : 00
[060h 0096 2] C2 Latency : 0001
[062h 0098 2] C3 Latency : 0057
-[064h 0100 2] CPU Cache Size : 0400
-[066h 0102 2] Cache Flush Stride : 0010
-[068h 0104 1] Duty Cycle Offset : 01
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
[069h 0105 1] Duty Cycle Width : 00
[06Ah 0106 1] RTC Day Alarm Index : 0D
[06Bh 0107 1] RTC Month Alarm Index : 00
[06Ch 0108 1] RTC Century Index : 00
[06Dh 0109 2] Boot Flags (decoded below) : 0003
Legacy Devices Supported (V2) : 1
8042 Present on ports 60/64 (V2) : 1
VGA Not Present (V4) : 0
MSI Not Supported (V4) : 0
PCIe ASPM Not Supported (V4) : 0
CMOS RTC Not Present (V5) : 0
[06Fh 0111 1] Reserved : 00
[070h 0112 4] Flags (decoded below) : 00008CAD
WBINVD instruction is operational (V1) : 1
WBINVD flushes all caches (V1) : 0
All CPUs support C1 (V1) : 1
C2 works on MP system (V1) : 1
Control Method Power Button (V1) : 0
Control Method Sleep Button (V1) : 1
RTC wake not in fixed reg space (V1) : 0
RTC can wake system from S4 (V1) : 1
32-bit PM Timer (V1) : 0
Docking Supported (V1) : 0
Reset Register Supported (V2) : 1
Sealed Case (V3) : 1
Headless - No Video (V3) : 0
Use native instr after SLP_TYPx (V3) : 0
PCIEXP_WAK Bits Supported (V4) : 0
Use Platform Timer (V4) : 1
RTC_STS valid on S4 wake (V4) : 0
Remote Power-on capable (V4) : 0
Use APIC Cluster Model (V4) : 0
Use APIC Physical Destination Mode (V4) : 0
Hardware Reduced (V5) : 0
Low Power S0 Idle (V5) : 0
[074h 0116 12] Reset Register : [Generic Address Structure]
[074h 0116 1] Space ID : 01 [SystemIO]
[075h 0117 1] Bit Width : 08
[076h 0118 1] Bit Offset : 00
-[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
+[077h 0119 1] Encoded Access Width : 01 [Byte Access:8]
[078h 0120 8] Address : 0000000000000CF9
[080h 0128 1] Value to cause reset : 06
[081h 0129 2] ARM Flags (decoded below) : 0000
PSCI Compliant : 0
Must use HVC for PSCI : 0
[083h 0131 1] FADT Minor Revision : 00
[084h 0132 8] FACS Address : 000000007BF46240
[08Ch 0140 8] DSDT Address : 000000007BF46280
[094h 0148 12] PM1A Event Block : [Generic Address Structure]
[094h 0148 1] Space ID : 01 [SystemIO]
[095h 0149 1] Bit Width : 20
[096h 0150 1] Bit Offset : 00
-[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
+[097h 0151 1] Encoded Access Width : 02 [Word Access:16]
[098h 0152 8] Address : 0000000000001000
[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
[0A0h 0160 1] Space ID : 01 [SystemIO]
[0A1h 0161 1] Bit Width : 00
[0A2h 0162 1] Bit Offset : 00
[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
[0A4h 0164 8] Address : 0000000000000000
[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
[0ACh 0172 1] Space ID : 01 [SystemIO]
[0ADh 0173 1] Bit Width : 10
[0AEh 0174 1] Bit Offset : 00
-[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0AFh 0175 1] Encoded Access Width : 02 [Word Access:16]
[0B0h 0176 8] Address : 0000000000001004
[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
[0B8h 0184 1] Space ID : 01 [SystemIO]
[0B9h 0185 1] Bit Width : 00
[0BAh 0186 1] Bit Offset : 00
[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
[0BCh 0188 8] Address : 0000000000000000
[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
[0C4h 0196 1] Space ID : 01 [SystemIO]
[0C5h 0197 1] Bit Width : 08
[0C6h 0198 1] Bit Offset : 00
-[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0C7h 0199 1] Encoded Access Width : 01 [Byte Access:8]
[0C8h 0200 8] Address : 0000000000001050
[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
[0D0h 0208 1] Space ID : 01 [SystemIO]
[0D1h 0209 1] Bit Width : 20
[0D2h 0210 1] Bit Offset : 00
-[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0D3h 0211 1] Encoded Access Width : 03 [DWord Access:32]
[0D4h 0212 8] Address : 0000000000001008
[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
-[0DCh 0220 1] Space ID : 00 [SystemMemory]
+[0DCh 0220 1] Space ID : 01 [SystemIO]
[0DDh 0221 1] Bit Width : 00
[0DEh 0222 1] Bit Offset : 00
[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
[0E0h 0224 8] Address : 0000000000000000
[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
[0E8h 0232 1] Space ID : 01 [SystemIO]
[0E9h 0233 1] Bit Width : 00
[0EAh 0234 1] Bit Offset : 00
[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
[0ECh 0236 8] Address : 0000000000000000
Change-Id: I9638bb5ff998518eb750e3e7e85b51cdaf1f070e
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29387
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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With this change, coreboot thinks we're running at 1MHz:
DW I2C bus 2 at 0xd1133000 (1000 KHz)
Elan eKT3644 IC Specification (trackpad) requires:
Low Time larger than 500ns (61 * 8.3ns = 506ns).
High Time larger than 260ns (32 * 8.3ns = 265ns),
Data Hold_time larger than 0ns.
Start Condition Hold time larger than 250ns.
Rise/Fall time of less than 120ns.
HCNT controls both High Time and Start Condition Hold time.
LCNT controls Low Time.
SDA_HOLD controls Data Hold Time.
P2 Atlas "Rise time" is 90ns and "Fall time" is 32ns and tuned
using resistors on the board and must be considered when
adjusting any of the parameters since these times are all measured
at 30 or 70% of base and peak voltages (0v/1.8v).
The eKT3644 requirements are met with LCNT=69, HCNT=33, SDA_HOLD=20
which yields the SCL at around 950KHz - suboptimal but compliant.
Lower LCNT or HCNT results in "lost arbitration" errors or not complying
with eKT3644 requirements.
Verified by gaggery.tsai@intel.corp-partner.google.com.
Scope shots posted here:
https://b.corp.google.com/issues/78601949#comment177
BUG=b:78601949
BRANCH=none
TEST=Farzam provided test points on track pad for SCL/SDA/GND.
Waveforms measured with oscilloscope and screen shots attached
to bug (comment #177, #155, #100).
Operate trackpad/touchscreen
Review dmesg (kernel) output for correct speed, parameters, and
no errors (e.g. "lost arbitration" or "host controller timeout")
Change-Id: Iaf42ba7b8818b7cd9c8dcc657823dac705659d38
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Signed-off-by: Grant Grundler <grundler@chromium.org>
Tested-by: gaggery.tsai@intel.corp-partner.google.com
Tested-by: grundler@chromium.org
Reviewed-on: https://review.coreboot.org/29553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com>
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Change-Id: I4d0df30255d006c0399dde1b3ba8ee513d98dc0a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Only input from the BJ port is wired to VSYS on Kalista. VBUS from
USB-C is for output only. In other words, Kalista is a source only
device from a USB/PD perspective.
This patch disables EC-EFS, which would be needed for the EC to jump
to RW to get PD power before the AP boots. Kalista will be always
supplied enough power to boot the AP through the BJ port.
CQ-DEPEND=CL:1330171
BUG=b:118386511
BRANCH=none
TEST=Boot Fizz. Verify normal boot, soft sync, recovery mode work.
Change-Id: Icd18662ae1e76f35eb9bcd521b1951aacc713252
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/29564
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I801849fb31fe6958e3d9510da50e2e2dd351a98d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I252a1cd77bf647477edb7dddadb7e527de872439
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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