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path: root/src/mainboard/google
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2021-01-11mb/google/dedede/var/magolor: Remove the unused touch controllerRen Kuo
Remove unused touch controller - Goodix BUG=None BRANCH=dedede TEST=build firmware Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Change-Id: I2a01666bc1e353e21ddf961a0eb721a0cb4013db Reviewed-on: https://review.coreboot.org/c/coreboot/+/49221 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10mb/google/cyan: Move board_id() to mainboard_fill_gnvs()Kyösti Mälkki
Only a google/cyan variant evalutes BDID in ASL. Change-Id: I3d839333333b4762ae5350734c85471a3c12838a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49003 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10soc/intel: Replace acpi_init_gnvs()Kyösti Mälkki
Rename these to soc_fill_gnvs() and move the callsite away from mb/. Change-Id: I760c36f65c6122103f2be98fc11ee13832c2772e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48716 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10mb/x/acpi_tables: Rename to mainboard_fill_gnvs()Kyösti Mälkki
Rename acpi_create_gnvs() functions under mb/ to reflect their changed functionality. Remove now empty mb/acpi_tables.c files. Change-Id: Ia366867ef73d1ade9805dc29b8e14b3073f44f60 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48707 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10mb/x/acpi_tables: Move EC_RW detectionKyösti Mälkki
These boards without ChromeEC do not set ACTIVE_EC_RW flag as part of the gnvs_assign_chromeos() function. Create abstraction to avoid <vendorcode/chromeos/x> include. Change-Id: Ic6029e1807fcfe7dd2c766ce8221e347b6b096f9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48777 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10ACPI: Drop redundant ChromeOS setup for GNVSKyösti Mälkki
Already done in common gnvs_get_or_create() implementation once gnvs_chromeos_ptr() is defined for platforms. Change-Id: I90fa2bc28ae76da734b3f88be057435aed9fe374 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48703 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-09mb/google/parrot: Replace while-loop with do-whileFelix Singer
Fixes linter error complaining about trailing semicolon. Change-Id: I3f74f25cb2e3edcdd509abd86d80098241c05741 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-09mb/google/parrot: Let else statement follow closing braceFelix Singer
Fixes a linter error. Change-Id: I1302e32b0d52e37d9cb4503128edc7d1df1c3bd8 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-09mb/google/parrot: Get rid of hard-coded function names in printksFelix Singer
Instead of hard-coding function names in strings, use the __func__ constant for better maintainability. Change-Id: I151560cd5a135e00f494eda3f9d3b592ee9d984a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-09mb/google/parrot: Fix spacing issuesFelix Singer
Add a space after each comma to fix linter issues. Change-Id: I5533c4fc7aa0e986da4350ec56b84903b3111a07 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-08mb/google/volteer: Configure Delbin USB2 ports for Type CJohn Zhao
Two USB2 ports 4 and 9 are assigned to type C connectors on Delbin board. This update configures these USB2 ports for Type C which will allow USB2 port reset message upstream from PCH to CPU to recover a USB3 device that downgraded to USB2 to upgrade back to USB3. BUG=b:176575892 TEST=Booted to kernel on Delbin board and verified usb2 port reset message enable bits through pch xhci_mmio_base + R_XHCI_MEM_U2PRM_U2PRDE where the offset register R_XHCI_MEM_U2PRM_U2PRDE has value 0x92f4. Validated various USB3 devices enumeration. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Idb3ce949e1ecf3adc7615e0af79a38a0cc9be18f Reviewed-on: https://review.coreboot.org/c/coreboot/+/49202 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08mb/google/octopus: add audio codec into SSFC support for BobbaMarco Chen
BUG=b:174118027 BRANCH=octopus TEST=adjust SSFC value of CBI to select RT5682 or DA7219 then check whether device tree is updated correspondingly by disabling unselected one. Signed-off-by: Marco Chen <marcochen@google.com> Change-Id: Id37c4c5716ade0851cfcb24e12b390841e633ac9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
2021-01-08mb/google/asurada: Support audioTzung-Bi Shih
- Turns audio-related things power on. - Selects I2S pin-muxing. - Exposes GPIO "speaker enable" for switching on and off. BUG=b:176856418 Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: If595657bbddad85bc9a154b3648bae1190cb00b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-08mb/google/dedede/var/sasuke: Add internal USB camera supportSeunghwan Kim
This change adds internal USB camera into devicetree for sasuke BUG=None TEST=Built and checked camera device existence with lsusb Change-Id: I51b9bb174205d984f1d060afd603f1d087095645 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49162 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08mb/google/dedede/var/sasuke: Enable ELAN touchpadSeunghwan Kim
This change adds ELAN touchpad into devicetree for sasuke. BUG=None TEST=Built and verified touchpad function Change-Id: If9c25f23ee1c0e88382fff036f77a6753775b81e Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-08mb/google/dedede/var/sasuke: Enable audio featureSeunghwan Kim
This change adds DA7219 audio codec and MAX98360A amplifier for sasuke. BUG=None TEST= Built and heared speaker sound on OS Change-Id: Ib48eb74fbfe171d46d0d23859057ba169b56bde2 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-08mb/google/dedede/var/sasuke: Configure GPIO NC padsSeunghwan Kim
Configure GPIO NC pads for sasuke. BUG=b:172104731 TEST="FW_NAME=sasuke emerge-dedede coreboot" Change-Id: I3bf8f97708536010da82402ea3d49e387e732d61 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-08mb/google/volteer: Update copano device treehao_chou
Update device tree override to match schematics. BUG=b:175896481 BRANCH=firmware-volteer-13672.B TEST=emerge-volteer coreboot Signed-off-by: hao_chou <hao_chou@pegatron.corp-partner.google.com> Change-Id: I1fb006d750bb2d670885ec8ccc627436c5078072 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-08mb/google/volteer: Add GPIO to copano supporthao_chou
Add support for gpio driver for copano BUG=b:175896481 BRANCH=firmware-volteer-13672.B TEST=emerge-volteer coreboot Signed-off-by: hao_chou <hao_chou@pegatron.corp-partner.google.com> Change-Id: I1e0f730c9865ed77c7071245b071315a9c6ea4c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48951 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08mb/google/volteer: Copano: Update SPD tablehao_chou
Add memory table to "mem_list_variant.txt", and command to generate files: go run ./util/spd_tools/lp4x/gen_part_id.go src/soc/intel/tigerlake/spd src/mainboard/google/volteer/variants/copano/memory/ src/mainboard/google/volteer/variants/copano/memory/mem_list_variant.txt DRAM Part Name ID to assign MT53D512M64D4NW-046 WT:F 0 (0000) H9HCNNNCRMBLPR-NEE 0 (0000) MT53D1G64D4NW-046 WT:A 1 (0001) H9HCNNNFBMBLPR-NEE 2 (0010) BUG=b:175896481 BRANCH=firmware-volteer-13672.B TEST=emerge-volteer coreboot Signed-off-by: hao_chou <hao_chou@pegatron.corp-partner.google.com> Change-Id: I2ace17e8fff12d3f5de15a35f609265d8b6ed6b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48948 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08mb/google/zork: Unmap FCH IO-APIC PCI interruptsRaul E Rangel
Now that the _PRT generates a GNB IO-APIC routing table we no longer need to route the PCI interrupts through the FCH IO-APIC. This change unmaps the IRQs since they are no longer used. BUG=b:170595019 TEST=Boot with `pci=nomsi amd_iommu=off` and verify /proc/interrupts Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I3467934bfcac14311505bec49a12652490554e6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/48669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-08mb/google/dedede: Enable "FastPkgCRampDisable" upd for noise mitigationMaulik V Vaghela
As part of acoustic noise mitigation calibration, we need to enable FastPkgCRampDisable upd along with slew rate = 1. This values has been derived based on noise calibration done. Please refer document 575216 for procedure. BUG=None BRANCH=dedede TEST=correct value has been programmed and slew rate measurement is correct on scope. Change-Id: Ie42c8ab647ff42fa043b6f717a9834f9b9c551f6 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Evan Green <evgreen@chromium.org>
2021-01-07mb/google/zork: Decrease stamp_boost parameter for dirinbozKevin Chiu
Original Stamp_boost parameter will cause boost time over 2500sec(3960sec) To pass balance performance and skin temperature test, decrease stamp_boost: 2500 -> 1640 BUG=b:175364713 TEST=1. emerge-zork coreboot 2. run balance performance and skin temperature test Change-Id: I44f086af6b5dd552efd2bd1ef4db0d69b652826d Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-01-07mb/google/dedede: Add support for charger throttlingSumeet Pawnikar
Add charger current throttling support for dedede baseboard BUG=None BRANCH=None TEST=Built and tested on boten system Change-Id: I79edba579249111294a982590660196f05be7eaf Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49083 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-07mb/google/volteer/var/elemi: Tune i2c frequencyWisley Chen
Tuning i2c frequency for elemi I2C0: 396.6 KHz I2C1: 395.9 KHz I2C5: 397.1 KHz BUG=b:176794161 BRANCH=volteer TEST=emerge-voleteer coreboot, and measure i2c clock. Change-Id: I23b04a9b5ff8873d9de12e762e8e2786ef474ac0 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-07mb/google/dedede/var/metaknight: update Goodix touch screen sequenceTim Chen
Update Goodix touch screen reset delay time to 180ms. BUG=b:176213670 TEST=Build and boot Metaknight to OS. Change-Id: I5801a36fb7c03b23046df16b1eaf4c548241bba5 Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-07mb/google/zork: Modify variant to Shuboz supportKane Chen
1. Add ELAN touchscreen/touchpad to overridetree.cb 2. Follow Dalboz setting to add variant.c BUG=b:174528384 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: Ic3193ca7957251841e75a7e5c7a16fc5047919fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/48001 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-07mb/google/lindar: Fix building with CONFIG_CHROMEOS unsetMatt DeVillier
Make CHROMEOS_DSM_CALIB depend on CHROMEOS, rather than force-select it. Change-Id: I4c3fd04ec00e0787381c58810938dd48f414635c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-07soc/intel/common/cse: Drop dependency on CHROMEOS for SOC_INTEL_CSE_LITE_SKUMatt DeVillier
The CSE lite SKU has 2 CSE firmware boot partitions vs 3 for the "normal" SKU; this has nothing to do with building for ChromeOS or not, and by having this dependency, boards with select the CSE lite SKU are unable to build with CONFIG_CHROMEOS unset due to Kconfig dependency issues. Test: build google/wyvern with CONFIG_CHROMEOS not set. Change-Id: I6959f35e1285b2fab7ea1f83a5ccfcb065c12397 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-07mb/google/puff/var/dooly: Config I2C0 SerialIoDevModeTony Huang
I2C0 has amplifier connection, thus set it to PchSerialIoPci. BUG=b:170273526 BRANCH=puff TEST=Build and check PCH serial IO config is set I2C0 to Mode 1 Change-Id: I9540f7b5538d37de53bcf43531488d714874a565 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
2021-01-07mb/google/dedede/var/magolor: modify raydium touch screenRen Kuo
modify raydium touch screen power on timing to meet requirement BUG=b:174280232 TEST=build firmware and measured the timing Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Change-Id: I3ecc9d8e21f8c76e9e96cf050dcde83c3c4f4ea7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48971 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-07mb/google/dedede/var/metaknight: Configure I2C high and low timesTim Chen
Configure the I2C bus high and low times for port0,2 and 4 I2C buses. BUG=b:176519792 TEST=Measured the I2C bus frequency lower than 400 KHz. Change-Id: Ieed038c93f0972c06cb3fa311742dd22ac2e875d Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-07mb/google/dedede/var/madoo: Update Goodix touchscreen power sequenceDtrain Hsu
Follow Goodix datasheet (GT7375 Programming Guide_Rev.0.1.pdf and GT7375P Programming Guide_Rev.0.6.pdf) to tune touchscreen power sequence. Increase reset_delay_ms from 120ms to 180ms. BUG=b:176511605 BRANCH=dedede TEST=Build and boot Madoo to OS Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Iae35e4da31a3c3afd24c7daf81a5a3e762acd3b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-01-07mb/google/dedede/var/boten: Configure I2C high and low timeStanley Wu
Configure the I2C bus high and low time for all enabled I2C buses. BUG=b:168783630 TEST=Measured the I2C bus frequency reduce to 387 KHz. Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: I37403dd3ac3c9320398207d2111e1ddb73d6a130 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48878 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-07mb/google/dedede/var/lantis: Config I2C high and low time for touchscreen/audioTony Huang
Config I2C high / low time in device tree to ensure I2C CLK runs accurately at I2C_SPEED_FAST (400 kHz). These tuning value is applied from touchpad as a base line, and EE measured touchscreen/audio runs at 399/396.7kHz after tuning. BUG=b:173709409 BRANCH=dedede TEST=Build and check after tuning I2C clock is under 400kHz Change-Id: I970d69e6361d7cf6fcfc4e5b0b3c5fbfa885367c Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-07mb/google/dedede/var/lantis: Config I2C high and low time for touchpadTony Huang
BUG=b:173709409 BRANCH=dedede TEST=EE measured result is 390.8kHZ Change-Id: I7a6475fd29d4c9f8efa78a42a112b5565511b939 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-07mb/google/zork/var/vilboz: Fix Goodix touchscreen power sequenceFrank Wu
According Goodix GT7375P Programming Guide_Rev.0.6, increase the stop delay time from 100 ms to 160 ms. The power sequence is not met with the latest guide_rev.0.6. BUG=b:176270381 BRANCH=zork TEST=Confirm the measured waveform complies with Goodix touchscreen spec. Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I687ffa2eb13a9ddecb3045c5e1540b94417329ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/48907 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-06soc/intel/broadwell: Move MAX_CPUS from mb to SoCFelix Singer
All Broadwell boards use 8 for MAX_CPUS, so this option can be factored out into SoC Kconfig. Change-Id: I311b95ea75a7c6b76b32c7197a0cec86db644234 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49122 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-06soc/intel/skylake: Move MAX_CPUS from mb to SoCFelix Singer
Configure MAX_CPUS in SoC Kconfig with 8 as default value and remove it from every mainboard where 8 is used. Change-Id: I825625bf842e8cd22dada9a508a7176e5cc2ea57 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49105 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-06mb/google/volteer/var/voema: Update Aux settings for Port 0David Wu
On Voema port 0 (MB PORT) does not have a retimer so the port needs to be configured for the SOC to handle Aux orientation flipping. BUG=b:176462544 TEST=tested on voema Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I3d31a5b848f56126f8ffe2babb29085471e8224f Reviewed-on: https://review.coreboot.org/c/coreboot/+/48976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2021-01-06mb/google/zork/mainboard: Remove unused pirq_dataRaul E Rangel
This table was wrong. It's also produced by the SoC code now. BUG=b:170595019 TEST=Verify PCI IRQ: log messages Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I008b6896064672f9d45a8e12f6cfc62c0cc41536 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-06cpu/intel/model_206ax: Rename `cX_acpower` optionsAngel Pons
They aren't specific to AC power operation anymore. Also adapt autoport. Change-Id: Ib04d0a08674b7d2773d440d39bd6dfbd4359e0fb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49089 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-06cpu/intel/model_206ax: Unify ACPI C-state optionsAngel Pons
All mainboards use the same values for AC and battery, even desktop boards without a battery. Use the AC values everywhere and drop the battery values. Subsequent commits will rename the AC power options accordingly, and will also clean up the corresponding acpigen code. This is intentional so as to ease reviewing the devicetree changes. Also update util/autoport accordingly. Change-Id: I581dc9b733d1f3006a4dc81d8a2fec255d2a0a0f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-05mb/google/zork: enable wake on MKBP eventsPeter Marheine
The EC generates EC_MKBP_EVENT_DP_ALT_MODE_ENTERED when USB-C connections enter DP alt mode, which should wake the system from S3. Configure S3 wake events to include MKBP so this actually wakes the system. BUG=b:174121852 BRANCH=zork TEST=Generating DP event on MKBP via EC console wakes morphius Change-Id: I8100c6253e8e5cae91586c4f2f45d66c15fecc6d Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2021-01-05mb/google/zork: Add INT[E-H] to FCH PIRRaul E Rangel
INT[E-H] are required because the GNB IO-APIC maps the 32 interrupts onto the 8 INT[A-H] that feed into the FCH PIC/IO-APIC. BUG=b:170595019 TEST=Verify ezkinil still boots Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I9c6689e212b136f6f3c64152803ed161b2284275 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-05mb/google/volteer/var/voema: Enable IPU for voemaDavid Wu
Enable IPU for voema for MIPI camera. BUG=b:169551066 TEST=IPU is enabled and shows in lspci. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I34736bffd4dc61a840003afe5afd6a9c8dc32e62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49002 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-04mb/google/hatch (baseboard): add ACPI backlight supportMatt DeVillier
Add ACPI backlight support for boards selecting BOARD_GOOGLE_BASEBOARD_HATCH. PUFF-based variants do not have an internal panel, so do not need this. Test: build/boot Windows 10 20H2 on google/akemi, verify display backlight controls functional. Change-Id: I5ce4c6e1c78299e89760a1356da452d56ba0aee6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49058 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-04mb/google/reef (and variants): add ACPI backlight supportMatt DeVillier
Enables backlight control under Windows 10. Test: build/boot Windows 10 20H2 on google/reef, verify display backlight controls functional. Change-Id: I4ce613badbdcfb9c843f52408df26c6cbb4b82a2 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-04drivers/vpd: Add support to read device serial from VPDMatt DeVillier
Add functions to read the system and mainboard serial numbers from VPD tables stored in flash. Remove board-specific implementations for google/drallion and google/sarien and select the new Kconfig instead. Test: build/boot google/akemi with RO_VPD region persisted from stock Google firmware, verify system/mainboard serial numbers present via dmidecode. Change-Id: I14ae07cd8b764e1e22d58577c7cc697ca1496bd5 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49050 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-04mb/google/zork: update DRAM table for morphiusKevin Chiu
Remove index0 DRAM assignment since it doesn't use in any build. Add Hynix DDR4 DRAM H5ANAG6NCJR-XNC, index was generated by gen_part_id BUG=b:175911098 BRANCH=zork TEST=emerge-zork coreboot Change-Id: I853a316c266afafeecff67b263005a77be316e2b Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48723 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-14 11:31:26 +0000