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2020-11-13broadwell: Flatten `acpi_init_gnvs` functionAngel Pons
Instead of relying on mainboards to call it, do like Lynx Point. Change-Id: Idb7457e0734e19d0a26f0762079e273b6e740475 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46793 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13broadwell: Factor out `acpi_fill_madt` functionAngel Pons
It is identical for all Broadwell mainboards, thus deduplicate it. Change-Id: I74559fbe42e44aa4d15ced5d88f6c15a1bf5203b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46792 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13nb/intel/haswell/acpi: Merge `haswell.asl` into `hostbridge.asl`Angel Pons
Tested with BUILD_TIMELESS=1, Google Wolf remains identical. Change-Id: I710581156937b042ba4cf5948c65d0795ad37bbf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46789 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13soc/intel/broadwell/acpi: Rename `systemagent.asl`Angel Pons
Rename it to `hostbridge.asl`, which is what Haswell uses. Change-Id: I6f97fc5c9459fe6b66dcfcf51900c751beda0ebe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46786 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13mb/google/reef: Configure IRQs as level triggered for HID over I2CKarthikeyan Ramasubramanian
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx BUG=b:172846122 TEST=./util/abuild/abuild Change-Id: Ifc6dd5f6549e7501f350afe8456a9a8096edcc25 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47425 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-13mb/google/poppy: Configure IRQs as level triggered for HID over I2CKarthikeyan Ramasubramanian
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx BUG=b:172846122 TEST=./util/abuild/abuild Change-Id: Ida1b1d05b39e67a9eba3bfaecca37f38821a438b Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-13mb/google/kahlee: Configure IRQs as level triggered for HID over I2CKarthikeyan Ramasubramanian
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx BUG=b:172846122 TEST=./util/abuild/abuild Change-Id: Ib2f203b5f5eea5c25cfd4543f5ed9f15101b1735 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-13mb/google/octopus: Configure IRQs as level triggered for HID over I2CKarthikeyan Ramasubramanian
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx BUG=b:172846122 TEST=./util/abuild/abuild Change-Id: Ic334816712370da63471135da8dd598ab02d54ef Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-13mb/google/zork: Configure IRQs as level triggered for HID over I2CKarthikeyan Ramasubramanian
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx BUG=b:172846122 TEST=./util/abuild/abuild Change-Id: I75a92616f11054993ff5a5bfefce5c3f4638c07c Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-13mb/google/drallion: Configure IRQs as level triggered for HID over I2CKarthikeyan Ramasubramanian
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx BUG=b:172846122 TEST=./util/abuild/abuild Change-Id: Iff00667377eecedcf0b83bcfc0bf50bd4c3411eb Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-13mb/google/deltaur: Configure IRQs as level triggered for HID over I2CKarthikeyan Ramasubramanian
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx BUG=b:172846122 TEST=./util/abuild/abuild Change-Id: I1773973f64bcc5ef6bd1856c5d8eb998bb6a4888 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-13mb/google/hatch: Configure IRQs as level triggered for HID over I2CKarthikeyan Ramasubramanian
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx BUG=b:172846122 TEST=./util/abuild/abuild Change-Id: I320198d56131cf54e0f73227479f69968719b2a7 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-13mb/google/volteer: Configure IRQs as level triggered for HID over I2CKarthikeyan Ramasubramanian
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx BUG=b:172846122 TEST=./util/abuild/abuild Change-Id: Ie7b82ea07ef97b2096d75229c445bd3a65cb3be0 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-13mb/google/dedede: Configure IRQs as level triggered for HID over I2CKarthikeyan Ramasubramanian
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx BUG=b:172846122 TEST=emerge-dedede coreboot Change-Id: I9d8fa57ae0f554896a4a0722e3e89567676382d4 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-13mb/google/dedede/var/metaknight: enable USB2 port for cameraTim Chen
Enable USB2 port 5 for user facing camera. Enable USB2 port 6 for world facing camera. BUG=b:169813211 BRANCH=None TEST=build metaknight firmware Change-Id: Iecb7787d46eab7096dec9f838a16da101105e09a Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-11-13mb/google/dedede/var/metaknight: Disable I2C port 3Tim Chen
Disable I2C port 3 for metaknight BUG=b:169813211 BRANCH=None TEST=build metaknight firmware Change-Id: Ic4a056d53a8c8abd04a9b786428da0986a255276 Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-11-12Delete mainboard/google/chezaJulius Werner
Work on this mainboard was abandoned and never finished. It's not really usable in its current state, so let's get rid of it. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I4cd2e2cd0ee69d9846472653a942fa074e2b924d Reviewed-on: https://review.coreboot.org/c/coreboot/+/47427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-11soc/intel/tigerlake: Update Kconfig for NEM Enhanced ModeShreesh Chhabbi
This change switches the selection of CAR mode so that INTEL_CAR_NEM_ENHANCED_V2 is the default unless mainboard selects INTEL_CAR_NEM. INTEL_CAR_NEM is selected only by mainboards using older silicon (ES1 or ES2) that did not support NEM enhanced mode. This enables NEM Enhanced Mode for TGL-U/Y RVPs. Bug=b:171601324 BRANCH=volteer Test=Build coreboot for volteer. Boot on SKU that has 4MB L3 cache. Change-Id: Ib6e041261cb8ca9c6e602935da4962aac0d9ece5 Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-10sb/intel/lynxpoint/sata: Always use AHCI modeAngel Pons
The other two modes are not used by any mainboard, and the code seems to be copied from older southbridges. As the code looks incorrect, drop it. Change-Id: I374546279a85cead1aea13e0952bbfd6f643a75b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-10mb/google/zork: Create Shuboz variantKane Chen
Create the shuboz variant of the zork reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.2.0). BUG=b:172021093 BRANCH=none TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I3f62625f8cbde1c9adf8ab335edeb9e811e32679 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47152 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-10mb/google/puff/var/dooly: Add WEIDA touchscreen deviceTony Huang
Adds ACPI properties for WDT8762A device. Per spec v0.8 HID name WDHT2002 T14=100ms BUG=b:163561649 BRANCH=puff TEST=emerge-puff coreboot and check system dmesg and evtest can get device. Change-Id: I178e9d5aa1e1501d33b3cd4092f3f522bb6f1a74 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-11-09hatch: Create genesis variantMatt Ziegelbaum
Create the genesis variant of the puff reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.2.0). BUG=b:172620124 BRANCH=None TEST=util/abuild/abuild -p none -t google/hatch -x -a make sure the build includes GOOGLE_GENESIS Signed-off-by: Matt Ziegelbaum <ziegs@chromium.org> Change-Id: I70886c2c5a25f5de1a4941ff235547ee812fa50d Reviewed-on: https://review.coreboot.org/c/coreboot/+/47334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-11-09mb/google/volteer/eldrid: Describe the privacy_gpioRicardo Ribalda
Add information regarding the privacy pin on the overridetree and the gpio. BUG=b:171888751 Change-Id: I1ab19a863715ba5a928dd7c16402d398e5475edc Signed-off-by: Ricardo Ribalda <ribalda@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-09mb/google/hatch/jinlon: Describe the privacy_gpioRicardo Ribalda
Add information regarding the privacy pin on the overridetree and gpio. BUG=b:169840271 Change-Id: Ifa628dda03f3f65976850aeabaf516f528a921b7 Signed-off-by: Ricardo Ribalda <ribalda@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-09mb/google/dedede/variants/magolor: Update Power Limit2 minimum valueSumeet R Pawnikar
Update Power Limit2 (PL2) minimum value to the same as maximum value for magolor board. DTT does not throttle PL2, so this minimum value change here does not impact any existing behavior on the system. BUG=b:168353037 BRANCH=None TEST=Build and test on magolor board Change-Id: I74e960de506d366cba2c8aefb23f9e69337fd163 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-09mb/google/dedede/var/boten: Add LTE power on/off sequenceKarthikeyan Ramasubramanian
LTE module used in boten has a specific power on/off sequence. GPIOs related to power sequnce are: * GPP_A10 - LTE_PWR_OFF_R_ODL * GPP_H17 - LTE_RESET_R_ODL 1. Power on: GPP_A10 -> 20ms -> GPP_H17 2. Power off: GPP_H17 -> 10ms -> GPP_A10 3. Warm reset: Power off -> 500ms -> Power on Configure the GPIOs based on these requirements. BUG=b:163100335 TEST=Build and boot Boten to OS. Ensure that the LTE module power sequence requirements are met. Change-Id: Ic6d5d21ce5267f147b332a4c9b01a29b3b8ccfb8 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-09mb/google/dedede: Add support for variant specific SMI sleep flowKarthikeyan Ramasubramanian
This support is required to power off certain components that exist only in certain variants. BUG=None TEST=Build and boot Boten to OS. Change-Id: Ib43ada784666919a4d26246a683dad7f3546fabb Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-09mb/google/volteer/var/voema: Add memory parts and generate DRAM IDsDavid Wu
This change adds memory parts used by variant voema to mem_parts_used.txt and generates DRAM IDs allocated to these parts. Added memory 1. MT53E512M64D4NW-046 WT:E 2. MT53E1G64D8NW-046 WT:E BUG=b:171755775 TEST=emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I24d466f92a7e0fa3ab2f6241f0b5af025c53ed98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47228 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-11-09Atlas: Wake up AP on AC plug and unplugDaisuke Nojiri
This patch makes Atlas resume from S0ix by AC plug and unplug. BUG=b:165328935 BRANCH=atlas TEST=Put Atlas in suspend. Wake it up by AC plug. TEST=Put Atlas in suspend. Wake it up by AC unplug. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I95676d785bfc1488a8c1bdd3d56f2c38d95f3fb6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-11-09mb/google/dedede/var/drawcia: Remove camera EEPROM power resourceKarthikeyan Ramasubramanian
EEPROM in the camera module does not require any specific power resources. This will ensure that no unnecessary resources are turned on while accessing the camera EEPROM. BUG=b:167938257 TEST=Build and boot to OS in Drawlat. Ensure that the camera EEPROM is listed in the output of i2cdetect. Change-Id: Iece9b3f657bf94a21cc08bf1745353575858f9b2 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-09mb/google/dedede: Enable Wake on AC connect and disconnectKarthikeyan Ramasubramanian
Handle AC connect and disconnect notifications from Embedded Controller (EC) and wake from S3/S0ix. BUG=b:172266344 TEST=Build and Boot to OS in Drawlat. Ensure that the system wakes up from suspend on AC connect and disconnect on both the TypeC ports. 276 | 2020-11-04 12:21:29 | S0ix Enter 277 | 2020-11-04 12:21:40 | S0ix Exit 278 | 2020-11-04 12:21:40 | EC Event | AC Disconnected 279 | 2020-11-04 12:21:57 | S0ix Enter 280 | 2020-11-04 12:22:03 | S0ix Exit 281 | 2020-11-04 12:22:03 | EC Event | AC Connected 282 | 2020-11-04 12:22:35 | S0ix Enter 283 | 2020-11-04 12:22:47 | S0ix Exit 284 | 2020-11-04 12:22:47 | EC Event | AC Disconnected 285 | 2020-11-04 12:23:08 | S0ix Enter 286 | 2020-11-04 12:23:16 | S0ix Exit 287 | 2020-11-04 12:23:16 | EC Event | AC Connected Change-Id: I7fa4ac0096548fd63af86e9f56c4c1ee25491399 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-09mb/google/dedede/variants: Update Power Limit2 minimum valueSumeet R Pawnikar
Update Power Limit2 (PL2) minimum value to the same as maximum value for dedede variants (baseboard and drawcia). Currently, variants like boten, waddledee, waddledoo, metaknight and wheelie uses the DTT entries from baseboard devicetree since there is no override present for these variants. So, these variants will also reflect this change of PL1 minimum value. For madoo variant, PL2 minimum value already set the same as PL2 maximum value. DTT does not throttle PL2, so this minimum value change here does not impact any existing behavior on the system. BUG=None BRANCH=None TEST=Build and test on drawcia system Change-Id: I7ecf1ffcc7871192ebe18eb8c3c3fd3e1193721e Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47154 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-09soc/intel/*/chip: Remove unused devicetree entryPatrick Rudolph
InternalGfx isn't used so drop it. Change-Id: I12f424d8d883e065ef8d007e56a8bff41a7fae53 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-09mb/google/volteer/var/voema: config CSE LITEDavid Wu
Config voema to use CSE LITE BUG=b:171755775 TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ic4ca82ce844e6367da70ed052445943572ae7b09 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-09mb/google/variant/voema: Select USE_CAR_NEM_ENHANCED_V2 for voemaDavid Wu
BUG=b:171755775 TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ibedbbe8f9ac039cbde114ace3266ec067a4003ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/47159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-09mb/google/volteer: Skip TPM detection except on SPIJes Klinke
Production Volteer devices have Cr50 TPM connected via SPI, depending on Cr50 firmware version it may or may not support long enough interrupt pulses for the SoC to safely be able to enable lowest power mode. Some reworked Volteer devices have had the Cr50 (Haven) TPM replaced with Dauntless, communicating via I2C. The I2C drivers do not support being accessed early in ramstage, before chip init and memory mapping, (tlcl_lib_init() will halt with an error finding the I2C controller base address.) Since the Dauntless device under development can be made to support longer interrupts, or a completely new interrupt signalling mode, there is no need to try to go through the same discovery as is done via SPI. This CL will skip the discovery, enabling the S0i3.4 sleep mode in all cases, on the reworked test devices. BUG=b:169526865, b:172509545 TEST=abuild -t GOOGLE_VOLTEER2 -c max -x Change-Id: I08a533cede30a3c0ab943938961dc7e4b572d4ce Signed-off-by: Jes Bodi Klinke <jbk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47049 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-09mb/google/volteer/variants/volteer2: Tune I2C3 camera bus freq 400 kHzJohnny Li
The current I2C3 bus frequency is 341 kHZ, which does not meet the spec. This change updates scl_lcnt, scl_hcnt, sda_hold value for I2C3 to bring the bus frequency closer to 400kHz. BUG=b:153588771 TEST=Verified that I2C3 frequency is 394kHz. Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com> Change-Id: Ie1ef95bb39d71fbb113120a0ec88305bc23e7ab9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-11-09mb/google/puff/var/dooly: Set default I2C0 frequencyTony Huang
This setting copy from puff reference board and should measure again after whole system build. BUG=b:155261464 BRANCH=puff TEST=emerge-puff coreboot and check system speaker has sound output. Change-Id: Idd5c3276e9306e81ea766d14ed1415a68dedc2ad Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47161 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-06zork/var/ezkinil: Adjust USB2 phy si fine tune on DVT BoardLucas Chen
Adjust USB2 phy si setting fine tune on DVT for Ezkinil. BRANCH=zork BUG=b:156315391 TEST=Measuring scope timing and test usb detection Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Change-Id: Id537b6e9a17f47481b6aedcea0c6a8474d993b6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/47011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-11-06mb/google/volteer/var/elemi: Update gpio and devicetreeWisley Chen
Update gpio and devicetree for elemi. BUG=b:170604353 TEST=emerge-volteer coreboot and boot into kernel Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Change-Id: I5b8880d485ed73aa4e65c1249c58f02c8f0c6501 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-06mb/google/variant/elemi: config CSE LITEWisley Chen
Config elemi to use CSE LITE BUG=b:170604353 TEST=emerge-volteer coreboot Change-Id: I31c7a743645d6a34ee34e750ba92c108b306ee09 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47019 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-06mb/google/variant/elemi: Select USE_CAR_NEM_ENHANCED_V2 for elemiWisley Chen
BUG=b:170604353 TEST=emerge-volteer coreboot Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Change-Id: I1a1ab6f3d57d5023523b85bfb00d48d8b70a6c1f Reviewed-on: https://review.coreboot.org/c/coreboot/+/47018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-06soc/amd/picasso: Update coreboot UPD variable names to include unitsZheng Bao
Use command below to change the variable globally. sed -i "s/\<variable\>/variable_u/g" `grep variable -rl ./ \ --exclude-dir=build --exclude-dir=crossgcc` BUG=b:171334623 TEST=Build Change-Id: I056a76663e84ebc940343d64178c18cb20df01a3 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-11-06mb/google/octopus/variants/garg: Add new LTE SKUKevin Chiu
Add new SKU definition: Garg360 (LTE DB,1A2C,TS, no stylus, rear camera) SKU ID - 39 BUG=b:170708728 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage Change-Id: Ifec4e1360bd1aff3825bc6413b0a2ccd8b822075 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47015 Reviewed-by: Marco Chen <marcochen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-05soc/amd/picasso: move MAX_CPUS setting from mainboard to SoC KconfigFelix Held
Since the mainboard Kconfig is sourced before the SoC one, it would still be possible to override this setting at mainboard level, even though that shouldn't be needed. The maximum CPU count for Picasso is 8, since the chips have only up to 4 cores with up to two threads each. Change-Id: I53449b8fa73c5d13e6ea77bee6eed8896b7d3ec3 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47205 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04sb/intel/lynxpoint: Align LP GPIO ACPI with BroadwellAngel Pons
Move the `GWAK` method into the GPIO device, and have lpc.c include the LP GPIO code. All usages of `GWAK` on mainboards need to be updated. Change-Id: Id6a41f553d133f960de8b232205ed43b832a83d2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46775 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04mb/google/link: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'dsdt.dsl' files are identical. Change-Id: I7d4fc3acd82023b007d80638bcb71476330ef320 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-11-04mb/google/beltino: Convert to ASL 2.0 syntaxElyes HAOUAS
Built google/beltino (Monroe) provides identical 'dsdt.dsl'. Change-Id: I12b6a8264e53ece30ae79da2d79c6f1d302fb357 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-11-04mb/google/volteer/var/voema: Update dq/dqs mappingsDavid Wu
Update dq/dqs mappings based on voema schematics. BUG=b:169356808 BRANCH=volteer TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I1aae4286278e712bf29ebb15738477828d3f74d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-04soc/amd: Change FIRMWARE_LOCATE to FIRMWARE_LOCATIONZheng Bao
Change-Id: I3a3d187fc24ab752dfe61893c15561a92d009fe2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46062 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-09 04:49:03 +0000