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FATAL_ASSERT is used for debugging purpos. Don't select it by default.
Change-Id: If4d521827f3d50fb662b89b24d00fb0517e7af2d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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Change-Id: I06cdb8eaaf7f74b47e1d1283dcaa765674ceaa45
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36070
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Turn off HDMI power when enter s0ix and S5.
BUG=b:143057255
BRANCH=N/A
TEST=Measure the power on GPP_E16 under s0ix and S5
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I580e6094d48663d5c208fd82c7744485d899bcc1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36224
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Modify DPTF parameters.
Modify TDP PL1 values to 15.
Remove TCHG Level 3 - 0.5A.
BUG=b:131272830
BRANCH=none
TEST=emerge-hatch coreboot chromeos-bootimage
Signed-off-by: YenLu Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I0e5c079856a167b1c2ef52e446d055404e565858
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35794
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Each variant needed to define variant_early_gpio_table(), even if
it didn't need to make any changes. Added a __weak version of the
function into baseboard/gpio.c.
Certain upcoming Hatch variants will not use SPD files. Allow
SPD_SOURCES in spd/Makefile.inc to be empty.
BUG=None
BRANCH=None
TEST=Build coreboot and see that it builds without error
Change-Id: Ie946cfd7c071824168faa38fd53bd338a5a451e1
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36068
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add Cirque Touchpad devicetree configuration to export relevant ACPI
objects to the kernel.
BUG=b:141259109
BRANCH=sarien
TEST=Boot to ChromeOS. Ensure that relevant ACPI objects are exported in
the SSDT.
Change-Id: I91dcb27b86c6a2bed5579f1f6c1102871d55b315
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This change removes an inversion of GPP_D17 that caused the
device to get stuck in a reboot loop because the kernel was crashing
within the first couple seconds of kernel boot.
BUG=b:142515200
BRANCH=none
TEST=Flash and boot nocturne, verify boot is stable and that device
doesn't reboot after jumping into kernel, and that it passes the
'tast -verbose run <ip> hardware.SensorRing' test.
Change-Id: Ia1408ef6ea92f6b31a9f3eee8720954af3a7c382
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35967
Reviewed-by: Yicheng Li <yichengli@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:142987639
TEST=emerge-hatch coreboot
Change-Id: I0ff1a81d0579d0b328a48bc7d4f867592ec63e8b
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philip Chen <philipchen@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I46d131f76ec930d2ef0f74e6eaabae067df10754
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Change-Id: I3d90e46ed391ce323436750c866a0afc3879e2e6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36359
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This drops support for FSP 1.1 in soc/intel/skylake, after all boards
have been migrated to FSP 2.0, which is backwards compatible.
Any moving of files happens in a follow-up commit to make review easier.
Change-Id: I0dd2eab0edfda0545ff94c3908b8574d5ad830bd
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35813
Reviewed-by: Michael Niewöhner
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ic2f0944b92dcad7048a0c38720d2ef3c855ef007
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID
object or an _ADR object, but should not contain both."
Change-Id: I50cafce0aaf465ee95562ccff6c8f63fb22096c0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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mainboard_silicon_init_params() is supposed to be used for only
overriding any FSP params as per mainboard configuration. GPIOs should
be configured by mainboard as part of its chip init(). This ensures
proper ordering w.r.t. any common operations that the SoC code might
want to perform e.g. snapshot ITSS polarities.
This change moves the configuration of GPIOs from
mainboard_silicon_init_params() to mainboard chip->init().
Change-Id: I5d10c01c5b9d5f8ed02274d51dcf9c2a17269685
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36270
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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mainboard_silicon_init_params() is supposed to be used for only
overriding any FSP params as per mainboard configuration. GPIOs should
be configured by mainboard as part of its chip init(). This ensures
proper ordering w.r.t. any common operations that the SoC code might
want to perform e.g. snapshot ITSS polarities.
This change moves the configuration of GPIOs from
mainboard_silicon_init_params() to mainboard chip->init().
Change-Id: I5cd89c6e24b6a4b0c20fd476915f3781a0d46e0d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36269
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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mainboard_silicon_init_params() is supposed to be used for only
overriding any FSP params as per mainboard configuration. GPIOs should
be configured by mainboard as part of its chip init(). This ensures
proper ordering w.r.t. any common operations that the SoC code might
want to perform e.g. snapshot ITSS polarities.
This change moves the configuration of GPIOs from
mainboard_silicon_init_params() to mainboard chip->init().
Change-Id: Ied0201b954894acd3503801e7739b91a2cc9b4a8
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36268
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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mainboard_silicon_init_params() is supposed to be used for only
overriding any FSP params as per mainboard configuration. GPIOs should
be configured by mainboard as part of its chip init(). This ensures
proper ordering w.r.t. any common operations that the SoC code might
want to perform e.g. snapshot ITSS polarities.
This change moves the configuration of GPIOs from
mainboard_silicon_init_params() to mainboard
chip->init(). Additionally, this change moves mainboard_ec_init() to
mainboard dev->init().
TEST=Verified that GPIOs are configured properly and hatch boots to
OS.
Change-Id: Ia509471a3678c60454cd4f14625f151860d9b9d2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36267
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Set VPD keys for DSM parameters in overridetree.cb for Helios.
RT1011 driver will load values from VPD and set them to device property.
BUG=b:140397934
BRANCH=none
TEST=On Helios, with patch series, check realtek,r0_calib and
realtek,temperature_calib are available to rt1011 codec driver.
Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org>
Change-Id: Ic72fd57becf93e70a1a716dbb76633509f2fd5c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The correct mapping for speakers to their names should be:
uid 0: Woofer Left
uid 1: Woofer Right
uid 2: Tweeter Left
uid 3: Tweeter Right
Also, fix the name to be 4-character.
BUG=b:140397934, b:143192767
BRANCH=none
TEST=On Helios, with patch series, check realtek,r0_calib and
realtek,temperature_calib are available to rt1011 codec driver.
And the speaker mapping is correct.
Change-Id: I353fb9ad0ca8ec85431eb2b59be748b4887278cf
Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36256
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add thermal sensor: TSR2 to ACPI table, monitor CPU temperature
BUG=b:143046086
TEST=FW_NAME="akemi" emerge-hatch coreboot chromeos-ec
chromeos-bootimage
Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: Id150c5c3cb6d07407fd20417237457b5722e6f2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Philip Chen <philipchen@google.com>
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Add enum for Vorticon sku.
Vortininja/Vorticon will load vbt_vortininja.bin
Dorp will load vbt_dorp.bin
BUG=b:143197918
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage
check i915_drrs_status shows DRRS supported NO
when SKU-ID sets to Dorp/Vortininja/Vorticon.
Change-Id: I67d7a8ab62a1838b0a0a05f532d8b067ece686d9
Cq-Depend: chrome-internal:2026287
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID
object or an _ADR object, but should not contain both."
Found-by: ACPICA 20191018
Change-Id: I8bcdfa7a4dc33c3e3866d3135249a602379b9615
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36265
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use RT1011 driver for Helios. Select CHROMEOS_DSM_CALIB to set device
properties for RT1011 speaker calibration.
BUG=b:140397934
BRANCH=none
TEST=On Helios, with patch series, check realtek,r0_calib and
realtek,temperature_calib are available to rt1011 codec driver.
Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org>
Change-Id: I1010be15466c5060aa1d73318393853a2515daac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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On hatch and variant HW designs supports VCCPRIM_CORE Low Voltage Mode.
VCCPRIM_CORE can be down to 0.75v when slp_s0 is asserted.
This commit enables PchPmSlpS0Vm075VSupport UPD so that FSP can
program related setttings to save power.
BUG=b:134092071
TEST=Run suspend_stress_test on kohaku and pass 100 cycles
Change-Id: Ia02ff8823883489b36349457213409496f082f36
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Correct ICC_MAX values per SKL-Y EDS spec.
Adapted from chromium commit 1c4e89e8 [Chell: Update ICC_MAX configuration]
Original-Change-Id: Ic660cc6a2d11e995a86a30ddde800d096d93e012
Original-Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/593715
Original-Reviewed-by: Duncan Laurie <dlaurie@google.com>
Change-Id: Ia31ce432cf979d574d84e9205a287f87de5de057
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Michael Niewöhner
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Change GPP_B21 default to low. This can prevent power leakage
of non-touch sku.
BUG=b:142849034
BRANCH=N/A
TEST=Measure the power of non-touch sku, check GPP_B21 is 0V.
Boot up with touch sku and check touch functional.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I80a3e5dc224e4dab97c21fd469d8c3f2d3e774e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com>
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Configure enable pin GPP_D9 pull high when active
BUG=b:143046441
TEST=build bios and verify touch screen works fine
Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I83060f31d4d22c9be05bba119816c6aa66e4126c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36186
Reviewed-by: Philip Chen <philipchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Share the same vbt_blooguard.bin to disalbe DRRS support.
BUG=b:143045247
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage
check i915_drrs_status shows DRRS supported NO when SKU ID is blooglet.
Change-Id: Ia180f265080f801a09f10ce8a8b520c47f218775
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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This patch is part of the patch series to drop support for FSP 1.1 in
soc/intel/skylake.
The following modifications have been done to migrate the board(s) from
FSP 1.1 to FSP 2.0:
- remove deprecated devicetree VR_RING domain (only 4 domains in FSP 2.0)
- switch to using the FSP default VBT
TODO:
- testing
Change-Id: Id747ef484dfdcb2d346f817976f52073912468d0
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I0c965e598e260ff8129aa07fb9fc5bf6e784e1d8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Add ELAN EKTH6915 USI touchsreen support.
BUG=b:139392144
TEST=check touchscreen work, and confirmed power sequence with vendor.
Change-Id: I8ebc067bbb407498de00ea0b6c23b0848023cffe
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36125
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add data.vbt and modify Kconfig appropriately;
allows use of FSP/GOP display init.
VBT extracted from stock ChromeOS firmware.
Change-Id: I8a2d093ad96f72fb420b94aafa790e3ba900d905
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Akemi unused devices declare:
- I2C #1 gpio_keys
- close I2C #3
- close GSPO #1
BUG=b:142800988
TEST=Reboot stress test and suspend stress test, the DUT will be
able to working properly
Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: Ibff1446ccb213abce1a2ae19718774d9d6737cc9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36086
Reviewed-by: Ben Kao <ben.kao@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I2a94c3b6282e9915fd2b8136b124740c8a7b774c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This commit creates a dood variant for Octopus. The initial settings
override the baseboard was copied from variant bobba.
BUG=b:141960652
BRANCH=octopus
TEST=emerge-octopus coreboot
Change-Id: Id8852e1f04f4356fac5445f6da6d56d430c88ad0
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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The change applies the DPTF parameters.
BUG=b:142849037
TEST=build and verified by thermal team
Change-Id: I5da8d373f38d23929ffec95bc1c9e942f131297f
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Chrome OS firmware images have moved bitmap resources from GBB into CBFS
for a long time, so the GBB should only hold firmware keys and HWID,
that is usually less than 10k.
ARM boards usually limit GBB to 0x2f00 (see gru, cheza and kukui) but
many recent x86 simply copy from old settings and may run out of space
when we want to add more resources, for example EC RO software sync.
Note, changing the GBB section (inside RO) implies RO update,
so this change *must not* be cherry-picked back to old firmware
branches if some devices were already shipped.
BRANCH=none
BUG=None
TEST=make # board=darllion,hatch,kahlee,octopus,sarien
Change-Id: I615cd7b53b556019f2d54d0df7ac2723d36ee6cf
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Tune I2C bus 1 clock and insure it meets I2C spec.
BUG=b:142683257
TEST==flash coreboot to the DUT and measure I2C bus 1 clock
frequency less than 400KHz
Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: Id4cdbad4dd9d451763fb536988402d6e6fe3a378
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add enable pin for elan touchscreen
BUG=b:142710871
TEST=touchscreen work
Change-Id: I09b6ffb962272bfe46e63b057be885b1bdf13554
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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Update power sequence to meet spec.
BUG=b:142710867
TEST=touchscreen work, and make sure power sequence to meet
spec with vendor.
Change-Id: I98f8b095374caa8c3540307a51f9d3b69baec905
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36060
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add the SPD data for MT40A1G16KD-062E:E
BUG=b:139397313
TEST=Compile successfully.
Change-Id: I3d1ae9269ff3129845a7f53dbacbab6e1b66b6d5
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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Disable DRRS on Blooguard SKU - 49, 50, 51, 52
BUG=b:142632381
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage
check i915_drrs_status shows DRRS supported NO when SKU ID is blooguard.
Cq-Depend: chrome-internal:1983227
Change-Id: I36a313fd2beacb878da7383f733e206067c1c0fb
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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This sets up some common default LPC decode ranges in a common place.
This may set up more decode ranges than needed but that typically does
not hurt. Mainboards needing additional ranges can do so in the
mainboard pch_enable_lpc hook.
Change-Id: Ifeb5a862e56f415aa847d0118a33a31537ab8037
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Port the backlight-PWM handling from Skylake instead of the previously
used Haswell version. We use a 200Hz PWM signal for all boards. Which
is higher than the previous devicetree value, 183Hz, but that was over-
ridden by the VBIOS anyway. 200Hz is still very low, considering LED
backlights, but accurate values are unknown at this time.
Lynx Point, the PCH for Haswell and Broadwell, is a transition point
for the backlight-PWM config. On platforms with a PCH, we have:
o Before Lynx Point:
The CPU has no PWM pin and sends the PWM duty-cycle setting
to the PCH. The PCH can choose to ignore that and use its own
setting (BLM_PCH_OVERRIDE_ENABLE).
We use the CPU setting on these platforms.
o Lynx Point + Haswell:
The CPU has an additional PWM pin but can be set up to send
its setting to the PCH as before. The PCH can still choose
to ignore that.
We use the CPU setting with Haswell.
o Lynx Point + Broadwell:
The CPU can't send its setting to the PCH anymore. BLM_PCH_
OVERRIDE_ENABLE must always be set(!) if the PCH PWM pin is
used (it virtually always is).
We have to use the PCH setting in this case.
o After Lynx Point:
Same as with Broadwell, only BLM_PCH_OVERRIDE_ENABLE is
implied and the bit not implemented anymore.
Change-Id: I1d61d9b3f1802ebe18799fc4d06f1f1d3b54c924
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Helios adds TEMP_SENSOR4 to the EC ADC2 pin. Add this to
the DPTF.
BRANCH=None
BUG=b:142266102
TEST=`emerge-hatch coreboot`
Verify that Helios builds correctly.
Change-Id: I3bc19f9b9bd644e134987749ad9a4d875ad8b40a
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Enable wifi sar feature and set wifi sar name for dragonair sku.
BUG=b:142109545
TEST=emerge-hatch coreboot chromeos-bootimage
1. Check wifi_sar-dragonair.hex in /cbfs-rw-raw/dratini
2. Add iwlwifi.debug into kernel params.
3. check SAR value from dmesg only when sku id is 21/22
Change-Id: I0e08610b7c7d2d8da5a749d278bcde26af590e31
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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FPMCU_PCH_BOOT1 pin is connected to GPP_C12. So, config GPP_C12.
BUG=b:142188003
TEST=emerge-hatch coreboot
Change-Id: I73a5c3529330ef3e72f4c7d5fcbbd2f6693494d8
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35845
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The next board rev will have a new option for an Elan touchscreen. Add
support for this in the devicetree, as well as use the 'probed' property
on both touchscreen options.
BUG=b:141957731
BRANCH=none
TEST=compiles (next board rev not available yet)
Change-Id: I135e693304cbb8dffc0caf4c07846033d6802208
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Update GPIO_138 and GPIO_139 setting to fix EMR function.
BUG=b:141729962,b:141281846
BRANCH=octopus
TEST=verify EMR function in Grob360S.
Change-Id: I28cef592374fb4aeee2f3d3010cc0e237d62a2fd
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Load the calibration params from flash first and check the correctness
of the params. If the params have correct format, perform DRAM fast
calibration with these params to reduce bootup time. Otherwise, load the
DRAM blob and perform DRAM full calibration.
Bootup time of DRAM partial calibration:
- 1,349,385 usecs with low frequency
- 924,698 usecs with middle frequency
- 1,270,089 usecs with high frequency
3,544,172 usecs in total.
Bootup time of DRAM fast calibration:
- 216,663 usecs with low frequency
- 328,220 usecs with middle frequency
- 322,612 usecs with high frequency
867,495 usecs in total.
BUG=b:139099592
BRANCH=none
TEST=emerge-kukui coreboot
Change-Id: I8de29b14b1fb24b3b4f351c855c5c4d8f350cc34
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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