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2015-03-24rk3288: update romstage & mainboardhuang lin
BUG=chrome-os-partner:29778 TEST=Build coreboot Change-Id: I877b4bf741f45f6cfd032ad5018a60e8a1453622 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 640da5ad5597803c62d9374a1a48832003077723 Original-Change-Id: I805d93e94f73418099f47d235ca920a91b4b2bfb Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209469 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Tested-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8867 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-24rk3288: add ddr driverJinkun Hong
Supports DDR3 and LPDDR3.Supports dual channel.ddr max freq is 533mhz. ddr timing config file in src\mainboard\google\veyron\sdram_inf Remove dpll init in rk clk_init(), add rkclk_configure_ddr(unsigned int hz). BUG=chrome-os-partner:29778 TEST=Build coreboot Change-Id: I429eb0b8c365c6285fb6cfef008b41776cc9c2d9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 52838c68fe6963285c974af5dc5837e819efc321 Original-Change-Id: I6ddfe30b8585002b45060fe998c9238cbb611c05 Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209465 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8865 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-03-24add make_idb.py & update bootblockhuang lin
BUG=chrome-os-partner:29778 TEST=Build coreboot Change-Id: Ica7b2bf2cf649c2731933ce59a263692bb2c0282 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ba9c36daedc749748f45e68a84f8c34c636adb1c Original-Change-Id: Ia0e4e39d4391674f25e630b40913eb99ff3f75c4 Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209427 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8862 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-24vboot2: separate verstage from bootblockDaisuke Nojiri
With CONFIG_RETURN_FROM_VERSTAGE false, the verstage loads the romstage over the bootblock, then exits to the romstage. this is necessary for some SOC (e.g. tegra124) which runs the bootblock on a different architecture. With CONFIG_RETURN_FROM_VERSTAGE true, the verstage returns to the bootblock. Then, the bootblock loads the romstage over the verstage and exits to the romstage. this is probably necessary for some SOC (e.g. rockchip) which does not have SRAM big enough to fit the verstage and the romstage at the same time. BUG=none TEST=Built Blaze with USE=+/-vboot2. Ran faft on Blaze. BRANCH=none Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: I673945c5e21afc800d523fbb25d49fdc83693544 Original-Reviewed-on: https://chromium-review.googlesource.com/212365 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Note: This purposefully is probably broken in vendorcode/google/chromeos as I'm just trying to set a base for dropping more patches in. The vboot paths will have to change from how they are currently constructed. (cherry picked from commit 4fa17395113d86445660091413ecb005485f8014) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I9117434ce99695f9b7021a06196d864f180df5c9 Reviewed-on: http://review.coreboot.org/8881 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-24nyans: reduce code duplication in bootblock and romstagesDaisuke Nojiri
this change reduces the code duplication of the bootblock and the romstages for Nyans. BUG=none TEST=Built Nyan, Big, and Blaze. Ran faft on Blaze. BRANCH=none Original-Signed-off-by: dnojiri@chromium.org (Daisuke Nojiri) Original-Change-Id: Ieb9dac3b061a2cf46c63afb2f31eb67ab391ea1a Original-Reviewed-on: https://chromium-review.googlesource.com/214050 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit f3413d39458f03895fe4963a41285f71d81bcf5f) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I912f63b12321aa26a7add302fc8a6c4e607330ef Reviewed-on: http://review.coreboot.org/8880 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-23vboot2: translate shared data to hand off to depthchargeDaisuke Nojiri
TEST=Built Blaze with USE=+/-vboot2. Ran faft: CorruptBothFwAB, CorruptBothFWSigAB, CorruptFwBodyA/B, CoccurptFwSigA/B, DevBootUSB, DevMode, TryFwB, UserRequestRecovery, SelfSignedBoot, RollbackFirmware. BUG=None BRANCH=none Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: I45a1efd4d55fde37cc67fc02642fed0bc9366469 Original-Reviewed-on: https://chromium-review.googlesource.com/205236 Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit 0a9e7f099251c33ce286fa8d704a3e021eac4d3e) Change-Id: I5f61c03c66ca83a5837c14378905ba178aba5300 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8655 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-03-23Enable publishing of board ID where supportedVadim Bendebury
These boards are supposed to be able to determine the board ID at run time based on GPIO settings. BUG=chrome-os-partner:30489 TEST=verified that all boards build. Checked that storm proto0 reports board ID of 0 on the console Original-Change-Id: Iadd758a799d69e1e34579d7d495378856b64c45b Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210119 (cherry picked from commit f4d41ddf906c1bf0d10da38011998fa0a630c332) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I0d5f94d3428157a70f0a9d711b57432e3f796733 Reviewed-on: http://review.coreboot.org/8722 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-23storm: Add board ID calculation functionVadim Bendebury
storm uses three GPIOs in tertiary mode, such that proto0 returns value of 8 when the GPIOs are interpreted as a single tertiary number. Adjust the calculated value to return board ID of 0 on proto0, and monotonously incrementing values on newer boards. BUG=chrome-os-partner:30489 TEST=when enabled, the board ID value of zero is reported on the console. Original-Change-Id: I2ff8fd5cbc8d568877b6f8bf220e146893f1e4be Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210118 (cherry picked from commit 6ba24f31583933f02be111c8767ae9df56537011) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I35ee218df35a0924d4bb8fcbc6c875450a609f24 Reviewed-on: http://review.coreboot.org/8721 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-23Include board ID calculations only when necessaryVadim Bendebury
For the majority of Chrome OS boards there is no need to include board ID calculation in any stage but ramstage, where the ID should be available for inclusion into the coreboot table. BUG=chrome-os-partner:30489 TEST=build only, no other tests yet Change-Id: I1451d52382bc48cc126d40267e0f61712f4a6d4b Original-Change-Id: Ib9c06698a399d31e79a9b14143343ba2ad46d0fb Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210117 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 27dd40e85bfcd0a38f388bad4d79f5fbb77a7566) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/8720 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-23ipq806x: implement GPIO APIVadim Bendebury
Add implementation of the GPIO API defined in src/include/gpiolib.h. Also, clean up the GPIO driver, make it use pointers instead of integers for register address. This requires a touch in the SPI driver, where the CS GPIO is toggled and in the board function where it enables USB interface. BUG=chrome-os-partner:30489 TEST=tested with the following patches, observed proto0 properly read the board ID. Original-Change-Id: I0962947c6bb32a854ca300752d259a48e9e7b4eb Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210115 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit e951f735001509d135cc61530ed0eecb5fc31a85) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I8a612dce000931835054086c1b02ebfc43dc57d2 Reviewed-on: http://review.coreboot.org/8718 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-23Generalize revision number calculation functionVadim Bendebury
Some platforms use tertiary interpretation of GPIO input state to increase number of distinct values represented by a limited number of GPIOs. The three states are - external pull down (interpreted as 0) - external pull up (1) - not connected (2) This has been required by Nvidia devices so far, but Exynos and Ipq8086 platforms need this too. This patch moves the function reading the tertiary state into the library and exposes the necessary GPIO API functions in a new include file. The functions are still supposed to be provided by platform specific modules. The function interpreting the GPIO states has been modified to allow to interpret the state either as a true tertiary number or as a set two bit fields. Since linker garbage collection is not happening when building x86 targets, a new configuration option is being added to include the new module only when needed. BUG=chrome-os-partner:30489 TEST=verified that nyan_big still reports proper revision ID. Change-Id: Ib55122c359629b58288c1022da83e6c63dc2264d Original-Change-Id: I243c9f43c82bd4a41de2154bbdbd07df0a241046 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/209673 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit c79ef1c545d073eaad69e6c8c629f9656b8c2f3e) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/8717 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-23rush: Add MMC supportFurquan Shaikh
BUG=None BRANCH=None TEST=Compiles successfully. Depthcharge is able to see mmc. Original-Change-Id: Ia0c9b432fa447c64fa13e5fae5a66a26bbc86360 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/210002 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 4cb05ffa95a2a36c5b4606d2f0efe9e574b84e1d) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I7f9a27a4c0f0553e78fc1a289bffebbebd37c099 Reviewed-on: http://review.coreboot.org/8716 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-03-23t132: Add support for tpm i2cFurquan Shaikh
Iniitialize I2C bus required for TPM operation. Problem observed was that if frequency is raised above 20KHz, TPM starts responding with NAKs either for address or for data. Need to look into that. BUG=None BRANCH=None TEST=Compiles successfully and TPM success messages seen while booting. Original-Change-Id: I9e1b4958d2ec010e31179df12a099277e6ce09e0 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/210001 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 01e87ae35431147f442e3f3e531537b8f0de1c9d) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I7dddc39d77f9a726fa51dd58ea9b7712c9a6fae2 Reviewed-on: http://review.coreboot.org/8715 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-03-20romstages: use common run_ramstage()Aaron Durbin
Instead of sprinkling the cbfs calls around (as well as getting return values incorrect) use the common run_ramstage() to perform the necessary work to load and run ramstage. Change-Id: I37b1e94be36ef7a43efe65b2db110742fa105169 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8710 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-18bootstate: use structure pointers for scheduling callbacksAaron Durbin
The GCC 4.9.2 update showed that the boot_state_init_entry structures were being padded and assumed to be aligned in to an increased size. The bootstate scheduler for static entries, boot_state_schedule_static_entries(), was then calculating the wrong values within the array. To fix this just use a pointer to the boot_state_init_entry structure that needs to be scheduled. In addition to the previous issue noted above, the .bs_init section was sitting in the read only portion of the image while the fields within it need to be writable. Also, the boot_state_schedule_static_entries() was using symbol comparison to terminate a loop which in C can lead the compiler to always evaluate the loop at least once since the language spec indicates no 2 symbols can be the same value. Change-Id: I6dc5331c2979d508dde3cd5c3332903d40d8048b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8699 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-17rush: Update rush Kconfig fileFurquan Shaikh
Update rush Kconfig file to include TPM and RAMSTAGE_INDEX options BUG=None BRANCH=None TEST=Compiles successfully. TPM works. Ramstage boots successfully. Original-Change-Id: Ie55260c710ffcb6a2e04c8658ca6dd3cdec6b6db Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209978 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 0088f5aade8533c6ed235de25934d47cd0743a67) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I5c4a54b74546de73eee7e7bae072cc712ce1838f Reviewed-on: http://review.coreboot.org/8680 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-17rush: Add ec_dummy file to enable vboot compilationFurquan Shaikh
BUG=chrome-os-partner:30784 BRANCH=None TEST=Compiles successfully for rush Original-Change-Id: Ic11bef85e5c7635000582f87727cd9a33b0b36e3 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209975 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 3d3f0494d8758ef5040384f63d023c042686bd2c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie15781d10a366b68f0db97378ccb348a4f074995 Reviewed-on: http://review.coreboot.org/8679 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-17rush: Pull in chromeos.c from nyan into rushFurquan Shaikh
Hardcoded values are set for developer,recovery mode. Change as per requirements BUG=chrome-os-partner:30784 BRANCH=None TEST=Compiles succesfully for rush Original-Change-Id: Ied506a9d1c4e0ba8ee06d57c6ca8c726220998b5 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209974 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 2e6934d47c5b4bb98e60486202b230bae79d927b) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I36e384b0d331fdd9e3f47954decfddaf4f31aed3 Reviewed-on: http://review.coreboot.org/8678 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-16coreboot: rk3288: Add a stub implementation of the rk3288 SOCjinkun.hong
Most things still needs to be filled in, but this will allow us to build boards which use this SOC. BUG=chrome-os-partner:29778 TEST=emerge-veyron coreboot Original-Change-Id: If643d620c5fb8951faaf1ccde400a8e9ed7db3bc Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205069 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 2f72473a8c2b3fe21d77b351338e6209035878fb) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I53fd0ced42f6ef191d7bf80d8b823bb880344239 Reviewed-on: http://review.coreboot.org/8653 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-15google/butterfly: Drop MRC.bin in favor of native raminitAlexandru Gagniuc
I thought this wasn't going to work, and observing the timC detection failure of early tests, I was getting somewhat discouraged; however, this works. I've tried it with all possible permutations of the following memory modules: * 2 GiB single-rank DDR3-1600 * 4 GiB single-rank DDR3-1600 * 4 GiB dual-rank DDR3-1600 I did notice a limited number of memtest errors during one of the runs, but they were in an address range that is otherwise marked as reserved. I wrote that off as "maybe something was doing MMIO there just when memtest was poking the address range". I was not able to reproduce that error. Change-Id: Ibd52e1d52fc8d900591d6a488f9a5b4d1e5e4fd3 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/8477 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2015-03-13Use a common boardid.h instead of per board copiesVadim Bendebury
There is no point in duplicating boardid.h per board - they are all the same. Let's keep a single instance in the common include directory and let the linker report a problem if one tries using this function on a board where it is not supported. BUG=chrome-os-partner:30489 TEST=verified that coreboot builds fine for nyan_big and nyan_blaze. Original-Change-Id: Ifbe9c2287a1d828d4db74c637d1d02047ac4da25 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/209699 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 589e6415faf18ca6aaf44da343dd33eadc8a53d3) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I8eef89cb822611a0050e5a50fc4b970eebd8d962 Reviewed-on: http://review.coreboot.org/8666 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-13nyan: Remove broken setup_display() from romstageJulius Werner
This patch removes a chunk of romstage code from Tegra and all Nyan boards that was supposed to enable some LCD power rails early, but never really worked. The dev_find_slot() function can only find PCI devices, which the CPU cluster is not. Since we're done with Nyan-RO and the ramstage display code is fine as it is, there is no point in trying to fix this... but we should remove it from ToT lest someone uses it as a blueprint to add more dead code to future boards. BRANCH=None BUG=None TEST=None Original-Change-Id: I6eee256873299429d4e3934fe7d454120390f34d Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207720 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit a3df62a3bcefcc20ae59648f5d1f0a01db3c02c6) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I8deedea5e9787848aae3064509c611bc349313cc Reviewed-on: http://review.coreboot.org/8638 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-03-13ryu: Add TPS65913 regs/init for VDD_CPU 1.0VTom Warren
Other default slams should be added later to the init table once we know what the kernel touches. But for now, only VDD_CPU is needed. Also slipped in a minor name change in mainboard.c BRANCH=none BUG=none TEST=none, no HW here for me to test on yet Change-Id: Ifbe86192449ed0466085808a0a12a15a7b6a1795 Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-on: https://chromium-review.googlesource.com/208385 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 53b332fb12cd685fbec265695333a70c4064524c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/8645 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-13ryu: Add support for full LPDDR3 SDRAM BCT init via BootROMTom Warren
Once LPDDR3 init is supported in the ryu romstage, this can be reverted. Note that this 528MHz BCT has been pre-qualed by NVIDIA AE's, but will be updated as more tuning is done. BUG=none BRANCH=none TEST=Builds, BCT is in binary, but I have no HW here to test on Original-Change-Id: I315a9a5d56290bb5f51863b15053d2171db7b1e4 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/208384 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 660e40cb473d47ce763e79d6061367bf381a1c48) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I29ad31fc83f45ca8f92809a7dc252cf984c8c6fe Reviewed-on: http://review.coreboot.org/8643 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-03-10ARM romstages: Support and fix COLLECT_TIMESTAMPSKyösti Mälkki
Change-Id: I53959eb937c1db3c4211e23a6476340383a33c5b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8021 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2015-03-09google/samus/acpi/mainboard.asl: Correctly align commentPaul Menzel
Fix up commit 00aedc5e (samus: add acpi resource for supporting RT5677 codec). Change-Id: I98b8c6f1a46f9f3bfd79da92bb070cebe8f20dc0 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/8234 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-05storm: Provide ability to build ap148 variantVadim Bendebury
With BOARD_VARIANT_AP148 configuration option enabled the image will be built for 512MB DRAM instead of 1024MB and the mainboard_part_number field in the lb_mainboard entry will be set to "AP148" instead of "Storm". BUG=chrome-os-partner:30440 TEST=manual . built and booted both AP148 and proto0 all the way to reading the kernel . verified that the config file includes correct part number and memory size . verified proper machine IDs reportted when starting the kernel Original-Change-Id: Ie609544a460fc991e66e8b95e8d7a3ed5e845f7b Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207427 Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit a80ab00f27eef9e3aa2f761659d6945d6fce2ef6) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I477e672dc4f48fa9c9893bf0759704501ea07b1a Reviewed-on: http://review.coreboot.org/8590 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-03-05rush_ryu: Add new mainboardAaron Durbin
This is a clone of rush for the time being. All the incompatible bits can be moved later. Additional patches to follow. BUG=chrome-os-partner:30569 BRANCH=None TEST=Built coreboot for rush_ryu board Original-Change-Id: Iae56d016d0c328d83242b95f307fefaa8c68deec Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207838 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit cf2b88963743e40a35d841ef522172cb2448abbf) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I92a8b4d31fac4a25e3afa3b6e158e1dba0f80aab Reviewed-on: http://review.coreboot.org/8594 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-05t132: bring up 64-bit denver coreAaron Durbin
The startup sequence for cpu0 is implemented while also providing a trampoline for transitioning to 64-bit mode because the denver cores on t132 come out of cold reset in 32-bit mode. Mainboard callbacks are provided for providing the board-specific bits of the bringup sequence. BUG=chrome-os-partner:29923 BRANCH=None TEST=Built and booted through ramstage. Original-Change-Id: I50755fb6b06db994af8667969d8493f214a70aae Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207263 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Stefan Reinauer <reinauer@google.com> (cherry picked from commit 17f09bf4bdb43986c19067ca8fd65d4c5365a7c6) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I14d99c24dd6e29a4584c8c548c4b26c92b6ade97 Reviewed-on: http://review.coreboot.org/8586 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04rush: PMIC: initial AS3722 PMIC writes for RushTom Warren
Still waiting on VDD_CPU value, etc. from board guys, but this is a start. BUG=None BRANCH=None TEST=Built and flashed rush, saw 'PMIC init done' string OK. Original-Change-Id: I6f8b16c4ebf1e9c159f8175d59262119ef0e498f Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/206412 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 96a9ff8f632c2b9bf3f81f5b8fc4f3b6784a02bc) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I9d3d7ff55f2d6ca88ebdcc8ad1d7de135f5136d2 Reviewed-on: http://review.coreboot.org/8582 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04rush: enable 128MiB MTS carveout below top of DRAMAaron Durbin
The recommended settings for the size of the MTS region is 128MiB. Therefore, provide this region 128MiB below the top of DRAM for each configuration. BUG=chrome-os-partner:29922 BRANCH=None TEST=Built and noted MTS carveout region at expected location. Original-Change-Id: Iac17f210dfef8e8a36617c7b3dceba8c2134ee9b Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/206291 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit f1758c74330afe9dd7eaa8ff1fef5e4d18ed14ad) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I369a3897e31f3126d031d3582f52f9892350f658 Reviewed-on: http://review.coreboot.org/8579 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04t132: Add shared romstageAaron Durbin
There's no reason to duplicate code in the mainboards. Therefore, drive the flow of romstage boot in the SoC. This allows for easier scaling with multiple devices. BUG=None BRANCH=None TEST=Built and booted to same place as before. Original-Change-Id: I0d4df84034b19353daad0da1f722b820596c4f55 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/205992 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit de4310af6f6dbeedd7432683d1d1fe12ce48f46e) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie74f0eb1c983aff92d3cbafb7fe7d9d7cb65ae19 Reviewed-on: http://review.coreboot.org/8575 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04coreboot rush: Add dram init codeFurquan Shaikh
Add support for initializing dram within romstage. This is an essential before we move to the armv8 core. BUG=None BRANCH=None TEST=Compiles succesfully for rush. Tried writing to and reading value from the base of sdram and it worked fine. Also tested with primitive_memtest CL: https://chromium-review.googlesource.com/#/c/186309/5 Original-Change-Id: I67ec04c766e249c9727b0cf2ba216522c862c2f5 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205823 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 33c468b16e7ccd8cf9266d6a9ca30c02da104821) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I4baface2c109ca74f85f43a25508677c46c64159 Reviewed-on: http://review.coreboot.org/8574 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04coreboot rush: Add support for basic romstageFurquan Shaikh
Add basic romstage support for rush. Since, dram init needs to be done before we can jump to armv8 core, romstage will run on armv4 core as well. Thus, correcting the compiler selection options. BUG=None BRANCH=None TEST=Compiles successfully for rush. Prints romstage banner and initial printk Original-Change-Id: Ie3cd290e56a712b07c1503dab199e4e34cec04d2 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205763 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit d20b4e66209e902f54a07a17d5ce741f0a0b3a7b) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ic6b7ef4a2ea01c95d0c7f040bbd079219cf5750a Reviewed-on: http://review.coreboot.org/8573 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-04coreboot t132: Enable loading of romstage from CBFS mediaFurquan Shaikh
Add proper Kconfig options and initialize cbfs media to enable loading of romstage BUG=None BRANCH=None TEST=Compiles successfully for rush and cbfs_load_stage returns entry pointer for romstage Original-Change-Id: If62edcdc0496d89d30003ffd7b827b77835910fd Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205762 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit c89c05bc86fd6c1e49fbed5e0730659b64bffc6c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I68c10171424c85605b5065a19634d3c5dd639b78 Reviewed-on: http://review.coreboot.org/8572 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04coreboot t132,rush: Add mainboard specific bootblock_initFurquan Shaikh
Pull in mainboard specific bootblock_init function from nyan into rush. Additionally, pull in all files required for proper compilation of rush after adding the bootblock_init function BUG=None BRANCH=None TEST=Compiles successfully for rush Original-Change-Id: I69c736275f66eca3ad92f97d166e91d4c2301364 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205583 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit e7aac547026717d7380f71593010e3ea34ecea51) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie26f91f8caaa06af3b195246febcdc70b9fe9795 Reviewed-on: http://review.coreboot.org/8570 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-02-25rush: Correct version field to match t132Aaron Durbin
The version field for t132 cpus is 0x00130001. Update it to the correct version. BUG=chrome-os-partner:29882 BRANCH=None TEST=Built and was able to see serial with subsequent changes. Original-Change-Id: I39d560307261fdfc34e071f5c35a4397c134e03c Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/205435 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 14916b3ba5545ab2cb35b6a4a7fa231b895ede46) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I785069d3eb82ed24bafd52ef627d53505a35c09a Reviewed-on: http://review.coreboot.org/8467 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-17google/rush: Add BCT support in mainboard rushFurquan Shaikh
Changes might be required for .bct files as we get to know more. Pulling in files from mainboard nyan for now BUG=None BRANCH=None TEST=Compiles successfully for rush Change-Id: Iaf81a384af0469c77940cf7309ba68018110b5eb Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/203144 Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit d3633f8cf8c01a07b54ceef2dd7bf7a64afd7c76) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/8412 Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-02-16mainboard/cmos: Delete obsolete commented parametersTimothy Pearson
Change-Id: Iccad79c142a7fcf89dd0fbebe8c07ad9ef019e91 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8459 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-02-15x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointerKevin Paul Herbert
On x86, change the type of the address parameter in read8()/read16/read32()/write8()/write16()/write32() to be a pointer, instead of unsigned long. Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330 Signed-off-by: Kevin Paul Herbert <kph@meraki.net> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/7784 Tested-by: build bot (Jenkins)
2015-01-27CBMEM: Move cbmemc_reinit()Kyösti Mälkki
This replaces need for separate cbmemc_reinit() calls made via CAR_MIGRATE() and in ramstage. Change-Id: If7b4d855c75df58b173f26ef3c90a4a7563166d3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7859 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2015-01-27vboot2: read dev and recovery switchDaisuke Nojiri
TEST=Built with VBOOT2_VERIFY_FIRMWARE on/off. Booted Nyan Blaze. BUG=none Branch=none Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: Ia5353018a0db3dae2e0432b7e6a34d46f81b0ffa Original-Reviewed-on: https://chromium-review.googlesource.com/206064 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit b420451c71c86bc27784d920f53870ee56ddc0f2) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I30c9f0ac44de0a5816b5b8d0ded2dc7d7e77c7a1 Reviewed-on: http://review.coreboot.org/8162 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-01-27vboot2: implement select_firmware for pre-romstage verificationDaisuke Nojiri
This patch has a basic structure of vboot2 integration. It supports only Nyans, which have bootblock architecture and romstage architecture are compatible from linker's perspective. TEST=Built with VBOOT2_VERIFY_FIRMWARE on/off. Booted Nyan Blaze. BUG=None BRANCH=none Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: I4bbd4d0452604943b376bef20ea8a258820810aa Original-Reviewed-on: https://chromium-review.googlesource.com/204522 Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit a6bce0cbed34def60386f3d9aece59e739740c58) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I63ddfbf463c8a83120828ec8ab994f8146f90001 Reviewed-on: http://review.coreboot.org/8160 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-01-26rush: Add support for rush boardFurquan Shaikh
Add basic support for rush board BUG=None BRANCH=None TEST=Compiles successfully with soc tegra132 and armv8 arch selected for romstage and ramstage Original-Change-Id: Ica57c68d230e4e0e9916729752395843de188733 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/197399 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 06a040dc320d7b04ec0f7e51c1b3987c8f6d80f3) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ica57c68d230e4e0e9916729752395843de188733 Reviewed-on: http://review.coreboot.org/8041 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-01-19samus: Update indices of ramstage and refcode blobsRandall Spangler
This must be committed at the same time as the corresponding depthcharge change which updates the fmap. BUG=chrome-os-partner:30079 BRANCH=none TEST=Build samus firmware. dump_fmap -h /build/samus/firmware/image.bin shows PD_MAIN_A and PD_MAIN_B sections. Boot samus. 'crossystem mainfw_act' -> A As root, 'crossystem fwb_tries=1' Reboot samus. 'crossystem mainfw_act' -> B CQ-DEPEND=CL:208984,CL:*169850,CL:208989 Original-Change-Id: Ibccec8b82ba22c61248a79023f42b92e4763403e Original-Signed-off-by: Randall Spangler <rspangler@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208899 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit d241e1dddaf8a435e49e08e60e4ad998735d2137) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ida8f7bd68d71e2a4a47e304b8f8283b566c52837 Reviewed-on: http://review.coreboot.org/8219 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-01-19samus: Delay bringing SSD out of resetDuncan Laurie
In order to ensure that we meet timing requirements for the SSD power sequencing delay bringing the SSD out of reset until after memory training. BUG=chrome-os-partner:29914 BRANCH=None TEST=build and boot on samus Original-Change-Id: I807e3d3698255287c3fe7219f44e8ec9a0985df1 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208155 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 1cf557049c49e1ba11ade1eee7a45fc2b075ff3d) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ib39a14a03e04a167fab45b58b3bc840eb4bcf317 Reviewed-on: http://review.coreboot.org/8215 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-01-19samus: Disable self refresh and MRC cache on broadwellDuncan Laurie
Add workarounds for power and/or lpddr3 issues on Broadwell SKU. BUG=chrome-os-partner:29787,chrome-os-partner:29117 BRANCH=None TEST=build and boot on samus Original-Change-Id: If99346212c10ad6026250e48bedd916611e2cb8c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208154 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit c3ee57114315320b542f53645ffb168ad654b756) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie28f3ad65000a627ba64486e0f16493e8101cef3 Reviewed-on: http://review.coreboot.org/8214 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-19samus: Enable keyboard backlightDuncan Laurie
- Turn on keyboard backlight early in boot (not resume) path as a sign of life for the system - Add ACPI device for keyboard backlight so the kernel can find and make use of it BUG=chrome-os-partner:30586 BRANCH=None TEST=build and boot on samus Original-Change-Id: Iecaef0ec5c814774e19d7c4a14cb92dc236cfee3 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208152 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit e166f76f9bd167468c7637dcce2b9eabf7dce8f0) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I47927d97c1586ec09310d014d8fba7d7a3d773c4 Reviewed-on: http://review.coreboot.org/8213 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2015-01-19samus: add acpi resource for supporting RT5677 codecKane Chen
Add codec acpi resource for supporting RT5667 codec. BUG=chrome-os-partner:29649 TEST=emerge-coreboot successfully checked codec device is probed Original-Change-Id: I739c0dbfdbfa221b06f99c3d934825b640096c6b Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/207707 Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit f9698c45a47efe7fd2a1f5432640f3db5e4bd3f0) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ib14b27421613d747e02037ecd2311d9966a5d813 Reviewed-on: http://review.coreboot.org/8212 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-01-16rambi: configure USBPHY_COMPBG by the setting in devicetree.cbKane Chen
USBPHY_COMPBG needs to be configured by project BUG=chrome-os-partner:30690 BRANCH=none TEST=emerge-rambi coreboot without problem checked the USBPHY_COMPBG is configured properly CQ-DEPEND=CL:208557 Original-Change-Id: I8f2714644e1ef5d790d7ef1f574ebb998abbdac6 Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/208731 Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> (cherry picked from commit 1e9aeebb769e30940175cf3c38afe7ecfa69b5b4) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I28aa445ccb4506db65784e30253dd16161b2bc75 Reviewed-on: http://review.coreboot.org/8217 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-13 18:59:40 +0000