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2019-11-18nb/intel/sandybridge: Set up console in bootblockArthur Heymans
Change-Id: Ia041b63201b2a4a2fe6ab11e3497c460f88061d1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-18nb/intel/sandybridge: Move to C_ENVIRONMENT_BOOTBLOCKArthur Heymans
There is some overlap between romstage and bootblock. LPC setup and BAR initialization is now done twice. The rationale is that the romstage should not depend too much on the bootblock, since it can reside in a RO fmap region. Enabling the console will be done in a followup patch. Change-Id: I4d0ba29111a5df6f19033f5ce95adcc0d9adc1fd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-18sb/intel/bd82x6x: Make the pch_enable_lpc hook optionalArthur Heymans
This also changes the name to mainboard_pch_lpc_setup to better reflect that it is an optional mainboard hook. This adds an empty weakly linked default. The rationale behind this change is that without an implementation of the hook some features might not work but that the result is likely still able to boot, so it can be made optional. Change-Id: Ie8e6056b4c4aed3739d2d12b4224de36fe217189 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-18nb/intel/sandybridge: Make the mainboard_rcba_config hook optionalArthur Heymans
This also changes the name to mainboard_late_rcba_config to better reflect what it does. This adds an empty weakly linked default. The rationale behind this change is that without an implementation of the hook some features might not work but that the result is likely still able to boot, so it can be made optional. Change-Id: I1897d0f5ca7427d304a425f5256cd43c088ff936 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-18nb/intel/sandybridge: Make the mainboard_early_init hook optionalArthur Heymans
This adds an empty weakly linked default. The rationale behind this change is that without the callback some features might not work but that the result is likely still able to boot, so it can be made optional. Change-Id: I62c8010aa81fc45d208e9293feb2f45b45f34a82 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-16kohaku: Set GPP_A10 to NCShelley Chen
Setting GPP_A10 to NC now that older boards are deprecated and this GPIO is not in use anymore. BUG=b:142056166 BRANCH=hatch TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: If8a249a3dcba90bb4ccb5e3f02595e680f789f93 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36869 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-15mb/google/kukui: Add new board 'kakadu'Hung-Te Lin
Add a new Kukui follower 'kakadu'. BUG=None TEST=make # select kakadu Change-Id: I9f25ce90285828c43435e45d9361ee7128d407fa Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36848 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-15mb/google/octopus/variants/bobba: Add SX9310 sensor to devicetreeSheng-Liang Pan
Add semtech SAR sensor. BUG=b:143449140 BRANCH=octopus TEST=Boot kernel with sx931x driver, i2cdetect show UU on slave address. Change-Id: Icfb8acf1bac73973748aa7443c95147c60bad770 Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36850 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-15mb/google/octopus/variants/bobba: support LTE power sequenceSheng-Liang Pan
GPIOs related to power sequnce are GPIO_67 - EN_PP3300 GPIO_117 - FULL_CARD_POWER_ON_OFF GPIO_161 - PLT_RST_LTE_L 1. Power on: GPIO_67 -> 0ms -> GPIO_117 -> 30ms -> GPIO_161 2. Power off: GPIO_161 -> 30ms -> GPIO_117 -> 100ms -> GPIO_67 3. Power reset: - keep GPIO_67 and GPIO_117 high and - pull down GPIO_161 for 30ms then release it. BUG=b:144327240 BRANCH=octopus TEST=build image and verify on the DUT with LTE DB. Change-Id: I68b71425391eda1e92806fecdb9c8dcd54f0b95a Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36771 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Henry Sun <henrysun@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-15vboot: use vboot persistent contextJoel Kitching
vb2_context object is now stored on the workbuf as part of vb2_shared_data. Use vboot's new API functions vb2api_init and vb2api_relocate to create and move the workbuf. BUG=b:124141368, chromium:994060 TEST=Build locally BRANCH=none Change-Id: I051be1e47bf79b15a1689d49a5d4c031e9363dfa Signed-off-by: Joel Kitching <kitching@google.com> Also-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/1902339 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2019-11-14soc/qualcomm: Link cbmem.c only in romstageArthur Heymans
Change-Id: I008fcca024fecf462c4b550b8dedbf4b06e491b8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36368 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-14/mb/google/hatch: clean manufacturing information in spdWisley Chen
Clean the vendor/manufacturing information in 16G_3200_4bg spd to become generic spd. BUG=None TEST=emerge-hatch coreboot Change-Id: I163dc4631a6b71efd36c75cfe1fc759040113387 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36810 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-14/mb/google/hatch/var/dratini: Add new memory supportWisley Chen
1. ram id 8: 16G 2666 2 bank groups memory 2. ram id 9: 16G 3200 4 bank groups memory BUG=b:142762387 TEST=boot with memory (KAAG165WA-BCT/H5ANAG6NCMR-XNC) Change-Id: Ic63d911458b59de11c12ce776f6f7d04b1eb3b6c Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36667 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-13mb/google/hatch/variants/helios: Fix leakage voltage problem on touchscreenKane Chen
Set GPP_C4 default to low to fix leakage voltage problem on touchscreen during power on. BUG=b:142368161 BRANCH=Master TEST=emerge-hatch coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, and make sure touchscreen works. Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: Ie9197192c9d6dfb30c10559990c6010b1b2d3a45 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36670 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-12mainboard/google/hatch: Create helios_diskswap variantAlexis Savery
Created helios_diskswap as a variant of helios (hatch variant). BUG=b:143378037 BRANCH=None TEST=none Change-Id: I6536b3908ec569e1ac42ea7c5be85701012ab177 Signed-off-by: Alexis Savery <asavery@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-11-12/mb/google/hatch: add new memory config supportWisley Chen
1. Add 16G 2666 2 bank group 2. Add 16G 3200 4 bank group BUG=b:142762387 TEST=boot with memory (KAAG165WA-BCT/H5ANAG6NCMR-XNC) Change-Id: I04810091ef2bf8ec1bd306ad141a70436638eac8 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-11-12mb/google/kukui: Add new configs 'damu' and 'kappa'Hung-Te Lin
New boards introduced to Kukui family. BUG=None TEST=make # select damu and kappa Change-Id: I7154aeee921114b7d12bf586adca250df19a3883 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-11-11mb/{google/fizz,razer/blade_stealth_kbl}: Add missing include ↵Elyes HAOUAS
<console/console.h> Change-Id: Ia4e496d359036591131c1ec0243d64c58823ca63 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-11Helios: Set the reset delay for Goodix touchscreen to 120msShelley Chen
With the 0.71586+ Goodix FW, we can reduce the reset delay from 500ms to 120ms. We should do the change in coreboot device tree after we ensure Helios DVT build is flashed with 0.71586+ Goodix FW. BUG=b:142316026 BRANCH=None TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I000ee4ea84c598b437992f1000f6e5b561cae605 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philip Chen <philipchen@google.com>
2019-11-09arch/x86: Replace some __SMM__ guardsKyösti Mälkki
We generally do not guard source in attempts to reduce the final object sizes, but rely on garbage collection. Most of the __unused attributes inserted here will be removed when remaining __SIMPLE_DEVICE__ guards can be removed. Change-Id: I2440931fab4f41d7e8249c082e6c9b5a9cd0ef13 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36641 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-09ELOG: Introduce elog_gsmi variantsKyösti Mälkki
This avoids a lot of if (CONFIG(ELOG_GSMI)) boilerplate. Change-Id: I87d25c820daedeb33b3b474a6632a89ea80b0867 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36647 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-08google/stout: Remove ELOG_GSMI from ECKyösti Mälkki
EC_HOST_EVENT_xxx are only defined with ec/chromeec. Change-Id: Ie0a1349ab460142dc2744155a422b5ee22528e4c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-08google/parrot: Remove ELOG_GSMI from ECKyösti Mälkki
EC_HOST_EVENT_xxx are only defined with ec/chromeec. Change-Id: Idf7b04edc3fce147f7857691ce7d6a0ce03f43fe Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-08arch/x86: Drop some __SMM__ guardsKyösti Mälkki
Change-Id: I64063bbae5b44f1f24566609a7f770c6d5f69fac Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-08mb/google/hatch/var/akemi: disable unused USB port for Akemi platformPeichao Wang
Akemi platform dosen't support WWAN device and unused USB2 port 3, 4, 5, 7, 8 and USB3 port 3, 4, 5 so close them. BUG=None TEST=FW_NAME="akemi" emerge-hatch coreboot chromeos-ec chromeos-bootimage Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I7eff4da77caea7d4fe46597320be134d34d78a22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-11-07hatch: Create puff variantEdward O'Callaghan
Includes: - gpio mappings, - overridetree.cb, - kconfig adjustments for reading spd over smbus. V.2: Rework devicetree with comments and drop some useless gpio maps. BUG=b:141658115 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I6449c4fcc1df702ed4f0d35afd7b0981e4c72323 Signed-off-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-11-07mainboard/google: Allow Hatch variants to read SPD data over SMBusEdward O'Callaghan
All Hatch variants so far embed static SPD data encoded within the firmware image. However we wish the flexibility for romstage implementations that allow for reading the SPD data dynamically over SMBus. This romstage variant allows for reading the SPD data over SMBus. V.2: Dispence with memcpy(). V.3: Revert back to previous patch with memcpy(). V.4: Rewrite again to avoid memcpy(). BRANCH=none BUG=b:143134702 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I3516a46b91840a9f6d1f4cffb2553d939d79cda2 Signed-off-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36449 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-07mb/google/hatch/variants/helios: Modify touchscreen power on sequenceKane Chen
The previous values do not affect the touchscreen function. But, the previous values cause the power leakage in S0ix. from b/142368161: 1. Modify GPP_D: The specification define T1 >= 10ms. We change it to 12ms for a safety and low impact value in our mind. Enable pin as GPP_D9 is define to be AVDD in specification. Set it to 10ms to make it to be the final one to pull low during power off sequence . 2. Add GPP_C4: If we set stop_off_delay_ms to be 1. The true T4 we got will be 300us . Set stop_off_delay_ms to be 2 . True T4 will be 500us . So we change it to 5 to be a low impact value in our mind according to the true T4 value we got . BUG=b:142368161 BRANCH=Master TEST=emerge-hatch coreboot chromeos-bootimage ./util/abuild/abuild -p none -t google/hatch -x -a Signed-off-by: YenLu Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I86c920ff1d5c0b510adde8a37f60003072d5f4e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35907 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-06mb/g/drallion: Override smbios enclosure type for drallionMathew King
Drallion can be either a clamshell or convertible depending on the presence of the 360 sensor board. Set the smbios type 3 enclosure type to either CONVERTIBLE or LAPTOP accordingly. BUG=b:143701965 TEST='dmidecode -t 3' Type = Convertible with sensor board connected Type = Laptop with sensor board disconnected Change-Id: I766e9a4b22a490bc8252670a06504437e82f72d5 Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36512 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-06mb/g/drallion: Consolidate 360 sensor board detectionMathew King
Create a single function to determine if the 360 sensor board is present on a device. BUG=b:143701965 TEST='emerge-drallion coreboot' Change-Id: I4100a9fdcfe6b7134fb238cb291cb5b0af4ec169 Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2019-11-06mainboard/google: Rework Hatch so that SPD in CBFS is optionalEdward O'Callaghan
All Hatch variants so far embed static SPD data encoded within the firmware image. However we wish the flexibility for romstage implementations that allow for reading the SPD data dynamically over SMBus. BRANCH=none BUG=b:143134702 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: Ie1637d08cdd85bc8d7c3b6f2d6f386d0e0c6589b Signed-off-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-05mb/google/hatch/variants/helios: Update TSR3 sensor thresholdsSumeet Pawnikar
Update thermal threshold settings for TSR3 sensor. There is an issue fan is always running, even during system idle state. This change fixes this issue and fan starts only when it breaches the temperature threshold. BRANCH=None BUG=b:143861559 TEST=Built and tested on Helios system Change-Id: Ia417f8c51442005cc8c2251c188cebc197e0a773 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36609 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-05mb/google/kahlee/treeya: Update STAPM parameters for TreeyaPeichao Wang
Tune stapm percentage from 80 to 68 and time from 250 second to 90 second make them meet Lenovo temperature spec. BUG=b:143859022 TEST=build firmware and install it to DUT and run fishbowl 1000, check temperature whether meets spec. Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I254140c9d242ed918b3b689d4fb4a1d0e871cd55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2019-11-04google/auron: hook up libgfxinitMatt DeVillier
Internal/external displays functional on all variants other than Samus. Unable to verify external outputs on Samus (USB-C using DP/HDMI adapter). Test: build/boot lulu variant with libgfxinit, verify internal/ external displays functional prior to OS display driver loaded. Both linear framebuffer and scaled VGA text modes functional. Change-Id: I867b2604861ebae02936e7fc0e7230a6adcb2d20 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-04soc/intel/sgx: convert SGX and PRMRR devicetree options to KconfigMichael Niewöhner
The devicetree is not made for user-choosable options, thus introduce Kconfig options for both SGX and the corresponding PRMRR size. The PRMRR size Kconfig has been implemented as a maximum value. At runtime the final PRMRR size gets selected by checking the supported values in MSR_PRMRR_VALID_CONFIG and trying to select the value nearest to the chosen one. When "Maximum" is chosen, the highest possibly value from the MSR gets used. When a too strict limit is set, coreboot will die, printing an error message. Tested successfully on X11SSM-F Change-Id: I5f08e85898304bba6680075ca5d6bce26aef9a4d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-04mb/google/hatch: update DLL values for KindredJamie Chen
Update emmc DLL values for Kindred BUG=b:131401116 BRANCH=none TEST=Boot to OS 100 times on Kindred EVT Change-Id: Ibd840b31bb0e5a742495758de55b532e6c3946aa Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com>
2019-11-04mb/*/*/others: Use sb/intel/common/acpi/platform.aslArthur Heymans
Change-Id: Iabfd680fdb50534e6b9f6cfdecda9f8de0f8a610 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-04sb/intel/lynxpoint: Use sb/intel/common/platform.aslArthur Heymans
Change-Id: I86260a374a3f60f16dc73573e7989f0a4ffec818 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-04include: Remove EC_EVENT_* from elog.hYu-Ping Wu
All of the EC_EVENT_* macros can be replaced with the EC_HOST_EVENT_* macros defined in ec_commands.h, which is synchronized from Chromium OS ec repository. BRANCH=none BUG=none TEST=emerge-kukui coreboot Change-Id: I12c7101866d8365b87a6483a160187cc9526010a Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-11-04mb/*/*{bd82x6x/ibexpreak}: Use sb/intel/common/acpi/platform.aslArthur Heymans
Change-Id: I36095422559e6c160aa57f8907944faa4c192dee Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-04mb/google/drallion: Update GPIO tableEric Lai
Follow latest GPIO table to change gpio. BUG=b:143728355 BRANCH=N/A TEST=build pass Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Iee61c74a5cab5a62a90c0543f212650c4f2420de Reviewed-on: https://review.coreboot.org/c/coreboot/+/36524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2019-11-04mb/google/drallion: Correct GPP_E7 as stop pinEric Lai
Current design reset pin is connected to PLTRST. GPP_E7 is stop pin for touch. Reserve reset pin for next stage implement. BUG=b:143733039 BRANCH=N/A TEST=check touch screen can work properly Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I3ebd56ab49b87da425583da04f082e69293a023e Reviewed-on: https://review.coreboot.org/c/coreboot/+/36535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2019-11-04mb/google/drallion: fix GPP_E16 glitch when enter S5Eric Lai
Set GPP_E16 reset to DEEP. BUG=b:143057255 BRANCH=N/A TEST=Measure GPP_E16 from S0 to S5 has no glitch Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I63932c6f5c8b7e6e9ab8aa55e69c629d29e7d1fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/36511 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-01mb/google/drallion: Add second touch pad supportEric Lai
Add second source touch pad with i2c address 0x15. BUG=b:142629138 BRANCH=N/A TEST=check new touch pad can work properly Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Icc58dbcf307f11c368a1a5408f32111ed5841d39 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36501 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-by: Mathew King <mathewk@chromium.org>
2019-11-01soc/intel/{cnl,icl}: Move globalnvs.asl/nvs.h into common/block/Subrata Banik
This patch creates a common instance of globalnvs.asl/nvs.h inside intel common code (soc/intel/common/block/) and ask cnl & icl soc code to refer globalnvs.asl and nvs.h from common code block. TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify GNVS operation region presence after booting to OS. Change-Id: Ia9fb12a75557bd7dc38f6d22ba2b32065d18b3ee Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-01soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpiSubrata Banik
This patch creates a common instance of sleepstates.asl inside intel common code (southbridge/intel/common/acpi) and asks all IA CPU/SOC code to refer sleepstates.asl from common code block. TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify S0/S3/S4/S5 entries after booting to OS. Change-Id: Ie2132189f91211df74f8b5546da63ded4fdf687a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36463 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-01mb/google/kukui: Unselect FATAL_ASSERTElyes HAOUAS
FATAL_ASSERT is used for debugging purpos. Don't select it by default. Change-Id: If4d521827f3d50fb662b89b24d00fb0517e7af2d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-11-01trogdor: Add mainboard gpio supportT Michael Turney
Change-Id: I06cdb8eaaf7f74b47e1d1283dcaa765674ceaa45 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36070 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-31mb/google/drallion: Turn off HDMI power when enter s0ix and S5Eric Lai
Turn off HDMI power when enter s0ix and S5. BUG=b:143057255 BRANCH=N/A TEST=Measure the power on GPP_E16 under s0ix and S5 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I580e6094d48663d5c208fd82c7744485d899bcc1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36224 Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-30mb/google/hatch/variants/helios: Modify DPTF parametersKane Chen
Modify DPTF parameters. Modify TDP PL1 values to 15. Remove TCHG Level 3 - 0.5A. BUG=b:131272830 BRANCH=none TEST=emerge-hatch coreboot chromeos-bootimage Signed-off-by: YenLu Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I0e5c079856a167b1c2ef52e446d055404e565858 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35794 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-15 08:42:14 +0000