summaryrefslogtreecommitdiff
path: root/src/mainboard/google
AgeCommit message (Collapse)Author
2015-12-10cbfs/vboot: remove firmware component supportAaron Durbin
The Chrome OS verified boot path supported multiple CBFS instances in the boot media as well as stand-alone assets sitting in each vboot RW slot. Remove the support for the stand-alone assets and always use CBFS accesses as the way to retrieve data. This is implemented by adding a cbfs_locator object which is queried for locating the current CBFS. Additionally, it is also signalled prior to when a program is about to be loaded by coreboot for the subsequent stage/payload. This provides the same opportunity as previous for vboot to hook in and perform its logic. BUG=chromium:445938 BRANCH=None TEST=Built and ran on glados. CQ-DEPEND=CL:307121,CL:31691,CL:31690 Change-Id: I6a3a15feb6edd355d6ec252c36b6f7885b383099 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12689 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-09google/oak: define flash sizePatrick Georgi
We never defined the flash size for this board, so the (too small) default was used. Instead, adopt the size given in depthcharge's fmap description. Change-Id: I63782922ee05a9595d6c0de56750460ebb67aec6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12674 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-12-04google/oak: Add timestamps in romstageYidi Lin
BUG=none TEST=emerge-oak coreboot BRANCH=none Change-Id: Idf74265c9c1ab3a1a74fd18dfd289fccad25177e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 569c433886b19cd08d168e995bf34156c2ba6963 Original-Change-Id: I07fda6a0719d49e2c07249276ae2cc0b57fdfeda Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292660 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12610 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-04mediatek/mt8173: Add mt6391 PMIC driverhenryc.chen
BUG=none TEST=emerge-oak coreboot BRANCH=none Change-Id: I2b9e1fc16183a29ba308313d347f2f0e948e96a7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ee56cab3b5c04838af80690c21d3aa160d71501a Original-Change-Id: I2eaa0a406c29b7c9012e3c9860967fc3f27a48a5 Original-Signed-off-by: henryc.chen <henryc.chen@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292669 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12608 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-03google/oak: Add board_id() and ram_code() implementationCC Ma
BRANCH=none BUG=none TEST=Oak build pass Change-Id: Ic2fd9b2ec0592d1f7195d72c60dab15961de0a9e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4d0b00a779b87b0b625cc2bccd8f7470b79e6410 Original-Change-Id: Id9f17d64e9e30946817b86ec8cdfe67ea3dbc798 Original-Signed-off-by: CC Ma <cc.ma@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292675 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12607 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03google/oak: Implement the code which reads GPIOs for ChromeOS.Yidi Lin
BUG=none BRANCH=none TEST=emerge-oak corebootk Change-Id: Ic1a0d640cac7fd98acd06d619736303fa449c0a1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ce465e8cbdf6465c072e476a91a400d78c959218 Original-Change-Id: Iade51db02f45264fdffe387e0563b60e637c0710 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292674 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12606 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03google/oak: Initialize the necessary pinsBiao Huang
BRANCH=none BUG=none TEST=verified on Oak rev2 & rev3 Change-Id: I35776f5bdf54243236afba860ae8e9117a160cde Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b46bd9a079107ab78964f7e39582b3b5c863b559 Original-Change-Id: I6696972d07adbf3da5967f09c1638bb977c10207 Original-Signed-off-by: Biao Huang <biao.huang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292673 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12605 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03google/chell: update dptf TSR1 & TSR2 critial pointsWisley
update dptf TSR1 & TSR2 critial points from 70 to 75 TSR1 & TSR2 are reach 68 degree that is close to 70 degree afer SVPT test, change the point will avoid to trigger critial in our factory run in test BRANCH=none BUG=none TEST=build and boot chell DUT Change-Id: Ie5b8b24d82e929a7bd254967b70b61fda2c8bd0a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cf29fee19edf425010cc76af95b7a8e73a3d82bb Original-Change-Id: Idb9dd77432cfd246c1c612e52c6f945352e265ca Original-Signed-off-by: Wisley Chen <Wisley.Chen@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313967 Original-Commit-Ready: Duncan Laurie <dlaurie@chromium.org> Original-Tested-by: Chen Wisley <wisley.chen@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Chen Wisley <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/12604 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03google/glados: Disable kepler deviceDuncan Laurie
Disable the kepler device to save power and enable S0ix testing. It has been disabled in the ME image and was not working anyway.. BUG=chrome-os-partner:40635 BRANCH=none TEST=build and boot on glados Change-Id: I6640c7a09d418ba4b4de6f16138c124436dd8758 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6490769a32539cb6ef429717f021519c152a4a54 Original-Change-Id: If6e384dd2218c6a110747a489329a59fa6433c02 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/313827 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12599 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-12-03google/chell: Update mainboard for EVTDuncan Laurie
- Disable kepler device, it is removed and was not used on proto anyway. - Enable GPP_D22 as GPO to control I2S2 buffer for bit-bang PDM. - Disable HS400, this is breaking some devices on proto boards and is being disabled to reduce risk for EVT build. - Change Type-C USB2 port drive strength. BUG=chrome-os-partner:47346 BRANCH=none TEST=build and boot on chell proto Change-Id: Icf31f08302c89b2e66735f7036df914c0a0b9e8c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d00abc12efa69a99e6b0272228f52fb29e6b9180 Original-Change-Id: I63bda0b06c7523df9af9aed9b82280133b01d010 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/313825 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12598 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03google/lars: SPD change for Proto boarddavid
Update Memory ID for Proto board Update detection of single/dual channel memory to use SPD Index (Memory ID) Remove boardid.h as it is no longer needed BUG=None BRANCH=None TEST=Build and Boot Lars (Proto) Change-Id: I100b0fec4bf555c261e30140109cb0f36576130c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 24a4fddf4f1a4441fca8783cfa451e220ff986d8 Original-Change-Id: I636e881cb3fb9a0056edea2bc34a861a59b91c8f Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313903 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/12593 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03mediatek/mt8173: Add a stub implementation of the MT8173 SoCYidi Lin
BUG=chrome-os-partner:36682 TEST=emerge-oak coreboot BRANCH=none Change-Id: I748752d5abca813a0469d3a76e4d40fcbeb9b959 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ece2f412d94f071a6f5f1dbed4dfaea504da9e1a Original-Change-Id: I1dd5567a10d20840313703cfcd328bec591b4941 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292558 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12587 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-24google/rambi: Fix IASL warnings _CRS must return a valueMartin Roth
The Touchpad and Touchscreen _CRS methods do not return an interrupt value if the I2c busses that the devices are on are not in PCI mode. Previously they didn't return any value if they weren't in PCI mode. This patch has them return an empty resource template. Fixes these warnings: dsdt.aml 2813: Method (_CRS) Warning 3115 - ^ Not all control paths return a value (_CRS) dsdt.aml 2813: Method (_CRS) Warning 3107 - ^ Reserved method must return a value (Buffer required for _CRS) dsdt.aml 2832: Method (_CRS) Warning 3115 - ^ Not all control paths return a value (_CRS) dsdt.aml 2832: Method (_CRS) Warning 3107 - ^ Reserved method must return a value (Buffer required for _CRS) Change-Id: I02a29e56a513ec34a98534fb4a8d51df3b70a522 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12519 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-23google/rambi: Fix end comment in KconfigMartin Roth
Change-Id: I3963d145f6d209e32256268259e93103c62809c5 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12504 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2015-11-23IASL: Enable warnings as errorsMartin Roth
We've actually got more warnings now than when I first tested IASL warnings as errors. Because of this, I'm adding it with the option to have it disabled, in hopes that things won't get any worse as we work on fixing the IASL warnings that are currently in the codebase. - Enable IASL warnings as errors - Disable warnings as errors in mainboards that currently have warnings. - Print a really obnoxious message on those platforms when they build. ***** WARNING: IASL warnings as errors is disabled! ***** ***** Please fix the ASL for this platform. ***** Change-Id: If0da0ac709bd8c0e8e2dbd3a498fe6ecb5500a81 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10663 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-20google/veyron_mickey: Update LPDDR3 configurationjiazi Yang
This makes the same changes to the LPDDR3 configuration that were made for Samsung modules: - Enable ODT function - Change DS to 40 from 34.3 BUG=chrome-os-partner:47416 BRANCH=firmware-veyron-6588.B TEST=Boot on mickey elpida board Change-Id: If8c729188803dd854dbbe80539fb228636b5eb9f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b3eb8bc31b9727b67a6b53b4370315010d9d6379 Original-Change-Id: I2d54d3087ecd3536469866f30e4eb2d8b1acd5c1 Original-Signed-off-by: jiazi Yang <Tomato_Yang@asus.com> Original-Reviewed-on: https://chromium-review.googlesource.com/311153 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/311855 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/12484 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-20google/veyron_danger & veyron_emile: Fix Kconfig warningsMartin Roth
These platforms needed to be adjusted to fix various Kconfig warnings. Both platforms needed MAINBOARD_HAS_NATIVE_VGA_INIT because they're setting MAINBOARD_DO_NATIVE_VGA_INIT. veyron_emile needed a few symbols that depend on CHROMEOS to be moved into a new config CHROMEOS section. This matches the other CHROMEOS platforms. veyron_danger needed to select MAINBOARD_HAS_CHROMEOS before the CHROMEOS symbol was set. Change-Id: I8c7f594ba572a02513a68095c16314006fb4e379 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12462 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-11-20google/lars & intel/kunimitsu: Fix Kconfig warningsMartin Roth
EC_SOFTWARE_SYNC depends on CHROMEOS, so move it into the CHROMEOS section. This fixes the kconfig warning: warning: (CHROMEOS && BOARD_SPECIFIC_OPTIONS ...) selects EC_SOFTWARE_SYNC which has unmet direct dependencies (MAINBOARD_HAS_CHROMEOS && CHROMEOS && VBOOT_VERIFY_FIRMWARE) Change-Id: I459f48fd18c7568c4584df7d4aefa69dec3e4907 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12460 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-18google/veyron_emile: retrieve the MAC address from vpdZhengShunQian
Emile has a on board ethernet. BUG=chrome-os-partner:47465 TEST=vpd -s ethernet_mac0=001122334455 build and check the MAC address Change-Id: I90ed0ed1253c804568fcdd3dd212bb062a48c836 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 99b275c594196de0811f68380e66c226d2649927 Original-Change-Id: I1690a1f39090c57c64d4965092c80eef9070babf Original-Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/311900 Original-Commit-Ready: Shunqian Zheng <zhengsq@rock-chips.com> Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/12452 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-18google/veyron*: Pulse the i2c clock once if sda was lowDouglas Anderson
On one particular TV the TV was holding SDA low when it came up. It would release the SDA when the SCL went low the first time. Unfortunately the HDMI i2c port wouldn't transmit until the SDA was released. Let's detect this case and insert a bogus clock pulse to try to get the other side to release SDA. It's unclear why the kernel doesn't have this problem. BRANCH=none BUG=chrome-os-partner:46256 TEST=Insignia TV works now Change-Id: Ic9d27eb69bdc9c5fb11a68258e0c755cdc8b79d7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 356ee7503f04e741a41be37ad573b588067b7114 Original-Change-Id: I4b6361877e0576cc4ea2f643f073f1aab660e434 Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/309258 Original-Reviewed-by: Agnes Cheng <agnescheng@google.com> Original-Commit-Queue: Agnes Cheng <agnescheng@google.com> Original-Trybot-Ready: Agnes Cheng <agnescheng@google.com> Original-Tested-by: Agnes Cheng <agnescheng@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/309546 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/12451 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-18google/lars: enable wakeup from S0ix using headset buttondavid
Kernel needs to set Audio IRQ as wake capable. BUG=None BRANCH=None TEST=emerge-lars coreboot Change-Id: Ib7f0fc52baa006d992a2f91a63417e3f76817634 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 32d82ac48c6f830fbb09b776d0adaf6b7a727416 Original-Change-Id: I3fd70ac99c623a99b07fa1a185ebace8c1fc3d69 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/312172 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12450 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-18google/lars: Enable wake from touch paddavid
This patch enables GPP_B5 as ACPI_SCI for wake. It also defines touchpad wake device in ACPI with GPE0_DW0_05 for _PRW. BUG=none BRANCH=none TEST=emerge-lars coreboot Change-Id: I2b65f6a37783ecdbdbc32ebe613243e042c865e9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ec5b629f920984564f12f2c09458ed300d031f69 Original-Change-Id: I9bd2b3595ae833fa5d07d97a7cda4a29041be837 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/311890 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/12449 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-18google/chell: Turn on keyboard backlight in romstageDuncan Laurie
Use the keyboard backlight to provide indication that the system is booting. This is useful for determining that a system is in S0 and is running BIOS code. BUG=chrome-os-partner:47435 BRANCH=none TEST=boot on chell and see keyboard backlight come on early Change-Id: I43e699bcc2f34998d3d6ce33ce72c7b04b55c146 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a3a0147b6de681365a9c995175076d5f397016fb Original-Change-Id: I2441c28431e71b13b70e6533e175d29ccfd8d7e9 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/312358 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12448 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-18google/chell: Set USB current limit to 2ADuncan Laurie
The GPIO for USBA_1_ILIM_SEL_L should be low to enable 2A charging from the Type-A port. BUG=chrome-os-partner:47172 BRANCH=none TEST=emerge-glados coreboot Change-Id: I1bbcdd467684e7c1372c8ca862d498fb6cbb966c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c8a8fbed6d0fd7aea0a41db2bde104fe7a05cabe Original-Change-Id: I3b18cbb204cfa19e50f34ea9533018e286342513 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/312451 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12447 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-18google/chell: disable power rails in sleep pathAaron Durbin
For the rails controllable by the host processor through gpios turn them off in the sleep paths. The result is that S3 and S5 will turn off those rails. BUG=chrome-os-partner:47228 BRANCH=None TEST=Built for chell. Change-Id: I5843f13be43a6ec143600585a5a0c47563e533dd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ddd5860dc0cfee68ec2f77f4931665740bede08c Original-Change-Id: Ife0e2fb11373dd129e20b914b45cd5b56c3493f7 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/312321 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/12446 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-18google/glados: disable power rails in sleep pathAaron Durbin
For the rails controllable by the host processor through gpios turn them off in the sleep paths. The result is that S3 and S5 will turn off those rails. BUG=chrome-os-partner:47228 BRANCH=None TEST=Built and booted glados. Suspended and resumed. Change-Id: I6d45683b64ca5f7c3c47e11f95951bd2d9abf31e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ed432e2b5535da6f872a53b76886d983f00b4e8e Original-Change-Id: I94d7e0b00bf7e7da8dc59f299e41b72e8fcb64f4 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/312320 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/12445 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-11google/veyron_emile: adjust to the spec of emileZhengShunQian
o. Make some gpio changes base on Emile spec. o. Init sdmmc function. o. Revert cpu freq reducing in recovery mode since Emile have more effective thermal than Mickey. o. Revert the changes of lpddr3-samsung-2GB config. BUG=chrome-os-partner:46658 TEST=build and boot on Emile BRANCH=veyron Change-Id: Ibdc2ce511c8e215c202e2067d79f4c60cdfca738 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 39e5436c8aa3353af77f62e548f48d19dc722999 Original-Change-Id: Ib2c78c9b5e3ac6620ab1772879a7ea0f7007f96e Original-Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/307651 Original-Commit-Ready: Shunqian Zheng <zhengsq@rock-chips.com> Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/12396 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-11google/veyron_emile: Add new board of veyronZhengShunQian
This is a copy of mickey and renamed. CQ-DEPEND=CL:306967 BUG=chrome-os-partner:46658 TEST=build coreboot BRANCH=veyron Change-Id: I9e1232f3f1334ec747a5beb52f214635a7ab08ae Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9316a9ec27d5799e290add1e5818f4449b680fde Original-Change-Id: I906de7bbc8b8e110e0774c14ec636a327230b325 Original-Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/307620 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/12394 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-11google/chell: Add chromeos.c to verstageDuncan Laurie
When enabling CONFIG_SEPARATE_VERSTAGE the functions in chromeos.c need to be put into verstage. BUG=chrome-os-partner:46289 BRANCH=none TEST=enable SEPARATE_VERSTAGE and build for chell Change-Id: Ic58a6e383806a7a64b9af760e194fddf15c645f1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 403f0707074802371237beecf1941034c1612f10 Original-Change-Id: Ib1154869974337b53a64efa5892a83ecd81973b8 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/310928 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12393 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-11google/chell: Disable Deep S3Duncan Laurie
In order to wake from trackpad and wifi we cannot enable Deep S3. BUG=chrome-os-partner:46289 BRANCH=none TEST=wake from trackpad on chell Change-Id: Ieb2210d5d15b5f5d744a686c743df11e5d72558f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cbc74e13b754249869144df84ab2bb9b7e77119a Original-Change-Id: I84265197fb964e0594a4672a40fd3e2362e29ae1 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/311306 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12392 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-11google/chell: Add SPD for new memory typeDuncan Laurie
This adds the SPD for SK-Hynix H9CCNNNCLTMLAR memory to be used in the EVT build. BUG=chrome-os-partner:47346 BRANCH=none TEST=emerge-chell coreboot Change-Id: I45d0840e43ed81d8286b005f0a99b014b7f0cf28 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1e917440141c586cb370147f9c5b782d6e77ea10 Original-Change-Id: I02f1349f38d83f4a09887adf81384b5a8f475dd0 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/311214 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12391 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-11intel/skylake: mainboards: Add MAINBOARD_FAMILY kconfig entryDuncan Laurie
The family variable was not being set yet for skylake, add this to the current boards. BUG=chromium:551715 BRANCH=none TEST=emerge-glados coreboot Change-Id: Icf175e4ce89cb47b9eabce1399eb3ef29e7a607f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7e379402f38634eb0204e03b616111fff9515cec Original-Change-Id: Ia31fb04b5c22defc71a0c02d9fa1eff93ccbc49d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/311213 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12390 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-11google/chell: Fix USB port assignment againDuncan Laurie
The net names are offset by 1. My board is not stable enough to really test all of these yet... BUG=chrome-os-partner:46289 BRANCH=none TEST=emerge-chell coreboot Change-Id: I65e17323f2819eca130c1bf0ccbc3ea0ec2f383f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 327194dcfcb3a5c9f431b1a2e26c230cb2b2a48b Original-Change-Id: I50e9ea091bb6e6a1da3a9434ae0fbf3f652fa354 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/311113 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12389 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-10google/{chell,lars}: Enable Fan control supportdavid
Copy from the CL https://chromium-review.googlesource.com/#/c/307028/ (I40c540dad32beefe249f025b570c347d3ad08c36) BRANCH=None BUG=None TEST=emerge-lars coreboot Change-Id: I131fb729661f0f3bfd198cdf238c627bf38a46a5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 70d471c507d12924466979c93742944975a03f27 Original-Change-Id: I0128dc65110ba363185db9c2aca5cdb140c344c2 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/310394 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/12344 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-11-07arm64: Remove cpu intialization through device-treeFurquan Shaikh
Since, SMP support is removed for ARM64, there is no need for CPU initialization to be performed via device-tree. Change-Id: I0534e6a93c7dc8659859eac926d17432d10243aa Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/11913 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-11-07arm64: Remove SMP supportFurquan Shaikh
As ARM Trusted Firmware is the only first class citizen for booting arm64 multi-processor in coreboot remove SMP support. If SoCs want to bring up MP then ATF needs to be ported and integrated. Change-Id: Ife24d53eed9b7a5a5d8c69a64d7a20a55a4163db Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/11909 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-11-07arm64: remove spin table supportAaron Durbin
As ARM Trusted Firmware is the only first class citizen for booting arm64 multi-processor in coreboot remove spintable support. If SoCs want to bring up MP then ATF needs to be ported and integrated. Change-Id: I1f38b8d8b0952eee50cc64440bfd010b1dd0bff4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11908 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-11-05Kconfig: Remove obsolete Kconfig symbols from google/intel boardsMartin Roth
- CACHE_ROM is no longer used in the coreboot code. It was removed in commit 4337020b (Remove CACHE_ROM.) - CAR_MIGRATION is also no longer used in coreboot code - it was removed in commit cbf5bdfe (CBMEM: Always select CAR_MIGRATION) - MARK_GRAPHICS_MEM_WRCOMB was removed in commit 30fe6120 (MTRR: Mark all prefetchable resources as WRCOMB) Change-Id: I8b33a08c256f6b022e57e9af60d0629d9a3ffac8 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12327 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-11-05google/chell: Fix USB port assignmentDuncan Laurie
The PCH pin names in the schematic were incorrectly labeled. BUG=chrome-os-partner:46289 BRANCH=none TEST=build and boot on chell Change-Id: I6153137b7c04d22db5b3f00f5eaf3f400f4c344c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6f362900b0635dc392c63b25a88a7723f22b467a Original-Change-Id: If6f8744f020a35a76647366b247723b03c02991a Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/310061 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12324 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-05intel/kunimitsu, google/glados: Enable Fan control supportSumeet Pawnikar
This patch enables the Fan thermal participant device in the device tree for thermal active cooling action for DPTF on SKL-U fan based kunimitsu board. This patch defines the _ART table in dptf ASL file. With active cooling policy (_ART), we can control the fan on/off and speed. BRANCH=None BUG=chrome-os-partner:46493 TEST=Built for kunimitsu board. Tested to see that the thermal devices and the participants are enumerated and can be seen in the /sys/bus/platform/devices. Also, checked the FAN type the cooling devices enumerated in the /sys/class/thermal with sysfs interface. Change-Id: I40c540dad32beefe249f025b570c347d3ad08c36 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 82ae11643ca23e65780006f3890f1d173363b8af Original-Change-Id: If44b358052a677d13c74919f09a3eb89611fccad Original-Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/307028 Original-Commit-Ready: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Original-Tested-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/12323 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-05mainboard: Remove last_boot NVRAM optionTimothy Pearson
The last_boot NVRAM option was deprecated and removed in commit 3bfd7cc6. Remove the last_boot option from all affected mainboards to eliminate user confusion. Change-Id: I7e201b9cf21dfe5dda156785bad078524098626d Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12316 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-28google/glados: Set the type-c flex port to max USB2 settingsDuncan Laurie
Change the tuning setting for the type-c port that is over the flex cable to use the max possible drive strength. Also fix up the comments to indicate what Type-c port goes where instead of just referring to them by number. BUG=chrome-os-partner:45367 BRANCH=none TEST=build and boot on glados Change-Id: Iebcffc9ab95d56289258017248c273090c88bb06 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 824ca87c4bf556d493dc8cdec561f37ab135cd2d Original-Change-Id: I081623bbb1b0f39f1569b9f5cf7933abefe202b3 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/309010 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12204 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-28google/chell: Set DPTF critical temperature to 99CDuncan Laurie
If we boot without a heatsink then DPTF may power off the system when it starts if the CPU temp is >90C. Since TJmax is 100C set the critical threshold to just below that value. Also remove the active thresholds as chell does not have a fan. This will have DPTF use the default values but without the DPTF active policy it shouldn't get used. BUG=chrome-os-partner:46694 BRANCH=none TEST=build and boot on chell w/o a heatsink Change-Id: Id9e8f2c547468db8ad0edaf6c362a9a9bb5b95a2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 23d9117d5d7a4b44fc2298352eba133747f8e246 Original-Change-Id: Ib8e074098e3956efeed0f9b7f8b16652658db374 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/308728 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12202 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-28google/lars: Add new mainboarddavid
This is based on kunimitsu with minor changes: - update GPIOs based on schematic - update SPD data for memory config - disable ALS BUG=None TEST=emerge-lars coreboot Change-Id: Id1c9edfe3cc665e90683344f1662de2e65caf766 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3201aa573a77fcad3b6b1335d23eb4c2a09c1708 Original-Change-Id: Ifae446e4668569b6100b29bc1f52b0fea1df2952 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/308283 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Bernie Thompson <bhthompson@chromium.org> Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/12201 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-28google/lars: Copy from intel/kunimitsudavid
Change-Id: I95129e6f519735e236c9c13b16e21df25b9ea607 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/12200 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-27intel/skylake: Clean up USB configuration in devicetreeDuncan Laurie
Instead of having many different arrays for USB configuration, with each array containing one bit of information, have one array containing all the information for each port. This way we can put the basic tuning parameters into a structure and then define structures for the basic supported configurations. The existing port definitions are taken from the Skylake HSIO tuning guide. BUG=chrome-os-partner:40635 BRANCH=none TEST=build and boot on glados, verify USB functionality in all ports. Change-Id: I5873dee011ae9e250b6654c73a7bd5c17681095b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 864040412b2d2923d3acbfca8055724887c58506 Original-Change-Id: Id518b1086abbe4a8c25d77fd4efc2d0de856bd5f Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/306734 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12163 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-27google/glados: csme: program sml gpios for csme power gatingArchana Patni
For SMT controllers to power gate, all SMT/SMS clock, data and alert signals should be inactive. The SML0 blocks are not used for any functional purposes and are not configured in the GPIO tables. SMT hardware will not allow the blocks to be power gated in this scenario. The SML* pins are now configured as GPIOs - input and deep. With this change, the SMT blocks are properly power gating. BRANCH=none BUG=chrome-os-partner:45618 TEST=build for Glados. Change-Id: Ie5406f2a1e0c485ac1290e2154755085fa3bb7b9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5b3fe3c2ddea4c5daedb04078b24cff14efa49d5 Original-Change-Id: I8dcc0bfc121e612a174e6fe3152650d0fcd68f39 Original-Signed-off-by: Archana Patni <archana.patni@intel.com> Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/306481 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12160 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-27google/chell: fix hynix spd dataAaron Durbin
Spreadsheet as built indicates: Samsung 4*8Gb - K4E8E304EE-EGCF - 0b0000 Samsung 4*16Gb - K4E6E304EE-EGCF - 0b0001 Hynix 4*8Gb H9CCNNN8GTMLAR-NUD - 0b0010 Hynix 4*16Gb H9CCNNNBJTMLAR-NUD - 0b0011 Adjust the Hynix spds to match accordingly. BUG=chrome-os-partner:46573 TEST=None BRANCH=None Change-Id: I2ae0335af3557c787cced899bfb80db045f99cd0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 35ed2b0a5af53203480c726b875875d7c2cfd855 Original-Change-Id: I3cb38b28c454fbd60b776954c377b4559c6efebd Original-Signed-off-by: Aaron Durbin <adurbin@chromium.orG> Original-Reviewed-on: https://chromium-review.googlesource.com/306580 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/12159 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-27google/chell: Add new mainboard for chellDuncan Laurie
This is based on glados with minor changes: - updated GPIOs based on schematic - add _PRW for trackpad wake now that it is on a new GPIO - add SPD for new memory config - disable ALS BUG=chrome-os-partner:46289 BRANCH=none TEST=emerge-chell coreboot Change-Id: Id5746bf2b5b26000fcc3f029b901bfe29b788dac Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9c5ebe98cf599ba80aac5e9ef238b7996789a819 Original-Change-Id: I75efda64a50b0e6e4a5c9008ce05d76c1e605b0c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/304927 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12151 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-14 09:03:18 +0000