Age | Commit message (Collapse) | Author |
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We decided to store the FSG on eMMC instead of SPI flash, so we don't
need this region anymore. Getting rid of it allows us to put more space
into CBFS (to store hi-res bitmaps). Also grow VPD by some remaining
amount to keep the FMAP alignment reasonable.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: If73450b65718affae71b6ada70ded5c5f45cfb4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philip Chen <philipchen@google.com>
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This reverts commit fddd101904188193197be10c8eae04e76386299b.
Reason for revert: With FSP compression and non serial FSP we now have enough space in RO.
Original change's description:
> mb/google/zork: Increase RO section to 5MB
>
> The current size is too small to fit all the depthcharge assets.
> Increasing it to 5MB gives us 648k of free space.
>
> $ cbfstool /build/zork/firmware/image-trembyle.serial.bin print -r COREBOOT
> FMAP REGION: COREBOOT
> Name Offset Type Size Comp
> cbfs master header 0x0 cbfs header 32 none
> fallback/romstage 0x80 stage 524316 none
> fallback/ramstage 0x80100 stage 96592 none
> config 0x97ac0 raw 843 none
> revision 0x97e80 raw 680 none
> spd.bin 0x98180 spd 8192 none
> etc/sdcard0 0x9a1c0 raw 8 none
> locales 0x9a200 raw 141 LZMA (166 decompressed)
> (empty) 0x9a300 null 3224 none
> fspm.bin 0x9afc0 fsp 720896 none
> (empty) 0x14b000 null 3992 none
> fsps.bin 0x14bfc0 fsp 327680 none
> pci1002,15d8,c1.rom 0x19c000 optionrom 54272 none
> pci1002,15d8,c4.rom 0x1a9480 optionrom 54272 none
> fallback/dsdt.aml 0x1b6900 raw 12727 none
> locale_hi.bin 0x1b9b00 raw 10441 LZMA (239928 decompressed)
> ...
> locale_ko.bin 0x254f80 raw 11282 LZMA (231168 decompressed)
> fallback/payload 0x257c00 simple elf 95169 none
> (empty) 0x26f000 null 245656 none
> apu/amdfw 0x2aafc0 raw 1277440 none
> (empty) 0x3e2e00 null 688472 none
> bootblock 0x48af80 bootblock 64 none
>
> BUG=b:130028876
> BRANCH=none
> TEST=Built image with depthcharge and booted.
>
> Change-Id: I9cd2902404ef68cdbd4a9484d5cb1ee9cba3efd1
> Signed-off-by: Raul E Rangel <rrangel@chromium.org>
> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2042850
> Reviewed-by: Martin Roth <martinroth@google.com>
BUG=b:130028876, b:150746858
BRANCH=none
TEST=emerge-zork coreboot-zork chromeos-bootimage and boot trembyle
localhost ~ # flashrom -p host -r /tmp/main.bin
flashrom v0.9.9 : 1e0291b4 : Apr 16 2020 06:13:41 UTC on Linux 5.4.39 (x86_64)
flashrom v0.9.9 : 1e0291b4 : Apr 16 2020 06:13:41 UTC on Linux 5.4.39 (x86_64)
Calibrating delay loop... OK.
coreboot table found at 0xcbe54000.
Reading flash... SUCCESS
localhost ~ # futility dump_fmap /tmp/main.bin | grep WP_RO -B 3
area: 22
area_offset: 0x00c00000
area_size: 0x00400000 (4194304)
area_name: WP_RO
localhost ~ # flashrom -p host --wp-range 0xc00000 0x400000 --wp-enable
flashrom v0.9.9 : 1e0291b4 : Apr 16 2020 06:13:41 UTC on Linux 5.4.39 (x86_64)
flashrom v0.9.9 : 1e0291b4 : Apr 16 2020 06:13:41 UTC on Linux 5.4.39 (x86_64)
coreboot table found at 0xcbe54000.
SUCCESS
localhost ~ # flashrom -p host --wp-status
flashrom v0.9.9 : 1e0291b4 : Apr 16 2020 06:13:41 UTC on Linux 5.4.39 (x86_64)
flashrom v0.9.9 : 1e0291b4 : Apr 16 2020 06:13:41 UTC on Linux 5.4.39 (x86_64)
coreboot table found at 0xcbe54000.
WP: status: 0x0094
WP: status.srp0: 1
WP: status.srp1: 0
WP: write protect is enabled.
WP: write protect range: start=0x00c00000, len=0x00400000
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5df10ee8e855adfaaf4b2fac4c2c47037ec093b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Create the voxel variant of the volteer reference board
BUG=b:157879197
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_VOXEL
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I8ba5412be211730db84675927c500238cb20ff3d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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BUG=b:157499341
BRANCH=NONE
TEST=FW_NAME="vilboz" emerge-zork coreboot
Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I28ab3edb130fc7bf8b786141bc088166052d4868
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41801
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The default HID was removed by a1c82c5ebee. We need to explicitly
specify it.
BUG=b:154756391
TEST=No longer see ERROR: _HID required message in console
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0083f98aea55ba262ac44b0018c9c1d2e12d9f8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: Id0bb5266246dbd959c6497d7c411f908cc49318c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Board does not have ChromeEC.
Change-Id: Id6ab2495d6e082fdcb71ec5162efde877d97ce22
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Boards have unconditional select EC_GOOGLE_CHROMEEC.
Change-Id: Id444c83fc40f908d2257e8ec2606f149722a9bde
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This file is not used.
BUG=b:154756391
TEST=Build trembyle and check that peripherals still work
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I721e295546aa75c9745a4836425b6e3e0067afaf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch enables enables the CSE Lite SKU for all the
puff variant boards.
BUG=b:143229683
TEST=Build and boot puff with CSE Lite SKU.
Cq-Depend: chrome-internal:3046770
Change-Id: I0de6bca162b01870ca554ae97bc4a41cf66fef18
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch modified the puff fmd files to support CSE Lite SKU.
* Reduce the SI_ALL size to 3MiB since ME binary size is less
than 2.5MiB.
* Increase the FW_MAIN_A/B size to accommodate the ME_RW update
binary with CSE Lite SKU.
BUG=b:154561163
TEST=Build and boot puff with CSE Lite SKU.
Cq-Depend: chrome-internal:3046770
Change-Id: I4d39a1bdeabf48fc740da67539f48a9ff72c442c
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41198
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Based on schematic and gpio table of halvor, generate gpio setting and
overridetree.cb for halvor.
BUG=b:153680359
TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage
Verify that the image-halvor.bin is generated successfully.
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Ic6bd018551be58945742d1a6e7f7c5560f218e40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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H1 is stable after HW rework. Connect +3.3V_ALW_PCH with +3.3V_PRIM.
Therefore change I2C speed back to FAST.
BUG=b:154885320
TEST=Check H1 I2C speed is 375kHz by scope. And no error message in
cbmem and kernel log.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: If58721039d90514a17f024e6b432f3a5226440e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
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The ripto board is still being used for testing so make sure it supports
the same audio config as volteer.
BUG=b:147462631
TEST=build ripto variant
Change-Id: Iabeb73307418dc16b12fa60ad26923cd9f6e1f3a
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
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For all of the audio devices in devicetree.cb add the probe matches
that will determine if the device should be enabled or not based on
the selected audio daughter board type.
AUDIO=MAX98357_ALC5682I_I2S: enable max98357 and alc5628, disable others
AUDIO=MAX98373_ALC5682I_I2S: enable max98373 and alc5682, disable others
AUDIO=MAX98373_ALC5682_SNDW: enable soundwire devices, disable others
BUG=b:147462631
TEST=test different device present in ACPI based on fw_config value:
> AUDIO=NONE
ectool cbi set 6 0x00000000 4 2
> AUDIO=MAX98357_ALC5682I_I2S
ectool cbi set 6 0x00000100 4 2
> AUDIO=MAX98373_ALC5682I_I2S
ectool cbi set 6 0x00000200 4 2
> AUDIO=MAX98373_ALC5682_SNDW
ectool cbi set 6 0x00000300 4 2
Change-Id: I5492e8cddcff3ba01023b0daef02be3508d347b0
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41216
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add the current firmware configuration table for the volteer mainboard
and define some actions based on probe results for audio:
- When I2S options are selected disable the SoundWire GPIOs.
- When SoundWire is enabled disable the I2S GPIOs.
- When no audio is enabled disable all the GPIOs.
BUG=b:147462631
TEST=Test that GPIOs are configured as expected based on the current
value of the fw_config field in cbi.
Change-Id: I179f8b6436be83a2b37911777764bd26a0d404b7
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41215
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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- Move all audio devices from baseboard to the volteer variant.
- Add max98373 devices and enable the driver
- Disable everything in FSP and let coreboot configure GPIOs.
BUG=b:147462631
TEST=this change makes all audio devices show up in ACPI, so this
was tested by ensuring that all audio devices are present in ACPI.
Change-Id: Ic654ea52a549053622603aa8c81fb37577d4e011
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: I7c0be437e8cb49934913563c6d21056034a50095
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41684
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: If8c7e26ebd954b19bfb8766b26570c6865ad255e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41676
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I54eda3d51ecda77309841e598f06eb9cea3babc1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: If8048586e3693a8e6f63d9dc2800b073bab78628
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41669
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Also, replace 'lapic.h' by 'lapic_def.h' in 'soc/intel/braswell/northcluster.c'.
Change-Id: I71cff43d53660dc1e5a760ac3034bcf75f93c6e7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41489
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Rename VPD_ANY to VPD_RO_THEN_RW, to reflect the VPD region search
preference. Update all existing code references for VPD_ANY.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I960688d1f6ab199768107ab73b8a7400a3fdf473
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41586
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This explicitly enables TCSS DMA0 controller and disables
TBT PCIe2 and PCIE3 since they are unused on volteer.
BUG=:b:146624360
TEST=Built and booted on Volteer.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I05cc9e3964d8037d433fca443be6e8d5b444bbce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41387
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch enables the necessary GBB configs for dedede
BUG=none
BRANCH=none
TEST=GBB Flag value was 0x39 before enabling the required flags
and now it is updated to 0x40b9. Verfied from CPU log.
Change-Id: Ica07c65d6cf23ea859de6aa8413377661547e47a
Signed-off-by: Usha P <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
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1. Configure SD card GPIOs.
2. Set SD card power polarity and card detect configs.
SD card CMD. DATA and CLK GPIOs are set for native pad termination
as per recommendation in EDS vol1 section 10.4.10
BUG=b:150872580
TEST=Verify SD card enumeration and read/write transactions.
Change-Id: I90c8ceb85ada23718ff7b6fd7013317c818dd532
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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TEST=Build and boot waddledoo board
Change-Id: Ic10af9a0d50946a98a5c4a77b492d242cef171ca
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41535
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Delete leading empty comment lines.
Change-Id: I8e14a0ad1e1e2227e4fb201f5d157f56f289f286
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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A verbatim copy of variants/puff.
BUG=b:156429564
BRANCH=none
TEST=none
Change-Id: I8c76d468177e1f3fcab53e0790599041b1a944d8
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41851
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable heci1 device from devicetree for PCI enumeration. This is
required for ME status dump using HFSTSx resgisters in PCI config
space. Heci1 device is later disabled through heci disable flow.
TEST=Build, boot waddledoo. ME status dump is seen in console logs.
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Change-Id: Icb77db3f0666c2d14ebef2c3214564346d1fd3c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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The first DRAM part supported by SPD_LPDDR4X_200b_4Gb_3733_DDP_1x16 is
NT6AP256T32AV-J2 so the SPD content is generally extracted from it's
SPD. On the other hand, SPD bytes 4 / 6 / 13 were amended to follow SoC's
requirement.
BUG=b:152277273
BRANCH=None
TEST=build the image successfully.
Change-Id: If6fb0855a961d1c68315a727466bf45569cf2597
Signed-off-by: Marco Chen <marcochen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41813
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch selects the fmd files based on config
BOARD_GOOGLE_BASEBOARD_PUFF and also renames the files
to align with basebaord name and layout size.
BUG=b:154561163
TEST=Built puff and verified that it selects the right fmd file.
Change-Id: Ice6196ca778c6c118ce89e1510a445339a5c3455
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch selects the fmd files based on config
BOARD_GOOGLE_BASEBOARD_HATCH and also renames them to
add the baseboard name and layout size tags.
BUG=b:154561163
TEST=Built hatch variants and verified that they select the
right fmd files.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I5d99ae28cc972ffa635adf100b756c36e168a8f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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All hatch and puff variants use 16MiB SPI flash except the legacy ones
which used 32MiB flash. Kconfig.name is updated to select
BOARD_ROMSIZE_KB_32768 only for the legacy variants and
BOARD_GOOGLE_HATCH_COMMON selects BOARD_ROMSIZE_KB_16384 by default if
BOARD_ROMSIZE_KB_32768 is not selected.
TEST=Verified using abuild --timeless that all hatch variants generate
the same coreboot.rom image with and without this change.
Change-Id: I708506182966936ea38562db8b0325470e34c908
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41662
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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VBOOT_EC_EFS is for EFS1 and EFS1 is deprecated. Puff uses EFS2
and its variants should follow.
BUG=b:157372086
BRANCH=none
TEST=emerge-puff coreboot
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I581f137b506a96df45e5bed21833856bb4f6aaa3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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Volteer's MUX connections are known, and can now be described in ACPI
tables. Port 1 has the only oddity, with SBU lines staying fixed in the
CC1 orientation.
TEST=Dump SSDT tables on Volteer, and confirm (coalesced for brevity):
Scope (\_SB.PCI0.PMC)
{
Device (MUX)
{
Name (_HID, "INTC105C")
Device (CON0)
{
Name (_ADR, 0)
Name (_DSD, Package() {
Package () { "usb2-port-number", 9 },
Package () { "usb3-port-number", 1 },
})
}
Device (CON1)
{
Name (_ADR, 1)
Name (_DSD, Package() {
Package () { "usb2-port-number", 4 },
Package () { "usb3-port-number", 2 },
Package () { "sbu-orientation", "normal" },
...
}
}
}
Change-Id: Id361b2df07e87ad72b6a59a686977b3f424e8ecf
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Dragonegg is no longer in development nor used. Remove it.
Change-Id: Ida30dba662bc517671824f8b70b73b4856836e97
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41783
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I858f870db0babcb51c594570e8136436ecbb0d1d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41823
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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ports""
This reverts commit 1726fa1f0ce474cde32e8b32be34a212aff3ffba.
Reason for revert: Resource allocator is split into old(v3) and
new(v4). So, this change to enable hotplug resource allocator for
volteer can land back.
BUG=b:149186922
Change-Id: Ib6a4df610b045fbc885c70bff3698a032b79f770
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I6c69dcad82ee217ed4760dea1792dd1a6612cd8b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Create the terrador variant of the volteer reference board
BUG=b:156435028
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_TERRADOR
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I088861d1f8b7b4ee8de1e5ab6c7d3109ffd0531b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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Change-Id: Ia56305e9554b666f8eaf590a91be84e5cac4c75c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41701
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change drops rt8168 ethernet Kconfig options for baseboard hatch
since it does not really support an ethernet device.
Change-Id: I7c19dbeb2f64b0643b082a9c588f8b14db4dfb8a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41661
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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mb/google/hatch supports two different reference platforms - Hatch and
Puff. This change adds Kconfigs BOARD_GOOGLE_BASEBOARD_PUFF in
addition to BOARD_GOOGLE_BASEBOARD_HATCH to better organize the
Kconfig selections and reduce redundancy. In addition to this, a new
config BOARD_GOOGLE_HATCH_COMMON is added that selects all the common
configs for both baseboards.
TEST=Verified using abuild --timeless option that all hatch variants
generate the same coreboot.rom image with and without this change.
Change-Id: I46f8b2ed924c10228fa55e5168bf4fe6b41ec36c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41660
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There are SX9310 devices present in devicetree.cb but the driver is
not enabled so it is not getting used.
Change-Id: I625233013a2e14eaf758e56027774fbf5df3bc83
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41700
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable Intel Speed Shift Technology (ISST) by default. Disable ISST in
waddledee and waddledoo variants on early phases.
BUG=b:151281860
TEST=Build and boot the mainboard. Ensure that cpufreq driver to
configure P-states is enabled in kernel on boards where board version is
provisioned.
Change-Id: Id65d7981501c2f282e564bfc140f8d499d5713e8
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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This is a copy of the mb/google/zork directory from the chromiumos
coreboot-zork branch. This was from commit 29308ac8606.
See https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/29308ac8606/src/mainboard/google/zork
Changes:
* Minor changes to make the board build.
* Add bootblock.c.
* Modify romstage.c
* Removed the FSP_X configs from zork/Kconfig since they should be
set in picasso/Kconfig. picasso/Kconfig doesn't currently define the
binaries since they haven't been published. To get a working build
a custom config that sets FSP_X_FILE is required.
BUG=b:157140753
TEST=Build trembyle and boot to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3933fa54e3f603985a0818852a1c77d8e248484f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41581
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change enables max98390 audio codec on nightfury.
BUG=b:149443429
BRANCH=firmware-hatch-12672.B
TEST=Built and checked audio function on nightfury
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: Ic9678583370cf5e41c87e35ba12f86572708fada
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Additional verb changes are needed for Headset and Mic detection to
work properly.
BUG=b:155360937
TEST=Headset and Mic detection is working in the UI audio tray
Change-Id: I184a05949f5522e929969156b72629be3d957e3f
Signed-off-by: Jairaj Arava <jairaj.arava@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41642
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Convert spaces to tabs in volteer variant makefiles, and remove empty
comment lines from file headers.
BUG=none
TEST="emerge-volteer coreboot chromeos-bootimage", flash and verify
volteer boots to kernel.
Change-Id: I6c818c3adcc55ce89707efff6dd9a6bce512daa5
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41587
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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