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2016-07-22google/reef: Update gpio config for audioSathyanarayana Nujella
This changelist updates gpio config for speaker SDMODE pin. It disables speaker by default. Audio kernel is expected to enable this when audio rendering starts. Change-Id: Id33ad29e637bf1fe6b02e8a4b0fd9e220e8983e7 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/15433 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-22soc/intel/apollolake: clarify meaning of LPDDR4 density meaningAaron Durbin
The 'dram density' is a misnomer because the memory initialization code treats that input parameter as a per rank density. Therefore, update the variables to further clarify how it's actually being used. BUG=chrome-os-partner:55446 Change-Id: Ie4c944f35b531812205ac0bb1c70f39ac401495e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15773 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-22mainboard/google/reef: indicate dual rank LPDDR4 skusAaron Durbin
The 16Gb devices use two ranks per channel within the DRAM module. However, the density settings are really on a per rank basis so indicate dual rank with a device density of 8Gb. BUG=chrome-os-partner:55446 Change-Id: Ib5dba6f9ed248750d68b726996c71def9b75961e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15772 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-21mainboard/google/reef: handle eMMC power signal polarity changeAaron Durbin
The EVT board uses an active high power control signal while the previous board used an active low signal. Update the tables to reflect the differences. BUG=chrome-os-partner:55470 Change-Id: I198c0e4e019fcffe2cf748d382351ac965a81077 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15763 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-21mainboard/google/reef: reverse the memory config bitsAaron Durbin
I mistakenly assumed the order of the bits matched how one would assign values as they wrote them msb .. lsb. However, the gpio lib doesn't do that. Correct the order so that values are read out correctly. BUG=chrome-os-partner:54949t Change-Id: I5304dfe2ba6f8eb073acab3377327167573ec2cc Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15753 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-20google/reef: Add wake signal for trackpadFurquan Shaikh
EVT has a wake signal for track pad which is routed to GP_15. BUG=chrome-os-partner:54960 Change-Id: I9a73a3dc74e3bbed63509a3c076ec17a6559da55 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15723 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-19mainboard/google/reef: explicitly set shipping Chrome OS optionsAaron Durbin
The Chrome OS options that will be shipped on this platform were being set in the chromium repo with an external config file. Set the options in the mainboard Kconfig file so there's no discrepancy as to what will be used. Change-Id: I05f0d1245611c16f54273728519a08e6edff3429 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15733 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-18google/oak & elm: initialize touchscreen reset gpioYH Huang
In order to save power in S3, we remove reset gpio setting in kernel. We still need to initialize touchscreen ic. Do it by pulling low reset gpio for 500us and then pulling high in firmware. BRANCH=none BUG=chrome-os-partner:55170 TEST=build on elm. Change-Id: Idbe0175a1fc1fa0b05e81706194c79d52c6101f6 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: f40cc9a22c2551c2c9455cb8b60f36353602bca6 Original-Change-Id: If2ac815c4fd5c5ae15443348a49eb31449b724b1 Original-Signed-off-by: YH Huang <yh.huang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/360312 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Johnny Chuang <johnny.chuang@emc.com.tw> Reviewed-on: https://review.coreboot.org/15719 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-07-18gru: implement hw reset functionVadim Bendebury
Asserting this GPIO will send a signal to the EC to trigger a reset for the AP and the CR50. BRANCH=none BUG=chrome-os-partner:55252 TEST=the device now reboots when it needs to switch between different boot modes instead of hanging with "failed to reboot" message. Change-Id: I8d168e313b6983c96c80f7ad6d70bb84c1ec1d9c Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 83a4c8ff68ab24a103f2166e948eb23624ea97f7 Original-Change-Id: Idfd20977cf3682bd8933f89e8eec53005e55864e Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/360238 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/15718 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-07-15soc/intel/apollolake: Consolidate ISH enablingAndrey Petrov
Since the Integrated Sensor Hub can be disabled through devicetree.cb as a PCI device, there is no need for a separate register variable. Remove handling the register and update mainboards' devicetrees. Also keep ISH disabled on both Reef and Amenia. Change-Id: I90dbf57b353ae1b80295ecf39877b10ed21de146 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15710 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15google/reef: Add wake-up from lid openShaunak Saha
This patch adds support to wake up from S3 on lidopen. mainboard.asl has the _PRW defined for the wakeup support in S3. BUG = chrome-os-partner:53992 TEST = Reef board wakes up from S3 on lidopen. Change-Id: Ic3bae26cea0642f98d938b3523d08f5902a1f4b5 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15643 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-15mainboards/skylake: use common Chrome EC SMI helpersAaron Durbin
Reduce duplicate code by using the Chrome EC SMI helper functions. BUG=chrome-os-partner:54977 Change-Id: Ie83e93db514aa0e12e71d371d7afab34a70797fd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15689 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-15mainboards/apollolake: use common Chrome EC SMI helpersAaron Durbin
Reduce duplicate code by using the Chrome EC SMI helper functions. BUG=chrome-os-partner:54977 Change-Id: Iba2ca7185ad7f0566858ce99f5ad8325ecc243cf Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15687 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
2016-07-15mainboards: remove direct acpi_slp_type usageAaron Durbin
Use the acpi_is_wakeup_s3() API instead of comparing a raw value to a global variable. This allows for easier refactoring. Change-Id: I2813b5d275cbe700be713272e3a88fdb5759db99 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15690 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2016-07-15mainboards: align on using ACPI_Sx definitionsAaron Durbin
The mainboard_smi_sleep() function takes ACPI sleep values of the form S3=3, S4=4, S5=5, etc. All the chipsets ensure that whatever hardware PM1 control register values are used the interface to the mainboard is the same. Move all the SMI handlers in the mainboard directory to not open code the literal values 3 and 5 for ACPI_S3 and ACPI_S5. There were a few notable exceptions where the code was attempting to use the hardware values and not the common translated values. The few users of SLEEP_STATE_X were updated to align with ACPI_SX as those defines are already equal. The removal of SLEEP_STATE_X defines is forthcoming in a subsequent patch. BUG=chrome-os-partner:54977 Change-Id: I76592c9107778cce5995e5af764760453f54dc50 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15664 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15Google Mainboards: Increase RO coreboot size on flashDaisuke Nojiri
Bitmap images will be moved to CBFS from GBB. This patch adjusts the flash map accordingly for rambi, samus, peppy, parrot, falco, panther, auron, and strago. BUG=chromium:622501 BRANCH=tot TEST=emerge-{samus,falco} chromeos-bootimage CQ-DEPEND=CL:354710,CL:355100 Change-Id: I6b59d0fd4cc7929f0de5317650faf17c269c4178 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 201a82311ba539b9b02d546ba331ff5bf73e0edf Original-Change-Id: I0b82285186540aa27757e312e7bd02957f9962ec Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/355040 Reviewed-on: https://review.coreboot.org/15658 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-14google/reef: Add mainboard SMI handlerShaunak Saha
This patch adds a mainboard SMI handler file which has functions to set proper Wake mask before going to sleep so that system can wake up on lidopen, key press etc. Also SCI mask is set on boot which will enable timely update of battery UI on charger connect/disconnect. BUG = chrome-os-partner:53992 TEST = Reef Platform wakes from S3 on lidopen, key press and also sysfs entry for AC is updated on charger connect/disconnect. Change-Id: I8c087994b48223b253dcf1cbb3ed3c3a0f366e36 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15615 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-14google/reef: Enable touchscreen in ACPIFurquan Shaikh
Add support for ELAN touchscreen on I2C3. Change-Id: Id8b07a3a3fd4beca0d7ce804ba8d6859275c70d9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15499 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-13gru: Enable TPM2Vadim Bendebury
Gru and derivative boards use TPM2 to support Chrome OS verified boot. BRANCH=none BUG=chrome-os-partner:50645 TEST=re-built Kevin firmware, verified that TPM2 support over SPI is enabled, and that with appropriate vboot and depthcharge patches applied the device can boot into chrome os properly verifying RW firmware and kernel key indices. Change-Id: Id14a51cea49517bd2cc090ba05d71385aad5b54c Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 60e229d93d7e219e261b851f654e459eb2cf4f41 Original-Change-Id: Ic6f3c15aa23e4972bf175b2629728a338c45e44c Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/354781 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: https://review.coreboot.org/15606 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-07-13oak/gru: Fix derivative KconfigsJulius Werner
Add a few missing Kconfig defaults for derivatives of the Oak and Gru baseboards. Also group all Kconfigs that must change for derivatives together for easier updating. BRANCH=None BUG=None TEST=None Change-Id: I95ebb08b4f13f09f2539b451d7b96a826ddf98f8 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: ae3f13c1dc323f4c7c4a176a4f5e1285fec312ce Original-Change-Id: I658130e88daa2d113fd722b0527cf0e7ab66c7ef Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/357922 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15605 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-07-13mainboard/google/reef: use new gpio interrupt macrosAaron Durbin
Utilize the new interrupt macros in order to specify correct polarity of the gpio interupts. Some of the interrupts were working by catching the opposite edge of the asserted interrupt. BUG=chrome-os-partner:54977 Change-Id: Iee33c0a949be0a11147afad8a10a0caf6590ff7b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15645 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-07-12google/reef: Add GPE routing settingsShaunak Saha
This patch sets the devicetree for gpe0_dw configuration and also configures the GPIO lines for SCI. EC_SCI_GPI is configured to proper value. BUG = chrome-os-partner:53438 TEST = Toggle pch_sci_l from ec console using gpioset command and see that the sci counter increases in /sys/firmware/acpi/interrupt and also 9 in /proc/interrupt Change-Id: If258bece12768edb1e612c982514ce95c756c438 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15556 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-12google/gru: Read RAM & board ids from the ADCShelley Chen
- Update so that the RAM id is read from ADC instead of hard-coded from the config array. - Update the boardid readings so that they are bucketed instead of within an error margin. BRANCH=None BUG=chrome-os-partner:54566,chrome-os-partner:53988 TEST=hexdump /proc/device-tree/firmware/coreboot/ram-code and boardid when OS boots up. Also verified that voltage read in debug output returns correct id. Change-Id: I963406d8c440cd90c3024c814c0de61d35ebe2fd Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 068705a38734d2604f71c8a7b5bf2cc15b0f7045 Original-Change-Id: I1c847558d54a0f7f9427904eeda853074ebb0e2e Original-Signed-off-by: Shelley Chen <shchen@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/356584 Original-Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/15586 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-12google/gru: Enable coreboot read recovery eventShelley Chen
Enable reading of keyboard recovery host event from coreboot. BUG=None BRANCH=None TEST=esc+refresh+power combo and make sure you see recovery fw screen. Change-Id: I166619d6202e23569395434e9dc1adb2a6a53296 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: f9279c8c06abb170589b1b11bf5287fbf38c9905 Original-Change-Id: Id980c77c8d7695b2c1b3343d968ad2a302d42aaa Original-Signed-off-by: Shelley Chen <shchen@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/357841 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: https://review.coreboot.org/15585 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-12google/gru: enable EC software syncShelley Chen
Enable CONFIG_EC_SOFTWARE_SYNC. Crossystem needs this to get ec RW/RO info. BUG=chrome-os-partner:54566 BRANCH=None TEST=1. apreset from ec console. Check for "VbEcSoftwareSync() check for RW update" string in ap console. 2. Run "ectool version" from OS to check that RO/RW version are different and that we're in RW: RO version: kevin_v1.1.4818-8243672 RW version: kevin_v1.1.4762-1957187 Firmware copy: RW 3. Run crossystem ecfw_act. check for RW return value. Change-Id: If6524f2cca4a6223ab9704d0af827e8c1072670f Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 0deb0e1c69d6bf21acf7640bf76f9196e14437d7 Original-Change-Id: I0db8235cf7d472f0aa642eea1998282d010d3433 Original-Signed-off-by: Shelley Chen <shchen@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/357811 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15584 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-12Gale: Add LED support.Suresh Rajashekara
Reusing the LED patterns as it was defined for Storm/WW/Platform. BUG=b:29051518 TEST=After about 3 seconds of powering on the device different colors should be seen at the LED ring, depending on the state of the device. Alternatively, move the device to different states manually by appropriate actions (like dev mode, rec mode etc) and observe the colors. BRANCH=None Change-Id: I6f1b23fee15747a402e209a2d06f8794bbc2c5a1 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: be1194b095d9a5cf269710c43a27a5afb3e87b29 Original-Change-Id: Ie82d4e148025c0040cdb26f53f028d9b4cbe2332 Original-Signed-off-by: Suresh Rajashekara <sureshraj@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/355200 Original-Commit-Ready: Suresh Rajashekara <sureshraj@chromium.org> Original-Tested-by: Suresh Rajashekara <sureshraj@chromium.org> Original-Reviewed-by: Suresh Rajashekara <sureshraj@chromium.org> Reviewed-on: https://review.coreboot.org/15572 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-10gru: include ram_code in coreboot tableVadim Bendebury
This is needed to ensure that the ram-code node is included in the device tree by depthcharge. BRANCH=none BUG=chrome-os-partner:54566 TEST=built updated firmware, booted on kevin into Linux shell, checked the device tree contents: localhost ~ # od -tx1 /proc/device-tree/firmware/coreboot/ram-code 0000000 00 00 00 01 0000004 localhost # Change-Id: Ibe96e3bc8fc0106013241738f5726783d74bd78b Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 53c002114f7044b88728c9e17150cd3a2cf1f80f Original-Change-Id: Iba573fba9f9b88b87867c6963e48215e254319ed Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/354705 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15566 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-08mainboard/google/reef: Use device driver for DA7219 configurationDuncan Laurie
Use the device driver for DA7219 device configuration in the SSDT and remove the static copy in the DSDT. Tested on reef to ensure that the generated SSDT contents are equivalent to the current DSDT contents. Change-Id: I288eb05d0cb3f5310c4dca4aa1eab5a029f216af Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15539 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-08google/reef: Add Maxim98357a supportHarsha Priya
Adds Maxim98357a support for reef using the generic driver in drivers/generic/max98357 Change-Id: I333d4e810e42309ac76dd90c19f05cf3e3a517e0 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/15435 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-07mainboard/google/reef: apply EVT board changesAaron Durbin
Based on the board revision apply the correct GPIO changes. The only differences are the addition of 2 peripheral wake signals and a dedicated peripheral reset line. BUG=chrome-os-partner:54959,chrome-os-partner:54960,chrome-os-partner:54961 BRANCH=None TEST=Built and tested on reef. Change-Id: I9cac82158e70e0af1b454ec4581c2e4622b95b4b Signed-off-by: Aaron Durbin <adurbin@chromuim.org> Reviewed-on: https://review.coreboot.org/15562 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-07mainboard/google/reef: add board_id() supportAaron Durbin
The board build version is provided by the EC on reef. Provide the necessary functional support for coreboot to differentiate the board versions. BUG=chrome-os-partner:54959,chrome-os-partner:54960,chrome-os-partner:54961 BRANCH=None TEST=Built and tested on reef. Change-Id: I1b7e8b2f4142753cde736148ca9495bcc625f318 Signed-off-by: Aaron Durbin <adurbin@chromuim.org> Reviewed-on: https://review.coreboot.org/15561 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-07mainboard/google/reef: add memory SKU id supportAaron Durbin
While the proto boards didn't have a memory SKU notion the EVT boards do. Therefore, provide support for selecting the proper memory SKU information based on the memory id straps. This works on EVT boards because the pins used for the strapping weren't used on proto. However, internal pullups need to be enabled so that proto boards read the correct id. BUG=chrome-os-partner:54949 BRANCH=None TEST=Built and used on reef for memory config. Change-Id: I8653260e5d1b9adc83b78ea2770c683b72535e11 Signed-off-by: Aaron Durbin <adurbin@chromuim.org> Reviewed-on: https://review.coreboot.org/15560 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-07nyan: Avoid running early_mainboard_init twice in vboot contextPaul Kocialkowski
A call to early_mainboard_init is already present in verstage, thus it is only necessary to call it from romstage when not in vboot context. Change-Id: I2e0b5a369c5fb24efae4ac40d83a31f5cf4a078d Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/15450 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-02google/reef: Add DA7219 support in acpiSathyanarayana Nujella
Add DA7219 support in acpi. DA7219 has advanced accessory detection functionality. Also add DA7219's AAD as a ACPI data node. Change-Id: I979275cb2ab1e593ff1e5d360bea83b843e45032 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/15436 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-02google/reef: ACPI: Move touchpad to SSDT and remove TPMDuncan Laurie
Instantiate the touchpad using the drivers/i2c/generic device driver to generate the ACPI object in the SSDT. There is not currently a separate wake pin for this device, this will be added in EVT hardware. This was tested on the reef board by ensuring that the touchpad device continues to work in the OS. Also remove the LPC TPM from the DSDT as it is not present. Change-Id: I3151a28f628e66f63033398d6fab9fd8f5dfc37b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15481 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-01mainboard/google/reef: Configure DDI0, DDI1 HPD GPIO linesAbhay Kumar
Configure GPIO_199 and GPIO_200 as NF2 to work as HPD. Change-Id: If3aa6b75ed22c221cfbedaecf16035cdd9939387 Signed-off-by: Abhay Kumar <abhay.kumar@intel.com> Reviewed-on: https://review.coreboot.org/15447 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-01mainboard/google/reef: Use common NHLTSaurabh Satija
Add ACPI NHLT table generation that the current hardware supports. Reef supports two audio codecs, Dialog 7219 for headsets and Maxim 98357 for speakers. Change-Id: Ie39947960c86b8f65140834e31f9ed9f1b578485 Signed-off-by: Saurabh Satija <saurabh.satija@intel.com> Reviewed-on: https://review.coreboot.org/15440 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-29google/reef: set 20K PULLUP on SDCARD DATA/CLK/CMDFreddy Paul
SD card need 20K PULLUP on D0-D3/CLOCK/COMMAND lines. Without this SDCARD will throw data read/write errors. BUG=chrome-os-partner:54676 TEST=Build and boot to OS. Verify SD card is detected and data read/write works well. Change-Id: I90da5b84dc2e488eb38f805322bd7b4dee394e5b Signed-off-by: Freddy Paul <freddy.paul@intel.com> Reviewed-on: https://review.coreboot.org/15345 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-28google/reef: disable unused devicesJagadish Krishnamoorthy
BRANCH=none BUG=chrome-os-partner:54325, chrome-os-partner:54581 TEST=device off in devicetree should disable the device. Change-Id: I5dada06cba0eea8a30f297e3a6940a36b2ff40ee Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/15339 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-24rockchip/rk3399: provide multiple SDRAM configurationsLin Huang
We want to be able to easily change SDRAM clock rate for debugging purposes. This patch adds configurations for 4 different clock rates. Same configs are used for all rk3399 boards at 200, 666 and 800 MHz. Kevin board does not run reliably at 666 MHz, an option for it is added to run at 300 MHz, this option is available to Kevin only. There is not much room left in the coreboot romstage section, this is why the config file for 928 MHz is being added with this patch but is not included in the code, one of the lower frequency options will have to be dropped for the higher frequency option to be added. BRANCH=none BUG=chrome-os-partner:54144 TEST=run "stressapptest -M 1024 -s 3600" and pass on both kevin and gru. Verified that on Kevin the firmware reports starting up SDRAM at 300 MHz and on Gru at 800 MHz. Change-Id: Ie24c1813d5a0e9f0f9bfc781cade9e28fb6eb2f1 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: ef5e4551b79c3f0531f9af35491f2c593f8482f1 Original-Change-Id: I08bccd40147ad89d851b995a8aab4d2b6da8258a Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/353493 Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org> Reviewed-on: https://review.coreboot.org/15309 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-24gru: Add elog supportSimon Glass
Add code to start up elog. This uses the EC RTC to obtain the timestamp. BUG=chrome-os-partner:52220 BRANCH=none TEST=boot on gru with CONFIG_ELOG_DEBUG enabled and see elog messages Change-Id: I4971d661b267ae8b7e3befeff482ca703b741743 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: e4e9823d8cecbf9873e78b048e389c7a737ff512 Original-Change-Id: I0fcf55b3feccf9a0ad915deb6d323b65bf2e9811 Original-Signed-off-by: Simon Glass <sjg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/353822 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15306 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-24gru: Add get_developer_mode_switch()Simon Glass
Add this function and make it return 0, as there is no physical dev switch (at least I think this is what we are supposed to do). This is needed for elog to work, which is needed so we can test RTC properly. BUG=chrome-os-partner:52220 BRANCH=none TEST=boot on gru with CONFIG_ELOG_DEBUG enabled and see elog messages: elog_init() SF: Detected W25Q64 with sector size 0x1000, total 0x800000 elog_find_flash() FMAP: area RW_ELOG found @ 5d8000 (32768 bytes) elog_scan_flash() elog_is_buffer_clear(base=0x000000000031d668 size=4096) ELOG: flash area invalid elog_flash_erase(address=0x000000000031d668 offset=0x005d8000 size=4096) SF: Successfully erased 4096 bytes @ 0x5d8000 elog_prepare_empty() elog_flash_write(address=0x000000000031d668 offset=0x005d8000 size=8) elog_scan_flash() elog_is_buffer_clear(base=0x000000000031d668 size=4096) elog_is_header_valid() elog_update_event_buffer_state() elog_is_buffer_clear(base=0x000000000031d670 size=4088) elog_is_area_valid() ELOG: FLASH @0x000000000031d668 [SPI 0x005d8000] ELOG: area is 4096 bytes, full threshold 3834, shrink size 1024 elog_add_event_raw(type=16) out: cmd=0x44: 03 b9 44 00 00 00 00 00 in-header: 03 3f 00 00 04 00 00 00 in-data: 6e 4c 00 00 elog_flash_write(address=0x000000000031d670 offset=0x005d8008 size=11) ELOG: Event(16) added with size 11 elog_add_event_raw(type=17) out: cmd=0x44: 03 b9 44 00 00 00 00 00 in-header: 03 3f 00 00 04 00 00 00 in-data: 6e 4c 00 00 elog_flash_write(address=0x000000000031d67b offset=0x005d8013 size=13) ELOG: Event(17) added with size 13 elog_add_event_raw(type=A0) out: cmd=0x44: 03 b9 44 00 00 00 00 00 in-header: 03 3f 00 00 04 00 00 00 in-data: 6e 4c 00 00 elog_flash_write(address=0x000000000031d688 offset=0x005d8020 size=9) ELOG: Event(A0) added with size 9 elog_add_boot_reason: Logged dev mode boot I can't actually see the timestamp, but the EC traffic is visible. Change-Id: I82bcf296dce4f4d146edf90b23bfae955fbe9e3a Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: ffc7a7e0e7b136144d2a0b2ed21a543eafee49fa Original-Change-Id: I1489c6b874cc49495635aec0bf303f7098455716 Original-Signed-off-by: Simon Glass <sjg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/353821 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@google.com> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15305 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-24gru: Show the current time on start-upSimon Glass
Display the current time from the EC. BUG=chrome-os-partner:52220 BRANCH=none TEST=(partial) boot on gru and see output: Date: 1970-01-17 (Saturday) Time: 1:42:44 Then reboot ~10 seconds later and see output: Date: 1970-01-17 (Saturday) Time: 1:42:53 Change-Id: I4288efc56f00e47f7575d0379a44871351da6200 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: d0361193e0ec135e21f0611d7fa6e5c02f2b2bfc Original-Change-Id: I04a072c788ba3fc915e6d73703f966955bbd3e7e Original-Signed-off-by: Simon Glass <sjg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/351783 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15304 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-24gru: Enable EC-based RTCSimon Glass
Obtain the real-time clock value from the EC on start-up and show the current time. BUG=chrome-os-partner:52220 BRANCH=none TEST=(partial) with future commits and EC clock set, boot on gru into Linux shell and check the firmware log: localhost ~ # grep Date: /sys/firmware/log Date: 2016-06-20 (Monday) Time: 18:09:16 Change-Id: Id3ef791f546419c4881a891251cbb62d7596884b Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 348e9373b0e95a17f5c39ec28a480712e6e45caf Original-Change-Id: Iff43b16a86d9fee483420ee2eff5ff3d276716a3 Original-Signed-off-by: Simon Glass <sjg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/351781 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15303 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-24google/lars: Move devices from mainboard.asl to devicetreeDuncan Laurie
Declare the mainboard attached devices in the devicetree and enable the provided device drivers by default to generate the ACPI objects for these devices. Then remove the static ACPI objects from the DSDT in mainboard.asl. This was tested on a Chell mainboard since I lack a lars device. Change-Id: Ifba6fc6589ddd54f4c85e8858f17997fbb4b6176 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15316 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-24google/glados: Move devices from mainboard.asl to devicetreeDuncan Laurie
Declare the mainboard attached devices in the devicetree and enable the provided device drivers by default to generate the ACPI objects for these devices. Then remove the static ACPI objects from the DSDT in mainboard.asl. This was verified on a glados board by verifying the SSDT contents against what used to be in the DSDT. Change-Id: I710cbb8462d0fe695297102a64bec8e4212acc65 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15315 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-24google/chell: Move devices from mainboard.asl to devicetreeDuncan Laurie
Declare the mainboard attached devices in the devicetree and enable the provided device drivers by default to generate the ACPI objects for these devices. Then remove the static ACPI objects from the DSDT in mainboard.asl. This was verified by comparing the generated ACPI code in the SSDT to what was in mainboard.asl and ensuring the contents are functionally equivalent. Change-Id: I4725bbe2d47178568e3024fe3bb48cc80ff861c3 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15314 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-23intel/sandybridge: Fix builds with System Agent blobKyösti Mälkki
Broken with commit: 5c10abe nb/intel/sandybridge: increase MMCONF_BASE_ADDRESS Available sandybridge/systemagent-r6.bin has MMCONF hard-coded at some places and samsung/lumpy fails at boot here: CBFS: Locating 'mrc.bin' CBFS: Found @ offset 9fec0 size 2fc94 System Agent: Starting up... System Agent: Initializing These are the last lines as captured over USB debug. Change-Id: I441847f0e71a5e1be9c8ef6a04a81eb7bdd8a6d9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15328 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-23google/reef: Update chromeos.fmd fileFurquan Shaikh
1. Mark 256KiB at end of BIOS region as unusable BIOS region is memory-mapped just below 4GiB, however last 256KiB is unusable. Mark it accordingly in fmd file. 2. Use up holes in RW region for RW_A and RW_B. 3. Fill up holes in RO with UNUSED regions. BUG=chrome-os-partner:54672 Change-Id: I5facc566bb70d950522e12228b0631ddf00ac63d Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15313 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-23rockchip/rk3399: correct sdram inc file DENALI_CTL_217_DATA valueLin Huang
for per cs training, there should be more cycles to switch delay line. so increase W2W_DIFFCS_DLY_F0 value from 0x1 to 0x5. BRANCH=none BUG=chrome-os-partner:54144 TEST=run "stressapptest -M 1024 -s 1000" and pass Change-Id: I11720b7c6f009789b88ca26fc5da88597ed1622e Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 9de93beae09174d50a31d2df655529f71628f77c Original-Change-Id: Ide23fff04fd63fb0afc538b610b7685756f79f8d Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/352953 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org> Reviewed-on: https://review.coreboot.org/15307 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-08 01:49:12 +0000