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2020-03-07mb/google/volteer: add CNVi ASL entry for dynamic SSDT generationSrinidhi N Kaushik
This change uses drivers/intel/wifi chip for CNVi device and adds dynamic SSDT entires for CNVi also export wake gpio for CNVi. BUG=none BRANCH=none TEST=Build and boot volteer Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Ia8baf1c7b770db23f31383bda46ae8d090468560 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-03-07mb/google/volteer: add samsung-K4UBE3D4AA-MGCR SPDNick Vaccaro
Add samsung K4UBE3D4AA-MGCR SPD as memory sku id 1. BUG=b:148182234 BRANCH=none TEST=none Change-Id: Ie00c45de4d31856109cda13051a75cfa2c2548f7 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-07chromeos: stop sharing write protect GPIO with depthchargeJoel Kitching
wpsw_boot is deprecated in favour of wpsw_cur. As such, coreboot no longer needs to share "write protect" GPIO with depthcharge. BUG=b:124141368, chromium:950273 TEST=make clean && make test-abuild BRANCH=none Change-Id: I2fcb7f82aa063fd72928171af5cbef0356ba620c Signed-off-by: Joel Kitching <kitching@google.com> Cq-Depend: chromium:2088434 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39318 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-06mb/google/kahlee/nuwani: Create Nuwani variantPeichao Wang
This commit creates a nuwani variant for Grunt. The initial settings override the baseboard was copied from variant treeya. BUG=b:144890301 TEST=emerge-grunt coreboot Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: Id3a7fc890340e5a88ebc4b516dc2c0b085654999 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39316 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-06mb/google/volteer: add new ripto variantNick Vaccaro
Add a new ripto variant based off of the volteer baseboard design. BUG=b:148385924, b:150810535 TEST="emerge-volteer coreboot chromeos-bootimage", flash ripto image and verify ripto boots to the kernel. Change-Id: If7606588147500a465f16c7846e2c8429ece93ec Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
2020-03-06mb/google/volteer: make variant_early_gpio_table weakNick Vaccaro
Declare variant_early_gpio_table() weak to allow override by variants. BUG=b:148385924, b:150810535 TEST=none Change-Id: Ife5e3b75256f71ecd763c4000fd2c7d7c927bb64 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39300 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-06mb/google/hatch/puff: Enable VBOOT_EC_EFSSam McNally
If the ChromeOS EC uses EC early firmware selection (EFS), the AP vboot build must also enable EC EFS. Puff EC uses EFS, so enable it in the AP vboot build. BUG=b:150742950 TEST=Puff can boot with EC EFS with hardware write protect enabled BRANCH=none Signed-off-by: Sam McNally <sammc@chromium.org> Change-Id: I0877000b7d277106436831f2d69775c25299da9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/39273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-04src/ec,mainboard: Move weak smbios_system_sku() override inwardsEdward O'Callaghan
Internalise smbios_system_sku() strong symbol inwards in the ec_skuid.c implementation and simply wrap a call to: google_chromeec_smbios_system_sku(). BUG=b:150735116 BRANCH=none TEST=none Change-Id: I05ebfc8126c0fb176ca52c307c658f50611ab6ab Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39146 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-04mainboard/google/dedede: Migrate onto SKU ID/fw_config helpersEdward O'Callaghan
Leverage the common sku id space helper encoders. dedede uses the non-legacy SKU ID space. squash in, mainboard/google/dedede: Migrate onto get fw_config helper BUG=b:149348474 BRANCH=none TEST=only tested on hatch Change-Id: I0c21a748fddef0985022cb4e77a8db95d6692f4b Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-03-04mainboard/google/octopus: Migrate onto SKU ID helpersEdward O'Callaghan
Leverage the common sku id space helper encoders and set the sku id max to 0xff for legacy to ensure we behave the same. BUG=b:149348474 BRANCH=none TEST=tested on hatch Change-Id: I60a37a5f9659b8df4018872956f95e07a3506440 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-03-03mb/google/drallion: Enable cbfs SAR valueEric Lai
Enable read SAR value from cbfs. BUG=b:150347463 TEST=NA Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I5f27b6f7245669728e3e394e9c6a39c11bfda3b8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
2020-03-03mb/*/Kconfig: Factor out MAINBOARD_VENDORAngel Pons
Only some mainboard vendors have a prompt for this option. Let's be fair and give this ability to everyone. Change-Id: I03eec7c13d18b42e3c56fb1a43dc665d5dbd1145 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-03mb/google/dedede: Add memory initialization support for dededeMeera Ravindranath
Update memory parameters based on memory type supported by dedede 1. Update dq/dqs mappings 2. Update spd data for Micron Memory 3. Add SPD data binary files for supported memory types 4. Update other FSPM UPDs as part of memory initialization BUG=none BRANCH=none TEST=Build dedede, flash and boot to kernel. Change-Id: I7248861efd1ecd5a0df0e17d39a44c168cab200e Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39136 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-02mb/google/kohaku: Add LPDDR 16G 2133 supportSeunghwan Kim
BUG=b:149775711 BRANCH=firmware-hatch-12672.B TEST=emerge-hatch coreboot Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Change-Id: I856d7b361e70b657966cd4036c79f2fedfabb766 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39126 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-02mb/**/dsdt.asl: Remove outdated sleepstates.asl commentAngel Pons
Previously, each Intel chipset had its own sleepstates.asl file. However, this is no longer the case, so drop these comments. This follows commit 408d1dac9e23250c0e485bbf934771f769b717c1. Change-Id: I0c0f4ad8bf743010ebdd2d53fcf297aeab64a662 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-02mb/**/dsdt.asl: Remove "Some generic macros" comment, againAngel Pons
It provides no useful information, so it might as well vanish. This follows commit 0142d441c63a9bb1a7955ea0ba764a2ddbc38d48. Change-Id: Iad41d8d39c6712cebfa5245f37bc69061b5ac552 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-02nb/intel/sandybridge: Fix VBOOTPatrick Rudolph
The VBOOT code can be compiled but it asserts with: ASSERTION ERROR: file 'src/security/vboot/common.c', line 40 Start VBOOT in bootblock to fix the assertion. Tested on Lenovo X220: The assertion is gone, the platform boots again. Change-Id: I48365e911b4f43aecba3b1f950178b7ceed5b2e9 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-03-02mb/google/octopus: support new Elan touch panel for FoobTommie
This is new elan touch screen IC, which includes touch panel and USI pen. BUG=b:149800883 BRANCH=octopus TEST=build bios and verify touch screen works fine Signed-off-by: Tommie Lin <tong.lin@bitland.corp-partner.google.com> Change-Id: Ibec3d08cc740e398a10a5c845181318724afc70a Reviewed-on: https://review.coreboot.org/c/coreboot/+/38823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Marco Chen <marcochen@google.com>
2020-03-02mb/google/hatch/var/jinlon: Disable EPS on some SKUsRajat Jain
Disable EPS on the SKUs that do not have it. Change-Id: I7305097beea3484634933ab856fd084933868a10 Signed-off-by: Rajat Jain <rajatja@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2020-03-02mb/google/hatch/var/jinlon: Enable gfx/generic driverRajat Jain
Enable the GFX device for Jinlon. Change-Id: I6ba90bf464e315ec364b6f35e7670924a2aba25a Signed-off-by: Rajat Jain <rajatja@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2020-02-28mainboard/google/volteer: Migrate onto SKU ID helpersEdward O'Callaghan
Leverage the common sku id space helper encoders. volteer uses the non-legacy SKU ID space. BUG=b:149348474 BRANCH=none TEST=only tested on hatch Change-Id: Ic66908afb7abb34527b4177cfd07f03ad718317c Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-28mainboard/google/hatch/puff: Toggle on TetonGlacierModeEdward O'Callaghan
Leverage in Puff to avoid diskswap variants. Later this could become part of the baseboard definition and hatch diskswap variants migrated over to use it as well. BUG=b:149171631 BRANCH=none TEST=Swap between x4 NVMe drives and 2x2 Teton Glacier hybrid drives and run lsblk, lspci, and nvme tools to confirm dynamic PCIe configuration on Puff. Change-Id: Ie87f0823f28457db397d495d9f1629d85cfd5215 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-28mainboard/google/hatch: Migrate onto SKU ID helpersEdward O'Callaghan
Leverage the common sku id space helper encoders. BUG=b:149348474 BRANCH=none TEST=tested on hatch Change-Id: I96e10010fd375b127f1e10387d6f7a839bc35fdd Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39019 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-27mb/google/hatch/var/jinlon: Configure GPP_E0 as outputRajat Jain
Configure GPP_E0 as output for view angle management Change-Id: Iad640eed855b47e365da55fa994c6a3c4c38caf9 Signed-off-by: Rajat Jain <rajatja@google.com>. Reviewed-on: https://review.coreboot.org/c/coreboot/+/39144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-02-27mb/google/dedede: configure ESPI IO decode range for chrome ECAamir Bohra
Configure below ESPI IO decode ranges: 1. 0x200-020F: EC host command range. 2. 0x800-0x8FF: EC host command args and params. 3. 0x900-0x9ff: EC memory map range. Change-Id: I1e450d6e45242180de715746b9852634de2669c6 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-02-27mb/google/dedede: Enable display supportAamir Bohra
1. Enable Internal Gfx device. 2. Configure DDI0 for EDP. 3. Configure HPD and DDC suppport for DDI1/DDI2. 4. Configure HPD GPIOs. TEST=Verify display on EDP panel in OS Change-Id: Ia53428af549ba01ab539f9474a6e5e79b72dff5c Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39132 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-26mb/google/hatch: reflow commentPatrick Georgi
Change-Id: I8c721c7ccba4f87d4acb9dae74213a46151fe2ed Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-26mainboard/hatch: Fix GPE wake commentsEdward O'Callaghan
The indirection of names is exceedingly confusing for ultimately the single interrupt trace of EC_PCH_WAKE_ODL between the EC gpio#74 to GPD2/LAN_WAKE# on the PCH side. This helps folks chase this indirection down through the code. BUG=b:147026979 BRANCH=none TEST=builds Change-Id: I35d746a202dae06d2f6f1edfaa3889864b09f50d Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-26mb/google/dedede: Update GPE configurationKarthikeyan Ramasubramanian
WWAN wake event is routed to GPP_D0 GPIO and Pen Detect wake event is routed to GPP_C12 GPIO. Update the GPE configuration accordingly. BUG=None TEST=Build the mainboard. Change-Id: Id36d2c8265a0b7ea241565f6bb723df6b37446fa Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-02-26treewide: capitalize 'USB'Elyes HAOUAS
Change-Id: I7650786ea50465a4c2d11de948fdb81f4e509772 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39100 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-26mb/google/dedede: Enable host bridge deviceAamir Bohra
Change-Id: Ie47265527b2b81748f4f3ad744d35cb81af17b80 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-02-26mb/google/fizz: allow 8 bit sku idsJeff Chase
Change-Id: I663678a4c572fe80298f7388870d5cd403122b98 Signed-off-by: Jeff Chase <jnchase@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2020-02-24mb/google: Fix typosElyes HAOUAS
Change-Id: I77c33c19b56dc9bd54e7555ce59f6a07bde3dbb6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-24gfx: Move drivers/generic/gfx to drivers/gfx/genericFurquan Shaikh
This change creates gfx directory under drivers/ so that all drivers handling gfx devices can be located in the same place. In follow-up CLs, we will be adding another driver that handles gfx devices. This change also updates the names used within the driver from *generic_gfx* to *gfx_generic*. In addition to that, mainboard drallion using this driver is updated to match the correct path and Kconfig name. TEST=Verified that drallion still builds. Change-Id: I377743e0f6d770eed143c7b6041dab2a101e6252 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2020-02-24mb/google/sarien: Remove MAC address pass throughDtrain Hsu
Remove MAC address pass through because when MAC address pass through setting change to "Use dock built-in MAC address", the MAC address always keeps the VPD value. BUG=b:149813043 TEST=tested on sarien and the result as below. (Option) (Result) - Use pre-assigned MAC address : Pass - Use Chromebook built-in address : Pass - Use dock built-in MAC address : Pass Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Ia85ef6ed0c4db82301375edd0968cf7dd2f62dc1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-02-24mb/google/drallion: Set GPP_G4 and GPP_G6 to NC pinEric Lai
Follow latest HW schematics to set GPP_G4 and GPP_G6 to NC pin. This can save 1mW power comsumption. BUG=b:149289256 TEST=NA Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ib3bf8b8f922a350d2b73ef5c9e9cf1b6e2c0f657 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-by: Mathew King <mathewk@chromium.org>
2020-02-24mb/google/{auron,slippy}/ec: clear pending events on S3 wakeupMatt DeVillier
Commit 6ae8b50 [chromeec: Depend on events_copy_b to identify wake source] partially broke resume from suspend on Auron and Slippy variants when multiple events exist in the EC event queue. In the case of the device suspending manually and then subsequently having the lid closed, the device will be stuck in a resume/suspend/resume loop until the device is forcibly powered down. Mitigate this by clearing any pending EC events on S3 wakeup. Test: build/boot several Auron/Slippy variants, test suspend/resume functional with both single and multiple events in EC event queue. Change-Id: I7ec9ec575d41c5b7522c4e13fc32b0b7c77d20d9 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-02-24mb/google/dedede: Add waddledoo variantKarthikeyan Ramasubramanian
Add initial support for waddledoo board. BUG=None TEST=Build the mainboard and variant board. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I8ab4d52c97b1cfb5549d2fce4b931748a1b1ff1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/38857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-24mb/google/dedede: Add EMMC configurationKarthikeyan Ramasubramanian
Turn on EMMC device and enable the HS400 mode. Configure the GPIOs associated with EMMC. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ic27c68f4622eec5b2930dc38186b82d895d3f67c Reviewed-on: https://review.coreboot.org/c/coreboot/+/38856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2020-02-24mb/google/dedede: Add USB configurationKarthikeyan Ramasubramanian
Add USB port configuration in devicetree. Configure USB Over-Current (OC) GPIOs. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I19f7563013c7d702d52b7f34a207a34abe308621 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2020-02-24mb/google/drallion: Remove MAC address pass throughDtrain Hsu
Remove MAC address pass through because when MAC address pass through setting change to "Use dock built-in MAC address", the MAC address always keeps the VPD value. BUG=b:147994020 TEST=tested on drallion and the result as below. (Option) (Result) - Use pre-assigned MAC address : Pass - Use Chromebook built-in address : Pass - Use dock built-in MAC address : Pass Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I1f58e98187feb4e428ca75f7e82c464567528526 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Mathew King <mathewk@chromium.org>
2020-02-18volteer: allow empty SPD_SOURCESPaul Fagerburg
Some Volteer variants might not use SPD files. Allow SPD_SOURCES in spd/Makefile.inc to be empty. BUG=None BRANCH=None TEST=Build coreboot and see that it builds without error Signed-off-by: Paul Fagerburg <pfagerburg@google.com> Change-Id: I5a8231b999e16503867d3c8df571b11fa0c1f6a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-17treewide: capitalize 'BIOS'Elyes HAOUAS
Also replace 'BIOS' by coreboot when the image is 'coreboot.rom'. Change-Id: I8303b7baa9671f19a036a59775026ffd63c85273 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-17mb/google/slippy: Fix IRQ of the ambient light sensorNicolò Veronese
Change based on google/auron that is similar to peppy. This will be helpful for the next follow-up commit that will add ACPI for the ambient light sensor. Change-Id: Ib2a8356d261d211d5ed5c0b035c94ec56b9c25b3 Signed-off-by: Nicolò Veronese <nicveronese@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-02-17mb/google/drallion/variants/drallion: Update thermal configuration for DPTFJohn Su
Follow thermal table for fine tuning. 1. Update PSV values for sensors. 2. Change PL1 min value from 4W to 5W. 3. Change PL1 max value from 15W to 12W. 4. Change PL2 min value from 15W to 12W. BUG=b:148627484 TEST=Built and tested on drallion Change-Id: I957d41e3c14f6dbcec8c3555382895698beabe40 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2020-02-17mb/google/drallion: Set cpu_pl2_4_cfg to baseline for DrallionJohn Su
Proper VR settings will be selected by CPU SKU and cpu_pl2_4_cfg. BUG=b:148912093 BRANCH=None TEST=build coreboot and checked IA_TDC from TAT tool. Change-Id: Ie471dee0c70e1831a822860c0a44455772a2b8be Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Mathew King <mathewk@chromium.org>
2020-02-17mb/google/octopus/variants/dood: add two new SKU IDsKenneth Chan
add SKU ID 3 and 4 for dood DVT 1: Dood WiFi + LTE (evt) 2: Dood WiFi (evt) 3: Dood WiFi + LTE + dual camera (dvt) 4: Dood WiFi + dual camera (dvt) BUG=b:148988979 TEST=build firmware and verify on the DUT of sku 3 and 4 check LTE module is enabled or not Change-Id: If86efe2a2f7b2e165ad44220b6dd59e9080b5892 Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38730 Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-17mb/google/drallion: Correct USB3 OC pin configurationEric Lai
USB3 OC pin is configured for the wrong pin. Follow HW circuit (schematics) to set it correctly. BUG=b:147869924 TEST=USB function works well and OC function is corresponds to the right port. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I61234a2054ab52fa508482d3dd0f94b13f96a5c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38885 Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-17mb/google/puff: Enable SPD_READ_BY_WORD to short the boottimeJamie Chen
Puff uses the smbus to access the SPD of memory DIMMs. It will short the SPD reading time if enabling SPD_READ_BY_WORD. BUG=b:149360051 BRANCH=None TEST=build puff and boot up OS ran cbmem -t | grep FspMemoryInit Without this patch: 950:calling FspMemoryInit 643,199 (257,588) With this patch: 950:calling FspMemoryInit 477,714 (154,612) Signed-off-by: Jamie Chen <jamie.chen@intel.com> Change-Id: I161e8eb386ab604b16746f0deeecc3d6c9063c3a Reviewed-on: https://review.coreboot.org/c/coreboot/+/38848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-02-17mb/google/kukui: fine tune the video timing of panel-BOE_TV101WUM_N53Jitao Shi
Fine tune the video timing of panel-BOE_TV101WUM_N53 to avoid noise. The parameters are based on BOE NV101WUM-N53 preliminary product spec. BRANCH=kukui BUG=b:147378025 TEST=bootup pass Change-Id: Ia9e2cc90f233e87d712c2dc6f4441ca2e5423162 Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38401 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-26 05:23:35 +0000